JPH0267766A - Bipolar-type semiconductor switching device - Google Patents

Bipolar-type semiconductor switching device

Info

Publication number
JPH0267766A
JPH0267766A JP22111088A JP22111088A JPH0267766A JP H0267766 A JPH0267766 A JP H0267766A JP 22111088 A JP22111088 A JP 22111088A JP 22111088 A JP22111088 A JP 22111088A JP H0267766 A JPH0267766 A JP H0267766A
Authority
JP
Japan
Prior art keywords
region
short
anode
drain
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22111088A
Other languages
Japanese (ja)
Other versions
JPH0783120B2 (en
Inventor
Tadaharu Minato
忠玄 湊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22111088A priority Critical patent/JPH0783120B2/en
Publication of JPH0267766A publication Critical patent/JPH0267766A/en
Publication of JPH0783120B2 publication Critical patent/JPH0783120B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To enhance an ON characteristic and an OFF characteristic by a method wherein a separation groove is formed between an anode region on the anode side and a short drain region and these regions are wired independently so that a sufficiently high forward bias and a sufficiently high reverse bias can be applied during an ON operation and an OFF operation. CONSTITUTION:Anode wiring parts 9 and short region wiring parts 10 are formed individually in anode regions 2 and short drain regions 8; the anode regions 2 and the short drain regions 8 are separated by separation grooves 22. Thereby, a high forward bias and a high reverse bias can be applied between the anode regions 2 and the short drain regions 8 independently of a gate bias. When the high forward bias is applied and flowe 15 of electrons are injected toward the anode regions 2 from the short drain regions 8, holes are injected to a substrate 1 from the anode regions 2, and an ON operation is completed more quickly.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明はバイポーラ型半導体スイッチング装置に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipolar semiconductor switching device.

〔従来の技術〕[Conventional technology]

従来技術の例として、ドレインショート型IGBTを例
としてその構成を説明する。
As an example of the prior art, the structure of a drain short type IGBT will be explained as an example.

第8図に従来のドレインショート型I GBTの模式断
面図を示す。図中、(1)は高比抵抗半導体の基板(通
常はN−基、i )であり、この基板(1)に、ドレイ
ンとなるP型不純物拡散領域(以下陽極領域という)(
21,N+ソース領域となるN型不純物拡散領域(以下
陰極領域という)(3)が形成されている。陽極領域(
2)−陰極領域(3)間を流れる主電流四の、オン、オ
フを制御するゲート(5)がゲート絶縁膜(6)を介し
て、主電流(2)の通路となるP型不純物拡散領域(4
)C以下Pウェルという)甲のNチャネル領域(6)上
に形成されている。陰極領域(3)はPウェル(4)と
ショートした形で、陰極配線(7)のように金属配線さ
れる。陽極領域(2)(ドレイン)も、基板(1)とシ
ョートした形で形成されているN型不純物領域(8)(
以下ショートドレイン領域という領域)とショートした
形で陽極配線(9)される。このように、陽極領域(2
)(ドレイン)に、ショートドレイン領域(8)をショ
ートした形で形成するので、一般にドレインショート型
と呼ばれている。
FIG. 8 shows a schematic cross-sectional view of a conventional short drain type IGBT. In the figure, (1) is a high resistivity semiconductor substrate (usually N-based, i), and this substrate (1) has a P-type impurity diffusion region (hereinafter referred to as an anode region) that becomes a drain.
21, an N-type impurity diffusion region (hereinafter referred to as a cathode region) (3) serving as an N+ source region is formed. Anode area (
2) P-type impurity diffusion where the gate (5), which controls the on/off state of the main current flowing between the cathode region (3) and the cathode region (3), becomes a path for the main current (2) through the gate insulating film (6) Area (4
) It is formed on the N channel region (6) of the instep (hereinafter referred to as P well). The cathode region (3) is short-circuited with the P-well (4) and is metal wired like a cathode wire (7). The anode region (2) (drain) also has an N-type impurity region (8) (which is formed short-circuited with the substrate (1)).
The anode wiring (9) is connected in a short-circuited manner to a region (hereinafter referred to as a short drain region). In this way, the anode region (2
) (drain) and the short drain region (8) is formed in a short-circuited manner, so it is generally called a drain short type.

次に、ドレインショート型IGBTの動作について説明
する。
Next, the operation of the drain short type IGBT will be explained.

まずオン動作は正電圧をゲート(5月こ印加することに
よって、Pウェル(4)の基板(1)表面に近い部分が
Nチャネル領域(ロ)となり、ターンオンが始まる。
First, in the on operation, by applying a positive voltage to the gate, the portion of the P well (4) close to the surface of the substrate (1) becomes an N channel region (b), and turn-on begins.

Nチャネル領域qυを介して、陰極領域(3)(ソース
)から、Nベースとなる基板(1)へ電子の注入が起こ
り、これに伴い、陽極領域(2)(ドレイン)より、ホ
ールが注入される。オン動作が完了すれば、Nベース層
である基板+11内にキャリアの蓄積が起こり、本来高
比抵抗層であった基板(1)が導電率変調を起こして、
オン抵抗が通常のパワーMOS F ETに比べて一桁
程度小さ(なる。
Through the N channel region qυ, electrons are injected from the cathode region (3) (source) to the substrate (1), which becomes the N base, and along with this, holes are injected from the anode region (2) (drain). be done. When the ON operation is completed, carriers accumulate in the substrate +11, which is the N base layer, and the substrate (1), which was originally a high resistivity layer, undergoes conductivity modulation.
The on-resistance is about an order of magnitude smaller than that of a normal power MOS FET.

次に、オフ動作はゲート(5)に印加している電圧を取
り去りゼロにすることによって行われる。ゲート(5)
 f[圧がゼロになると、Nチャネル領域(ロ)が消失
し、元のPウェル(4)にもどるので、陰極領域(3)
から基板(1)のベース領域への電子の注入が断たれオ
フ状態へと移行し、最終段階ではP型不準物領域のPウ
ェル(4)と基板(1)のN−領域に形成される空乏層
が、陽極領域(2)の手前まで、基板(1)全体に広が
り、オフ動作が完了する。それまでの、過渡状態におい
て、基板(1)中には、ホールが残ってオリ、かすかな
がら、陽極領域(2)と基板(1)及びPウェル(4)
 (P−ス)のP型不純物領域で形成されるPNP ト
ランジスタにホール電施が流れることになる。このNチ
ャネルが消失してから、オフ動作が完了するま;でのP
NP トランジスタに電流が流れている時間を、テール
時間(itall)  と呼ぶ、スイッチング損失を考
える場合、このttiHの間は主電圧は回復してきて8
す、ttiHが長くなるほどオフ時の電力損失は太き(
なり、最悪の場合、素子の破壊につながる。従って、j
tallは小さけれハ小さい程良い。ショートドレイン
領域(8)のN十不純物領域はGTO(ゲートターンオ
フサイリスタ)のエミッタ短絡構造を真ねLものであり
、jtallを小さくする目的で設けられπ部分である
。tlllの間に、基板(1)甲に残存しているキャリ
アのうち、電子はN+のショートドレイン領域(8]に
流れ込み電子濃度が減小するので、基板(1)中の電気
的中性条件を保つために、ホール濃度も減少する。した
がって、Lt&目がショートドレイン領域(8)を設け
ないときよりも設けたときの方が小さ(なる。また、シ
ョートドレイン領域・(8)を設けることによって、−
素子に占める陽極領域(2)の割合が小さくなることも
副次的はtailの減少効果に寄与している。
Next, the off operation is performed by removing the voltage applied to the gate (5) and making it zero. Gate (5)
f [When the pressure becomes zero, the N channel region (b) disappears and returns to the original P well (4), so the cathode region (3)
The injection of electrons into the base region of the substrate (1) is cut off and the state shifts to an off state, and in the final stage, electrons are formed in the P well (4) of the P-type impurity region and the N- region of the substrate (1). The depletion layer spreads over the entire substrate (1) up to this side of the anode region (2), and the OFF operation is completed. Until then, in the transient state, holes remained in the substrate (1), and the holes formed in the anode region (2), the substrate (1), and the P-well (4) were faint.
The hole current flows to the PNP transistor formed of the P-type impurity region (P-s). After this N channel disappears until the off operation is completed;
The time during which current flows through the NP transistor is called the tail time (ital).When considering switching loss, the main voltage recovers during this ttiH period.
The longer ttiH, the greater the power loss when off (
In the worst case, this may lead to destruction of the element. Therefore, j
The smaller the tall, the better. The N1 impurity region of the short drain region (8) is exactly the same as the emitter short circuit structure of a GTO (gate turn-off thyristor), and is a π portion provided for the purpose of reducing jtall. During tllll, electrons among the carriers remaining in the substrate (1) A flow into the N+ short drain region (8) and the electron concentration decreases, so that the electrically neutral condition in the substrate (1) is reduced. In order to maintain the short drain region (8), the hole concentration also decreases. Therefore, when the short drain region (8) is provided, Lt& is smaller (becomes smaller) than when the short drain region (8) is provided. By, −
The smaller proportion of the anode region (2) in the element also contributes to the tail reduction effect.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のドレインショート型IGBTは以上のように構成
されていたので次のような問題点がJ)つた。
Since the conventional drain short type IGBT was constructed as described above, it had the following problems.

第1に、従来の形のショートドレイン領域はターンオフ
時には機能するが、オン動作に無用のものであるだけで
な(、むしろオン特性を阻害する働きを持っている。タ
ーンオンの初期過程は上記のごとく、ゲート順バイアス
によるNチャネル領域の形成に支配されるが、ターンオ
ンはドレイン領域の陽極領域から注入されたホールが陰
極領域に到達することをもって完了する。したがって、
陽極領域側からのホールの注入効率によって、支配され
るものである。ホールの注入効率はP 不純物領域の濃
度、及び面積の関数と考えられるので、陽極領域の一素
子当りに占める面積が大きいほど良い。しかし、ショー
トドレイン領域を設けることにこって、陽極領域の面積
は大幅に縮小され、かつ、陽極領域とN のショートド
レイン領域の界面近傍は、ドレインあるいはショートド
レインとしての機能を失い、また、陽極領域より、基板
に注入されたホールの一部はN+のショートドレイン領
域へと流れ込み、陰極領域へ到達せずに消滅してしまう
First, although the conventional type of short drain region functions during turn-off, it is not only useless for the on operation (in fact, it has the function of inhibiting the on characteristics. The initial process of turn-on is as described above. The turn-on is dominated by the formation of the N channel region due to gate forward bias, but turn-on is completed when the holes injected from the anode region of the drain region reach the cathode region.
This is controlled by the hole injection efficiency from the anode region side. Since the hole injection efficiency is considered to be a function of the concentration and area of the P 2 impurity region, the larger the area of the anode region per element, the better. However, by providing the short drain region, the area of the anode region is significantly reduced, and the area near the interface between the anode region and the N2 short drain region loses its function as a drain or short drain, and Some of the holes injected into the substrate flow into the N+ short drain region and disappear without reaching the cathode region.

第2に、従来の形のショートドレイン領域はオン抵抗に
も悪影響を及ぼす。すなわち、オン状態が完了し、キャ
リγの蓄積が基板内で起・つてもN+のショートドレイ
ン領域近傍ではホール密度が減少するために、低抵抗領
域が、ショートドレイン領域のない場合に比べて小さ(
なる。
Second, conventionally shaped short drain regions also have a negative impact on on-resistance. In other words, even when the on-state is completed and carry γ is accumulated in the substrate, the hole density decreases near the N+ short drain region, so the low resistance region is smaller than when there is no short drain region. (
Become.

第3に、従来の形のショートドレイン領域では、オフ時
に充分な機能を発揮しているとは言えない状態にある。
Thirdly, the conventional type of short drain region cannot be said to exhibit sufficient functionality when turned off.

ttiH時、ショートドレイン領域のごく近傍のホール
濃度は、電子かN のショートドレイン領域に流れ込む
ことによって電気的中性条件を保つために減少するが陽
極領域(ドレイン)−陰極領域(ソース)間の電位勾配
が大きい1こめに、大半の残存ホールは、陰極側のPウ
ェルへと流れて行(ことになる。陽極とショートドレイ
ン領域を配線ショートしただけでは、ショートドレイン
領域のホールに対する有効領域は非常に限られており不
充分であると言える。
During ttiH, the hole concentration in the immediate vicinity of the short drain region decreases to maintain electrically neutral conditions by flowing into the short drain region of N2, but the hole concentration between the anode region (drain) and the cathode region (source) decreases. When the potential gradient is large, most of the remaining holes flow to the P-well on the cathode side. It can be said that it is extremely limited and insufficient.

このように従来形のドレインショート型rGBTはオン
特性、オフ特性の両方に問題点を持っていたわけであり
、これは、アノード側にN+領領域短絡構造を持つ単ゲ
ートSlサイリスタ、 GTOサイリスタなど、すべて
のバイポーラ型半導体スイッチング装置に共通な問題点
であった。
In this way, conventional drain short type rGBTs have problems in both on and off characteristics, and this is due to the problems faced by single-gate Sl thyristors, GTO thyristors, etc., which have a short-circuited N+ region on the anode side. This is a problem common to all bipolar semiconductor switching devices.

上記のような問題を解決するために、第9図及び第10
図のドレインショート型IGBTの模式断面図に示すよ
うにri!I極領域色領域−トドレイン領域を独立に配
線したものがある(特許出願中)。図において(1)〜
(9)、(6)は第8図の従来例に示したものと同等で
ある。OGはショート領域配線、卿は高比抵抗領域であ
る。しかし第9図及び第1θ図に示すものにおいては、
陽極領域(2)とショートドレイン(8)の逆バイアス
が素子設計上充分高くとれないと云う問題点があった。
In order to solve the above problems, Figures 9 and 10
As shown in the schematic cross-sectional view of the drain short type IGBT in the figure, ri! There is one in which the I-pole area, color area and drain area are independently wired (patent pending). In the figure (1) ~
(9) and (6) are equivalent to those shown in the conventional example of FIG. OG is a short-circuit region wiring, and OG is a high resistivity region. However, in what is shown in Fig. 9 and Fig. 1θ,
There was a problem in that the reverse bias between the anode region (2) and the short drain (8) could not be set sufficiently high due to device design.

すなわち第9図のように陽極領域がショートドレイン領
域と同一平面内に隣接して設けられているので、逆バイ
アス時に印加できる電圧は、陽極領域とショートドレイ
ン領域の不純物濃度が一定の場合は、この陽極領域とシ
ョートドレイン領域の距離によって決まり、この距離が
第10図のように大きいほど高い電圧が印加できる。こ
のことは、高い逆バイアスによる動作を行う場合、A子
面積が太き(なったり、逆に素子面積一定の場合には、
陽極領域、ショートドレイン領域の面積を小さくするな
どの制限が生れ、(高速スイッチング、低オン抵抗特性
と云う)本来の目的から遠ざかってしまうと云う問題点
をかかえていた。
In other words, as shown in FIG. 9, since the anode region is provided adjacent to the short drain region in the same plane, the voltage that can be applied during reverse bias is as follows: It is determined by the distance between this anode region and the short drain region, and the larger this distance is as shown in FIG. 10, the higher the voltage can be applied. This means that when operating with a high reverse bias, the A element area becomes large (or, conversely, when the element area is constant,
This has resulted in limitations such as reducing the area of the anode region and the short drain region, which has led to the problem of moving away from the original objectives (high-speed switching and low on-resistance characteristics).

この発明は、上記のような問題点を解消するためになさ
れたもので、オン特性オフ特性の両方の向上をはかるこ
とのできるバイポーラ型半導体スイッチング装置を得る
ことを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a bipolar semiconductor switching device that can improve both on-characteristics and off-characteristics.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、アノード側のN+ショー
ト領域をアノード領域と分amを形成して各々の領域を
絶縁して配線したものである。
In the semiconductor device according to the present invention, the N+ short region on the anode side is separated from the anode region am, and each region is insulated and wired.

〔作用〕[Effect]

この発明における半導体チイッチング装置は、アノード
側のN のショートドレイン領域がriIJ極領域占領
域分離して配線されたことにより、オン及びオフ動作時
に、陽極領域−ショートドレイン領域間に順・逆バイア
スが印加でき、ターンオン時間、ターンオフ時間をそれ
ぞれ短縮する。更に、N+のショートドレイン領域と陽
極領域が分離溝によって分離されているので、充分に高
い順逆バイアスが印加ができるので一層、スイッチング
特性が向上する。
In the semiconductor switching device of the present invention, the N2 short drain region on the anode side is wired to separate the riIJ pole region, so that forward and reverse biases are applied between the anode region and the short drain region during on and off operations. can be applied, reducing turn-on time and turn-off time. Furthermore, since the N+ short drain region and the anode region are separated by the isolation trench, a sufficiently high forward and reverse bias can be applied, further improving the switching characteristics.

〔実施例〕〔Example〕

以下、この発明の一実施例について、第、1図にした、
ドレインショート型I GBTの模式断面図を用いて説
明する。第1図は大面において第8図の従来例と同じで
あり、図中(1)〜@は@8図及び第9図に示したもの
と同等であるので説明は省略する。異なるのは、陽極領
域(2)とショートドレイン領域(8)の、各々に陽極
配線(9)及びショート領域配線QQを設け、かつ、陽
極領域(2)とショートドレイン領域(8)を分離溝(
ロ)によって分離したことである。
Hereinafter, one embodiment of the present invention will be explained as shown in FIG.
This will be explained using a schematic cross-sectional view of a short drain type IGBT. FIG. 1 is largely the same as the conventional example shown in FIG. 8, and since (1) to @ in the figure are equivalent to those shown in FIG. 8 and FIG. 9, their explanation will be omitted. The difference is that the anode region (2) and the short drain region (8) are each provided with an anode wiring (9) and a short region wiring QQ, and the anode region (2) and the short drain region (8) are separated by a trench. (
(b)).

この分離溝(2)によって、ゲートバイアスとは独立に
、陽極領域(2)−ショートドレイン領域(8)間に高
イア111i・逆バイアスを印加することが可能になる
This separation groove (2) makes it possible to apply a high IA 111i and reverse bias between the anode region (2) and the short drain region (8) independently of the gate bias.

次に動作について、オン動作は第2図を用いて、オフ動
作は第3図を用いて説明する。
Next, regarding the operation, the ON operation will be explained using FIG. 2, and the OFF operation will be explained using FIG. 3.

第2図は、第1図に示すI GBTのオン動作の初期過
程を表わす断面図であり、(12a)は陽極領域(2)
−ショートドレイン領域(8)間に順バイアスを印加す
る順バイアス*S、α4011はいずれも模式的に表わ
した電子の流れである。オン動作の開始は従来技術の説
明で述べた如く、ゲート(5)に正電圧を印加すること
によって行なわれる。ゲート(6)に正電圧を印加した
だけでは、陽極領域(2)からホールの注入は起らず陰
極領域(3)からチャネルを通じて基板(1)に流れ込
む電子の流れσぐが、陽極領域(幻に到達して始めて、
陽極領域(2)からホールの注入が開始される。したが
って、陰極領域(3)を出発した電子が基板(1)中を
陽極領域(2)まで進む時間が必要である。そこで、陽
極領域(2)−ショートドレイン領域(8)間に高い順
バイアスを印加することにより、ショートドレイン領域
(8)より陽極領域(2)に向けて速やかに電子の流れ
(至)を注入すると、陰極領域(3)からの電子の到着
を待つまでもな(、陽極領域(2)から基板(1)へと
ホールが、ジョートドにイン領域(8)からWh極極減
域2)へ注入された電子の流れ(イ)に引き寄せられて
、注入される。その結果、陽極領域(2)−ショートド
レイン領域(8)間がゼロ又は小さな順バイアスである
ときに比べてより早くオン動作が完了する。
FIG. 2 is a cross-sectional view showing the initial process of turning on the IGBT shown in FIG.
-Forward bias *S and α4011 for applying a forward bias between the short drain region (8) are electron flows schematically represented. The ON operation is started by applying a positive voltage to the gate (5), as described in the description of the prior art. Simply applying a positive voltage to the gate (6) does not cause hole injection from the anode region (2), and electrons flow from the cathode region (3) through the channel into the substrate (1), but the anode region ( Only after reaching the illusion,
Hole injection starts from the anode region (2). Therefore, time is required for the electrons leaving the cathode region (3) to travel through the substrate (1) to the anode region (2). Therefore, by applying a high forward bias between the anode region (2) and the short drain region (8), a flow of electrons is rapidly injected from the short drain region (8) toward the anode region (2). Then, without waiting for the arrival of electrons from the cathode region (3), holes are injected from the anode region (2) to the substrate (1) and from the in region (8) to the wh polar depletion region 2). They are attracted to the flow of electrons (a) and are injected. As a result, the ON operation is completed more quickly than when the forward bias between the anode region (2) and the short drain region (8) is zero or small.

第3図は、第1図に示すI GBTのオフ動作の申・後
半の過程を表わす断面図であり、 (xzb)は陽極領
域(2Jとショートドレイン領域(8J間の逆バイアス
電源、(財)はPウェル(4)側より基板(1)甲へ延
び始めた空乏層を表わす。(至)はホールの流れ、αη
は電子の流れを模式的に表わす。オフの場合も始めは従
来技術の説明の場合と同じく、ゲート(5)の正電圧を
取り去ってやれば、Nチャネル領域(6)は消失し、陰
極領域(3)からの電子の注入はなくなり、Pウェル(
4)を含めたP 領域より空乏ahが図示のように拡が
り始める。基板(1)甲にとり残されたホールは、PN
P )ランジスタのコレクターに相当するPウェル(4
)などのP 領域へホールの流れαQとなって流れ込む
。このとき、陽極領域(2)−ショートドレイン領域(
8)間に、充分高い逆バイアス電源(12b)を印加し
てやれば、基板(1)中の残存電子のかなりの部分がシ
ョートドレイン領域(8)へと流れ込ひ。そのために、
従来技術のショートドレイン構造によるホールの中和と
いうような消極的な方法ではなく、余剰電子の掃き出し
く引き出し)という積極的な方法でターンオフ時間、特
にjtallを短縮することができる。このttail
を短縮する効果は、ショートドレイン領域(8)から電
子の引き出しという形で、両面ゲートSIサイリスタの
第2ゲートと同様な働きが期待できる。
FIG. 3 is a cross-sectional view showing the first and second half of the off operation of the IGBT shown in FIG. ) represents the depletion layer starting to extend from the P-well (4) side to the substrate (1) A. (to) represents the flow of holes, αη
schematically represents the flow of electrons. In the off-state, as in the explanation of the prior art, if the positive voltage of the gate (5) is removed, the N-channel region (6) disappears and electron injection from the cathode region (3) ceases. , P-well (
The depletion ah begins to expand from the P region including 4) as shown in the figure. The holes left on the board (1) are PN
P) P well (4) corresponding to the transistor collector
) etc. flow into the P region as a flow of holes αQ. At this time, anode region (2) - short drain region (
8) If a sufficiently high reverse bias power supply (12b) is applied during this period, a considerable portion of the remaining electrons in the substrate (1) will flow into the short drain region (8). for that,
The turn-off time, particularly jtall, can be shortened not by a passive method such as neutralizing holes using the short drain structure of the prior art, but by an active method of sweeping out excess electrons. This tail
The effect of shortening is the extraction of electrons from the short drain region (8), which can be expected to have the same effect as the second gate of a double-sided gate SI thyristor.

更に、従来のショートドレイン構造におけるショートド
レイン領域(8)より、この発明におけるショートドレ
イン領域(gJの方がターンオフ動作に対してはるかに
有効に働(1こめ、従来のショートドレイン領域(8)
が−素子に対して占めていた面積の割合を小さくするこ
とが可能である。その結果、陽極領域(2)の面積を増
やすことが可能となり、陽極領域(2)からのホールの
注入効率が向上し、オン動作時の順バイアス効果に加え
て、更に一段のオン特性及びオン抵抗の改善がはかれる
Furthermore, the short drain region (gJ) in the present invention works much more effectively for the turn-off operation than the short drain region (8) in the conventional short drain structure (1).
It is possible to reduce the ratio of the area occupied by the - element to the - element. As a result, it is possible to increase the area of the anode region (2), improving the efficiency of hole injection from the anode region (2), and in addition to the forward bias effect during on operation, further on characteristics and on The resistance can be improved.

このように、オン動作時に順バイアス電i (12,)
を印加することによって従来、オン動作には悪影響を及
ぼす等のショートドレイン領域(8)が積極的にオン特
性を向上させ、かつ、オフ動作時にも、従来の消極的な
方法に代って積極的にオフ特性を向上させ、また、副次
的にも、オン−オフのトレードオフの良い素子設計を可
能にすることが出来る。
In this way, the forward bias voltage i (12,)
By applying , the short drain region (8), which conventionally had a negative effect on on operation, actively improves the on characteristics, and also during off operation, instead of the conventional passive method, the short drain region (8) can be actively improved. The off-state characteristics can be improved primarily, and as a side effect, element design with good on-off trade-off can be achieved.

なお、上記第1図、第2図及び第3図に示した実施例で
は、陽極領域(2ンとショートドレイン領域(8)を分
離溝により分離して配置した場合を示したが、分離溝で
のもれ電流を小さくシ、安定した状態で大きな逆バイア
ス’;1111174 (12b)を印加する場合には
、第4図に示し1こように、陽極領域(2)−ショート
ドレイン領域(8)間の分離# @をポリシリコン等の
絶は物で埋め合せた方が良い。第4図はこの発明の他の
実施例によるI GBTの断面図で(1)〜(6)は第
1図に示したものと同等である。勾は埋め合わせ絶縁物
である。分離溝(財)を埋め合わせ絶縁物(2)により
埋め合せる;ことによって、素子の機械的な破壊強度も
増加するので、その意味からは、基板(1)と似かよっ
た物理的性質を有する物′R(例えば基板(1)がSi
であればポリシリコン)が良いと考えられるが、素子の
大きさが比較的小さい(数鴫角程度)であれば、ポリイ
ミドのような有機高分子の液体を塗布して焼きしめる方
が工程的には簡便である。同じ意味あいから、SOG 
(5pin onGrass )の手法を用いることも
できる。
In the embodiments shown in FIGS. 1, 2, and 3, the anode region (2) and the short drain region (8) are separated by a separation groove. When applying a large reverse bias (12b) in a stable state while keeping the leakage current small, as shown in FIG. ) It is better to compensate for the separation # @ with an essential material such as polysilicon. Fig. 4 is a cross-sectional view of an IGBT according to another embodiment of the present invention, and (1) to (6) are the first It is equivalent to the one shown in the figure.The slope is the filler insulator.The isolation groove (material) is filled with the filler insulator (2); by doing so, the mechanical breakdown strength of the device is also increased. In terms of meaning, a substance 'R having similar physical properties to the substrate (1) (for example, if the substrate (1) is Si
However, if the size of the element is relatively small (about a few square meters), it is more convenient to apply an organic polymer liquid such as polyimide and bake it. It is easy to use. Because it has the same meaning, SOG
(5 pin on grass) method can also be used.

また、上記実施例では、ドレインショート型I GBT
について説明したが、この発明はパイポーラ型スイッチ
ング素子でアノード側にショート構造を有するもの全般
にわたって、適用可能である。
Further, in the above embodiment, the drain short type IGBT
However, the present invention is applicable to all bipolar switching elements having a short structure on the anode side.

以下にSlサイリスタ、GTOサイリスクダイオードの
場合について説明する。
The case of a Sl thyristor and a GTO thyrisk diode will be explained below.

第5図は、この発明の一実施例によるSlサイリスタの
断u図である。図において、(1)〜(6) * (7
) t(9) 、 Q(Jは第1図に示したものと同等
である。(2a)はアノード(P+不純物領域)、(3
a)はカソード(N+不純物領域) 、(8a)はショ
ートエミツパ夕(N+不純物領域)、嬶はゲートrp”
+続物領域)、QlはN−エピタキシャル層、(1)は
ゲート電極配線、(財)はN−高比抵抗のチャネル領域
を表わす。基本的なオン・オフ動作はそれぞれゲート(
ト)−力ソード(3a)間に順・純バイアスを印加し、
チャネル領域なυを空乏層によって開閉することによっ
て行われる。IGBTの場合と同様に、チャネルの開閉
に伴ない、アノード(2a)−ショートエミッタ(8a
)間に順・逆バイアスを印加して、オン・オフ動作を助
ける。また、第6図はこの発明の他の実施例によるSl
サイリスタで分離溝を埋め合わせ絶縁物(2)で埋め合
せた場合を示す断面図である。
FIG. 5 is a cut-away diagram of an Sl thyristor according to an embodiment of the present invention. In the figure, (1) to (6) * (7
) t(9), Q(J is the same as shown in Figure 1. (2a) is the anode (P+ impurity region), (3
a) is the cathode (N+ impurity region), (8a) is the short emitter (N+ impurity region), and is the gate rp”
Ql represents an N-epitaxial layer, (1) represents a gate electrode interconnection, and N- represents a high resistivity channel region. The basic on/off operations are gates (
G) Apply a forward/pure bias between the force sword (3a),
This is done by opening and closing the channel region υ using a depletion layer. As in the case of IGBT, as the channel opens and closes, the anode (2a) - short emitter (8a)
) to assist in on/off operation. Further, FIG. 6 shows an Sl according to another embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a case where the isolation trench is filled with a thyristor and an insulator (2).

第7図はこの発明の他の実施例によるGTOサイリスタ
を示す断面図である。図中、同一符号のものはSlサイ
リスタの第5図に示したものに相当する。GTOサイリ
スタの場合、主電流は、ゲート(至)を通りぬけてカソ
ード(3a)−アノード(2a) 間に流れる。
FIG. 7 is a sectional view showing a GTO thyristor according to another embodiment of the invention. In the figure, the same reference numerals correspond to the Sl thyristors shown in FIG. 5. In the case of a GTO thyristor, the main current flows between the cathode (3a) and the anode (2a) through the gate.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、アノード側の陽極領域
と、ショートドレイン領域を分離溝を設けて独立に配線
し、オンオフ時に充分高い順・逆バイアスが印加できる
ように構成したので、オン特性・オフ特性が向上し、か
つ、オン−オフ特性のトレードオフの取り易い半導体ス
イッチング装置が得られる効果がある。
As described above, according to the present invention, the anode region on the anode side and the short drain region are wired independently with a separation groove, and are configured so that sufficiently high forward and reverse biases can be applied during on/off, so that the on-state characteristics - There is an effect that a semiconductor switching device with improved off-characteristics and an easy trade-off between on-off characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例であるドレインショート型
、IGBT半導体スイッチング装置の断面図、第2図及
び第3図は第1図の半導体スイッチング装置の動作を説
明する断面図、第4図はこの発明の他の実施例であるド
レインショート型I GET半導体スイッチング装置の
断面図、第5図及び第6図はこの発明の他の実施例であ
るSlサイリスタの断面図、第7図はこの発明の他の実
施例であるGTOサイリスタの断面図、第8図、第9図
、第10図は従来のドレインショート型IGBT半導体
装置の断面図を示す。 図において、(1)は基板、(2月よ陽極領域、(2a
)はアノード(P+不純物領域) 、 (3)は陰極領
域、(3a)はカソード(N 不純物領域)、(4月よ
Pウェル、(5)はゲート、(6)はゲート絶縁膜、(
7)は陰極配線、(8月よショートドレイン領域、(8
a)はショートエミッタ(N+不純物領域)、(9)は
陽極配線、α〔はショート領域配線、αυはNチャネル
領域、(ロ)は主電流、α0國は電子の流れ、α呻はホ
ールの流れ、(ト)はゲートCP+不純物領域)、Ol
eはN−エピタキシャル層、勾はゲート電極配線、(2
)はチャネル領域、(支)は分am、に)は埋め合わせ
絶縁物、鱒は空乏層である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a cross-sectional view of a drain short type IGBT semiconductor switching device which is an embodiment of the present invention, FIGS. 2 and 3 are cross-sectional views explaining the operation of the semiconductor switching device of FIG. 1, and FIG. is a cross-sectional view of a drain short type I GET semiconductor switching device which is another embodiment of the present invention, FIGS. 5 and 6 are cross-sectional views of an Sl thyristor which is another embodiment of the present invention, and FIG. A sectional view of a GTO thyristor according to another embodiment of the invention, FIGS. 8, 9, and 10 show a sectional view of a conventional drain short type IGBT semiconductor device. In the figure, (1) is the substrate, (2a) is the anode region, (2a is
) is the anode (P+ impurity region), (3) is the cathode region, (3a) is the cathode (N impurity region), (April P well, (5) is the gate, (6) is the gate insulating film, (
7) is the cathode wiring, (August short drain region, (8)
a) is the short emitter (N+ impurity region), (9) is the anode wiring, α[ is the short region wiring, αυ is the N channel region, (b) is the main current, α0 is the flow of electrons, α is the hole Flow, (g) is gate CP + impurity region), Ol
e is the N-epitaxial layer, gradient is the gate electrode wiring, (2
) is the channel region; In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体基板をはさんで基板の裏面に第一の主電極とな
る第一の導電型領域を、上記半導体基板の表面に第二の
主電極となる第二の導電型領域を持つ、バイポーラ型半
導体スイッチング装置において、裏面の第一の主電極と
なる第一の導電型領域と独立に配線する制御電極となる
第二の導電型領域を、分離溝を介して裏面に設け、かつ
上記の分離溝の深さが、上記第一主電極となる第一導電
型の領域が広がる深さ及び、上記制御電極となる第二導
電型領域の広がる深さより深いことを特徴とするバイポ
ーラ型半導体スイッチング装置。
A bipolar semiconductor having a first conductivity type region serving as a first main electrode on the back side of the substrate across a semiconductor substrate, and a second conductivity type region serving as a second main electrode on the front surface of the semiconductor substrate. In the switching device, a second conductivity type region serving as a control electrode is provided on the back surface via a separation groove, and the second conductivity type region serving as a control electrode is wired independently from the first conductivity type region serving as the first main electrode on the back surface, and the above separation groove is deeper than the depth at which the first conductivity type region serving as the first main electrode extends and the depth at which the second conductivity type region serving as the control electrode extends.
JP22111088A 1988-09-01 1988-09-01 Bipolar semiconductor switching device Expired - Lifetime JPH0783120B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22111088A JPH0783120B2 (en) 1988-09-01 1988-09-01 Bipolar semiconductor switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22111088A JPH0783120B2 (en) 1988-09-01 1988-09-01 Bipolar semiconductor switching device

Publications (2)

Publication Number Publication Date
JPH0267766A true JPH0267766A (en) 1990-03-07
JPH0783120B2 JPH0783120B2 (en) 1995-09-06

Family

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Country Status (1)

Country Link
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US5289019A (en) * 1991-07-24 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate bipolar transistor
EP0599221A1 (en) * 1992-11-20 1994-06-01 Hitachi, Ltd. IGBT with bipolar transistor
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Cited By (26)

* Cited by examiner, † Cited by third party
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JPH0414263A (en) * 1990-05-07 1992-01-20 Fuji Electric Co Ltd Insulated gate type bipolar transistor
US5289019A (en) * 1991-07-24 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate bipolar transistor
EP0525587A1 (en) * 1991-07-29 1993-02-03 Siemens Aktiengesellschaft Field effect controllable semi-conductor device
EP0599221A1 (en) * 1992-11-20 1994-06-01 Hitachi, Ltd. IGBT with bipolar transistor
US5572048A (en) * 1992-11-20 1996-11-05 Hitachi, Ltd. Voltage-driven type semiconductor device
EP0634796A1 (en) * 1993-07-12 1995-01-18 Kabushiki Kaisha Toshiba Insulated gate bipolar transistor
US5485022A (en) * 1993-07-12 1996-01-16 Kabushiki Kaisha Toshiba High switching speed IGBT
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