JPH023980A - Perpendicular field effect transistor - Google Patents
Perpendicular field effect transistorInfo
- Publication number
- JPH023980A JPH023980A JP63153768A JP15376888A JPH023980A JP H023980 A JPH023980 A JP H023980A JP 63153768 A JP63153768 A JP 63153768A JP 15376888 A JP15376888 A JP 15376888A JP H023980 A JPH023980 A JP H023980A
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel region
- source
- channel
- source electrode
- Prior art date
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Links
- 230000005669 field effect Effects 0.000 title claims description 9
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 230000003071 parasitic effect Effects 0.000 abstract description 19
- 230000000694 effects Effects 0.000 abstract description 7
- 238000010276 construction Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 34
- 239000000758 substrate Substances 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は縦型電界効果トランジスタ(MOSFET)に
係る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to vertical field effect transistors (MOSFETs).
(従来の技術)
従来より知られている縦型MO8FETとしては、例え
ば第8図に示されている如き構造のものがある。これは
、UMO3FETと称されている構造のものであり、n
+型或いはp+型の基板1と、n″′型のドレイン領域
2と、p型のチャネル領域3と、n+型のソース領域4
と、ゲート電極5と、絶縁膜6と、ソース電極7と、フ
ィールドSiO□層8と、ゲートSiO2層(ゲート酸
化M)9とを有しており、前記ゲート電極5は、ソース
領域4とチャネル領域3とドレイン領域2の三つの領域
を貫通するU溝の内側壁に沿って設けられ、これに沿っ
てチャネル領域3に生じる反転層によるチャネル10の
発生を制御するようになっている。(Prior Art) A conventionally known vertical MO8FET has a structure as shown in FIG. 8, for example. This has a structure called UMO3FET, and n
+ type or p+ type substrate 1, n″′ type drain region 2, p type channel region 3, and n+ type source region 4
, a gate electrode 5, an insulating film 6, a source electrode 7, a field SiO□ layer 8, and a gate SiO2 layer (gate oxide M) 9, and the gate electrode 5 is connected to the source region 4. It is provided along the inner wall of the U-groove that penetrates the three regions of the channel region 3 and the drain region 2, and is designed to control the generation of the channel 10 by the inversion layer generated in the channel region 3 along this.
この構造のMOSFETに於ては、ソース領域4よりド
レイン領域2へ電流をチャネル10によってそれらの貫
層方向、即ち図にて垂直方向に流すことができ、これに
より微細加工により面積の増加をきたすことなく素子の
オン抵抗が低下すると云う利点が得られ、このtJMO
3FETは他の縦型MO3FETであるUMOSFET
よりも微細化限界が高いと云われている。In a MOSFET with this structure, current can be passed through the channel 10 from the source region 4 to the drain region 2 in the direction through these layers, that is, in the vertical direction in the figure, and this causes an increase in area due to microfabrication. This tJMO has the advantage of reducing the on-resistance of the device without
3FET is another vertical MO3FET, UMOSFET
It is said that the limit of miniaturization is higher than that of
上述の1MO8FETに於て、基板1の導電型がp+型
にされると、謂ゆるIGBT(伝導度変調型MO3FE
T)と称されている型式のMOSFETになる。このI
GBTは、特にn−型のドレイン領域2の比抵抗を高く
する必要がある高耐圧デバイスのオン抵抗を低下せしめ
るために有効な構造のものであり、従来より種々発表さ
れている。In the above-mentioned 1MO8FET, if the conductivity type of the substrate 1 is made p+ type, it becomes a so-called IGBT (conductivity modulated MO3FE).
This is a type of MOSFET called T). This I
The GBT has a structure that is effective for lowering the on-resistance of a high-voltage device in which the specific resistance of the n-type drain region 2 needs to be increased, and various GBTs have been published in the past.
(発明が解決しようとする課題)
しかしながら、上述の如き従来の縦型MO3FETにも
木質的な欠点がある。これは、ソース領域4とチャネル
領域3とドレイン領域2とにより寄生のnpn型トラン
ジスタが形成されることである。この寄生npn型トラ
ンジスタが動作すると、MOSFETは本来の動作を行
えなくなり、これはデバイス破壊の原因になる。(Problem to be Solved by the Invention) However, the conventional vertical MO3FET as described above also has a woody drawback. This means that a parasitic npn transistor is formed by the source region 4, channel region 3, and drain region 2. When this parasitic npn type transistor operates, the MOSFET cannot perform its original operation, which causes device destruction.
上述の縦型MO8FETに於ける寄生バイポーラ効果に
ついて第9図〜第12図を用いて詳しく説明する。The parasitic bipolar effect in the vertical MO8FET described above will be explained in detail using FIGS. 9 to 12.
第9−1図は第8図に示された1MO8FETと同じ1
MO8FETの要部を拡大して示している。尚、第9−
1図に於て、第1図に対応する部分は第1図に付した符
号と同一の符号により示されている。第9−1図に示さ
れている1MO8FETは、n+型の基板1をドレイン
電極とする通常型の0MO3FETであり、これは、ド
レイン領域2とチャネル領域3とソース領域4とによる
npn型トランジスタQpと、ベース抵抗rBと、ドレ
イン領域2とチャネル領域3との間のpn接合容量C4
とを含んでいる。またこれはソース電極7の真下にてチ
ャネル領域3とドレイン領域2とによるダイオードDi
を有している。従ってこのUMOSFETの等価回路は
第9−2図の如く示される。Figure 9-1 is the same 1MO8FET shown in Figure 8.
The main parts of MO8FET are shown enlarged. In addition, No. 9-
In FIG. 1, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. The 1MO8FET shown in FIG. 9-1 is a normal type 0MO3FET in which the n+ type substrate 1 is used as the drain electrode. , base resistance rB, and pn junction capacitance C4 between drain region 2 and channel region 3.
Contains. Also, this is a diode Di formed by the channel region 3 and the drain region 2 directly under the source electrode 7.
have. Therefore, the equivalent circuit of this UMOSFET is shown as shown in FIG. 9-2.
第9−2図より明らかな如く、寄生npn型トランジス
タQpのベースはベース抵抗rnを通じてソース電極7
に結ばれるから、トランジスタQpは定常時にはオフ状
態をとり、ドレイン−ソース間の電流バスはMOSFE
Tの本来のチャネルだけにて制御される。しかし第10
−1図に示されている如く、誘導負荷をスイッチングす
る時に発生ずるスパイク電圧、或いは第10−2図に示
されている如く、モータMのブリッジ駆動等にて発生す
る転流ノイズは、上述の寄生npn型トランジスタQp
を動作させるトリガとなる。スパイク電圧、転流ノイズ
は、ρn接合容1C」を通ってベース抵抗1”aに変位
電流を流し込む他に、これらの電圧がドレイン領域2と
チャネル領域3とのpn接合の耐圧(QpのBVcn−
に等しい)を越える時には、アバランシェブレークダウ
ンを引き起し、これもまたベース抵抗raに多大な電流
を流し、寄生npn型トランジスタQpを動作させるよ
うになる。−度、寄生npn型トランジスタQpが動作
すると、第11図に示されている如く、それの安全動作
領域ASOはバイポーラの二次降伏制限によりMOSF
ETのそれよりはるかに小さいから、エネルギーが大き
い時には瞬時に素子破壊が生じる虞れがある。As is clear from FIG. 9-2, the base of the parasitic npn transistor Qp is connected to the source electrode 7 through the base resistor rn.
Since the transistor Qp is connected to
Controlled only by T's original channel. But the 10th
As shown in Figure 1, the spike voltage that occurs when switching an inductive load, or as shown in Figure 10-2, commutation noise that occurs during bridge drive of motor M, etc. parasitic npn type transistor Qp
It becomes a trigger to operate. In addition to flowing a displacement current into the base resistor 1''a through the ρn junction capacitance 1C, these voltages cause the breakdown voltage of the pn junction between the drain region 2 and the channel region 3 (BVcn of Qp −
(equal to ), it causes avalanche breakdown, which also causes a large current to flow through the base resistor ra, causing the parasitic npn transistor Qp to operate. - degree, when the parasitic npn transistor Qp operates, its safe operating area ASO is limited to the MOSFET due to the bipolar secondary breakdown limit, as shown in FIG.
Since it is much smaller than that of ET, when the energy is large, there is a risk that the device will be destroyed instantly.
第12−1図は、p+型の基板1′を有する1MO8F
ET、即ちIGBTを示しており、これは上述の寄生n
pn型トランジスタQpに加え、基板1′とドレイン領
域2とチャネル領域3とによる寄生pnp型トランジス
タQnを含んでいる。Figure 12-1 shows a 1MO8F with a p+ type substrate 1'.
ET, or IGBT, which is free from the above-mentioned parasitic n
In addition to the pn-type transistor Qp, it includes a parasitic pnp-type transistor Qn formed by a substrate 1', a drain region 2, and a channel region 3.
このトランジスタQnは、第12−2図の等価回路でも
明らかな如く、もう一つのトランジスタQpとサイリス
タ結合(正帰還結合)しているから、上述の如きトリガ
によりトランジスタQpが動作すると、たちまち寄生サ
イリスタによりラッチアップが生じ、ターンオフできな
くなる。As is clear from the equivalent circuit in Figure 12-2, this transistor Qn is thyristor-coupled (positive feedback coupling) with another transistor Qp, so when the transistor Qp operates due to the above-mentioned trigger, the parasitic thyristor This causes latch-up and makes it impossible to turn off.
(発明の目的)
本発明は、従来の縦型MO3FETに於ける上述の如き
不具合に鑑み、寄生バイポーラ効果がなく、誤動作する
ことのない改良された縦型MO8FETを提供すること
を目的としている。(Objective of the Invention) In view of the above-mentioned problems in the conventional vertical MO3FET, an object of the present invention is to provide an improved vertical MO8FET that does not have parasitic bipolar effects and does not malfunction.
(課題を解決するための手段)
上述の如き目的は、本発明によれば、ソース領域をn型
半導体より金属或いはシリサイドに置き換えることによ
り達成され、本発明による縦型電界効果トランジスタは
、第一導電型のドレイン領域と、第二導電型のチャネル
領域と、前記チャネル領域を貫通して前記ドレイン領域
に達する溝を有し、前記溝の内側壁にゲート絶縁膜を介
して設けられたゲート電極によって前記チャネル領域の
電導状態を制御する縦型電界効果トランジスタに於て、
前記チャネル領域の一部にオーミック接合され且前記ゲ
ート絶縁膜に接するように設けられた金属或いはシリサ
イド製のソース電極を有し、前記ソース電極自体が電界
効果トランジスタのソース領域とされていることを特徴
としている。(Means for Solving the Problems) According to the present invention, the above objects are achieved by replacing the n-type semiconductor with metal or silicide for the source region, and the vertical field effect transistor according to the present invention has the following features: A gate electrode having a conductivity type drain region, a second conductivity type channel region, and a groove penetrating the channel region and reaching the drain region, and provided on an inner wall of the groove with a gate insulating film interposed therebetween. In a vertical field effect transistor in which the conduction state of the channel region is controlled by
A source electrode made of metal or silicide is provided in an ohmic contact with a part of the channel region and in contact with the gate insulating film, and the source electrode itself is used as a source region of a field effect transistor. It is a feature.
(実施例)
以下に添付の図を参照して本発明を実施例について詳細
に説明する。(Example) The present invention will be described in detail below with reference to the accompanying drawings.
第1図及び第2図は本発明による縦型電界効果トランジ
スタ(MOSFET>の一つの実施例を示している。尚
、第1図及び第2図に於ても第8図に対応する部分は第
8図に付した符号と同一の符号により示されている。1 and 2 show one embodiment of a vertical field effect transistor (MOSFET) according to the present invention. In addition, in FIGS. 1 and 2, the parts corresponding to FIG. They are indicated by the same reference numerals as those shown in FIG.
本発明による縦型MO3FETが従来型のものと異なっ
ているところは、従来のソース領域4に代えて金属或い
はシリサイドにより構成されたソース電極11がゲート
酸化M9に直接接触している点である。ソース電極11
はチャネル領域3とオーミック接合されており、チャネ
ル領域3に生じるチャネル10はソース電極11より直
接放出される電子によって形成されるようになる。The vertical MO3FET according to the present invention differs from the conventional type in that, instead of the conventional source region 4, a source electrode 11 made of metal or silicide is in direct contact with the gate oxide M9. Source electrode 11
is in ohmic contact with the channel region 3, and the channel 10 generated in the channel region 3 is formed by electrons directly emitted from the source electrode 11.
横型MO8FETに於ては、既にショットキーソース型
のデバイスが提案されているが、しかしこれは平面上に
てゲートとソースとの間を絶縁するため、該両者のオフ
セットが避けられず、このため素子のオン電圧、しきい
値電圧が高くなるという問題がある。For lateral MO8FETs, a Schottky source type device has already been proposed, but since the gate and source are insulated on a plane, an offset between the two is unavoidable. There is a problem that the on-state voltage and threshold voltage of the device become high.
これに対し本発明による縦aMosFErに於ては、縦
溝の内側壁面に形成されたSi酸化膜を絶縁膜として使
用しているから、オフセットを無くすことが可能になり
、しかもソース領域からドレイン領域に至るまでの酸化
膜は後述の製造プロセスからして明らかになるように、
シリコン基板そのものを酸化した極めて良貰の酸化膜で
あることが大きな利点となる。On the other hand, in the vertical aMosFEr according to the present invention, since the Si oxide film formed on the inner wall surface of the vertical trench is used as an insulating film, it is possible to eliminate the offset, and moreover, it is possible to eliminate the offset from the source region to the drain region. As will become clear from the manufacturing process described below, the oxide film up to
A major advantage is that it is an extremely high-quality oxide film made by oxidizing the silicon substrate itself.
第3−1図及び第3−2図はMOSFETのオン状態時
とオン状態時のエネルギーバンド図である。FIGS. 3-1 and 3-2 are energy band diagrams when the MOSFET is in the on state and when it is in the on state.
ゲート電極■。3がしきい値電圧Vthより低い時、即
ちVos<Vihである時にはMOSFETはオン状態
を示す。この時には、第3−1図に示されている如く、
金属ソースM(ソース電極11)とチャネル領域P(3
)との間にはφBnのバリヤが存在し、チャネル領域P
に対し電子の注入が行われない。従ってこの時にはチャ
ネル領域Pは非導通状態を保ち、ソース電極11とドレ
イン領域2との間にて電流は流れない。Gate electrode■. 3 is lower than the threshold voltage Vth, that is, when Vos<Vih, the MOSFET is in the on state. At this time, as shown in Figure 3-1,
Metal source M (source electrode 11) and channel region P (3
), a barrier of φBn exists between the channel region P
No electron injection takes place. Therefore, at this time, the channel region P remains non-conductive, and no current flows between the source electrode 11 and the drain region 2.
ゲート電圧■。3がしきい値電圧Vthより高い時、即
ちV。s>Vthである時にはMOSFETはオン状態
を示す。この時には、第3−2図に示されている如く、
チャネル領域Pのポテンシャルが低下し、ソース電極1
1よりチャネル領域Pに電子が直接注入され、これによ
りチャネル領域Pに反転層によるチャネル1.0が形成
される。チャネル10はソース電極11とドレイン領域
2とを接続する導通路となり、ソース電極11とドレイ
ン領域2との間にて電流が流れる。Gate voltage■. 3 is higher than the threshold voltage Vth, that is, V. When s>Vth, the MOSFET is in an on state. At this time, as shown in Figure 3-2,
The potential of the channel region P decreases, and the source electrode 1
Electrons are directly injected into the channel region P from the channel region P, thereby forming a channel 1.0 in the channel region P by an inversion layer. The channel 10 becomes a conductive path connecting the source electrode 11 and the drain region 2, and a current flows between the source electrode 11 and the drain region 2.
基板1がP+型基板により構成され、MOSFETがI
GBTをなしている場合には、基板1よリドレイン領域
2へ正孔が注入されて伝導度変調が生じ、オン抵抗が更
に低下するようになる。第4図はこのMOSFETの静
特性を示している。The substrate 1 is composed of a P+ type substrate, and the MOSFET is I
In the case of forming a GBT, holes are injected from the substrate 1 to the drain region 2, causing conductivity modulation, and the on-resistance further decreases. FIG. 4 shows the static characteristics of this MOSFET.
本発明によるMOSFETは、N+拡散層によるソース
領域を使用していないから、寄生バイポーラトランジス
タを含まない。従って本発明によるMOSFETの等価
回路は、第5−1図或いは第5−2図にて示され、理想
的なMOSFET或いはIGBTになる。本発明による
MOSFETは寄生バイポーラトランジスタを含まない
から、第6図に示されている如く、素子の安全動作領域
ASOがMO3本来の広い領域になる。The MOSFET according to the present invention does not include a parasitic bipolar transistor because it does not use a source region formed by an N+ diffusion layer. Therefore, the equivalent circuit of the MOSFET according to the present invention is shown in FIG. 5-1 or 5-2, and becomes an ideal MOSFET or IGBT. Since the MOSFET according to the present invention does not include a parasitic bipolar transistor, the safe operating area ASO of the device becomes a wider area than MO3, as shown in FIG.
IGBTに於ては、寄生バイポーラトランジスタを含ま
ないことから、ラッチアップ耐電が格段に向上し、これ
に加えてN−ドレイン領域2に対して正孔を充分に注入
することができるので、オン抵抗が従来のものに比して
著しく低下するようになる。尚、従来のIGBTに於て
は、ラッチアップの回避のために正孔注入を抑制したり
、ライフタイムキラーにより正孔濃度を制御しており、
オン抵抗を犠牲にしていた。Since the IGBT does not include a parasitic bipolar transistor, the latch-up resistance is greatly improved, and in addition, holes can be sufficiently injected into the N-drain region 2, so the on-resistance is reduced. becomes significantly lower than the conventional one. In addition, in conventional IGBTs, hole injection is suppressed to avoid latch-up, and the hole concentration is controlled using a lifetime killer.
On-resistance was sacrificed.
また本発明によるMOSFETに於ては、ソースN+拡
散が不要であるから、生産性も改善され、製造コストの
低減が図られる。Further, in the MOSFET according to the present invention, since source N+ diffusion is not required, productivity is improved and manufacturing costs are reduced.
次に第7図(a)〜(j)を用いて第1図に示されてい
る如き本発明によるMOSFETの製造手順の一例にに
ついて説明する。Next, an example of the manufacturing procedure of the MOSFET according to the present invention as shown in FIG. 1 will be explained using FIGS. 7(a) to (j).
(a)図に示されている如く、先ずn+基板、或いはp
+基板上にn−層をエピタキシャル成長させなウェハを
準備し、その上にSiO□膜を熱酸化により最大100
0人程度以下成長させ、更にその上に5iyN4膜をC
V−D法により堆積させ、溝形成用のマスクパターンを
形成する。尚、n−層の比抵抗及び厚さはデバイスの要
求ドレイン耐圧に応じて選定されればよく、要求ドレイ
ン耐圧が100V程度の場合には比抵抗は10Ω1、厚
さは10μm程度であってよい。(a) As shown in the figure, first the n+ substrate or the p
A wafer is prepared on which an n- layer is epitaxially grown on a + substrate, and a SiO□ film is deposited on it by thermal oxidation to
Grow less than 0.0 mL, and then add a 5iyN4 film on top of it.
It is deposited by the V-D method to form a mask pattern for forming grooves. Note that the resistivity and thickness of the n-layer may be selected according to the required drain withstand voltage of the device, and when the required drain withstand voltage is approximately 100 V, the resistivity may be 10Ω1 and the thickness may be approximately 10 μm. .
次に(b)図に示されている如く、反応性イオンエツチ
ングの手法によりn−層にほぼ垂直な溝を切る。この講
の深さは2,5μm程度であってよい。溝をライトエッ
チし、ダメージ層の除去を行つ。Next, as shown in Figure (b), a substantially perpendicular groove is cut in the n-layer by a reactive ion etching technique. The depth of this layer may be approximately 2.5 μm. Lightly etch the groove and remove the damaged layer.
次に(C)図に示されている如く、溝の内側壁面をドラ
イ酸化し、ゲート酸化膜(9)を成長させる。Next, as shown in Figure (C), the inner wall surface of the trench is dry oxidized to grow a gate oxide film (9).
ゲート酸化膜の厚さは1000人程度以下であってよい
。尚、Si3N4Mにより被覆されている部分は酸化さ
れない。The thickness of the gate oxide film may be about 1,000 or less. Note that the portion covered with Si3N4M is not oxidized.
次に(d)図に示されている如く、多結晶SiをCV−
D法によって堆積し、多結晶Siにより溝を埋める。Next, as shown in the figure (d), polycrystalline Si is
It is deposited by the D method and the grooves are filled with polycrystalline Si.
次に(e)図に示されている如く、多結晶Siをエッチ
バックし、溝内にのみ多結晶Siが残存するようにする
。Next, as shown in the figure (e), the polycrystalline Si is etched back so that the polycrystalline Si remains only in the grooves.
次にU)図に示されている如く、5tiN4層をマスク
として多結晶Siのみを選択酸化する。Next, as shown in Figure U), only the polycrystalline Si is selectively oxidized using the 5tiN4 layer as a mask.
この酸化層の厚さは5000人程度以下ってよい。The thickness of this oxide layer may be about 5,000 or less.
次に(g)図に示されている如く、熱リン酸により5i
5Na層を除去し、続けてチャネル領域形成予定部の5
fO2をエツチングしてn−層のSi表面を露出させる
。Next, (g) as shown in the figure, 5i
The 5Na layer is removed, and then the 5
Etch fO2 to expose the n-layer Si surface.
次に(h)図に示されている如く、n−層のSi表面を
ライトエッチし、溝の酸化膜を充分露出させる。ここで
、エツチング液として、ヒドラジン等のアルカリ系溶液
を使用すれば、SiO2だけを残してSiを除去できる
。Next, as shown in the figure (h), the Si surface of the n-layer is lightly etched to sufficiently expose the oxide film in the groove. Here, if an alkaline solution such as hydrazine is used as the etching solution, Si can be removed leaving only SiO2.
次に(i)図に示されている如く、n−層に対してB+
(ボロン)をイオン注入し、拡散することにより、チ
ャネル領域(3)を形成する。このチャネル領域(3)
の厚さは2μm程度であってよい。Next, (i) as shown in the figure, B+ for the n- layer.
A channel region (3) is formed by implanting (boron) ions and diffusing them. This channel area (3)
The thickness may be about 2 μm.
この工程はデバイスのしきい値電圧Vthを決定するも
のであり、表面不純物濃度が所望の値になるようにイオ
ン注入拡散条件を決める。尚、拡散深さはドレイン耐圧
でチャネル領域3がバンチスルーしない程度に定められ
ればよい。This step determines the threshold voltage Vth of the device, and the ion implantation and diffusion conditions are determined so that the surface impurity concentration becomes a desired value. Note that the diffusion depth may be determined to such an extent that the channel region 3 does not bunch through at the drain breakdown voltage.
次にl)図に示されている如く、ゲート電極(5)であ
る多結晶Si上の酸化膜の一部を開口(第2図にて符号
12により示す)してから電極金属を蒸着し、ソース電
極(11)とゲート用配線電極(第2図にて符号5′に
より示す)とを形成する。この後にソース電極(11)
とチャネル領域(3)をなすSiとをオーミック接合さ
せるための熱処理を行つ。Next, l) As shown in the figure, a part of the oxide film on the polycrystalline Si that is the gate electrode (5) is opened (indicated by reference numeral 12 in Figure 2), and then electrode metal is deposited. , a source electrode (11) and a gate wiring electrode (indicated by reference numeral 5' in FIG. 2) are formed. After this, the source electrode (11)
A heat treatment is performed to form an ohmic contact between the silicon layer and the Si forming the channel region (3).
ここで電極金属はチャネル領域との間にシリサイド合金
層やp型、n型の遷移領域を形成するが、この遷移領域
は可及的に薄いことが望ましい。なぜならば、この遷移
領域が厚くなると、しきい値電圧Vthが大きく変化し
、またオフセット電圧の原因となるからである。Here, a silicide alloy layer or a p-type or n-type transition region is formed between the electrode metal and the channel region, and it is desirable that this transition region be as thin as possible. This is because when this transition region becomes thicker, the threshold voltage Vth changes significantly and also causes an offset voltage.
従って電極金属は、W、Ti、Pt等の高融点金属であ
ることが好ましい。Therefore, the electrode metal is preferably a high melting point metal such as W, Ti, or Pt.
上述の製造手順例に於ては、熱処理後も金属を存在させ
ているが、シリサイド層だけを残存させ、金属を除去し
、新たにAI等により前記シリサイド層の一部だけ配線
電極を取り出しても同等の効果が得られる。この場合に
はシリサイド層がソースとして機能する。In the above manufacturing procedure example, the metal is left even after the heat treatment, but only the silicide layer remains, the metal is removed, and a new wiring electrode is taken out of only a part of the silicide layer using AI etc. The same effect can be obtained. In this case, the silicide layer functions as a source.
金属によっては、Siとの仕事関数の差が過大で、チャ
ネル領域(3)に対して直接にオーミック接合を取りに
くい場合があるが、この場合にはチャネル領域の一部に
高濃度拡散層を設ければよい。Depending on the metal, the difference in work function with Si may be too large and it may be difficult to form an ohmic contact directly with the channel region (3). Just set it up.
またソース領域となるゲート近傍のソース電極(11)
は、例えばショットキー接合の如きバリヤが存在しても
ゲート電圧による表面電位変調効果によって容易にその
バリヤが取り除けるため、問題はない。Also, the source electrode (11) near the gate which becomes the source region
For example, even if a barrier such as a Schottky junction exists, there is no problem because the barrier can be easily removed by the surface potential modulation effect of the gate voltage.
(発明の効果)
上述の如く、本発明によるMOSFETに於ては、ソー
ス領域が金属或いはシリサイドよりなるソース電極自体
により与えられているから、寄生バイポーラ効果が生じ
ることなく、MOSFETの性能が最大に発揮されるよ
うになり、しかも製造プロセスが簡単であるなめ、製造
コストの低減が図られる。(Effects of the Invention) As described above, in the MOSFET according to the present invention, since the source region is provided by the source electrode itself made of metal or silicide, the performance of the MOSFET is maximized without causing parasitic bipolar effects. Moreover, since the manufacturing process is simple, manufacturing costs can be reduced.
またゲート酸化膜がSi基板自体の一部を酸化した膜に
より構成されると、良質のゲート酸化膜が得られ、MO
SFETの性能が向上するようになる。Furthermore, if the gate oxide film is formed by oxidizing a part of the Si substrate itself, a high quality gate oxide film can be obtained, and MO
The performance of SFET will improve.
第1図は本発明によるMOSFETの一つの実施例を示
す構造図、第2図はその平面図、第3−1図及び第3−
2図はエネルギーバンド図、第4図は本発明によるMO
SFETの静特性を示すグラフ、第5−1図及び第5−
2図は各々本発明によるMOSFETの等価回路図、第
6図は本発明によるMOSFETの安全動作領域を示す
グラフ、第7図(a)〜(j)は本発明によるMOSF
ETの製造手順の一例を示す工程図、第8図は従来より
知られる1MO3FETを示す構造図、第9−1図は第
8図に示された1MO3FETの寄生デバイスを示す構
造図、第9−2図はその等価回路図、第10−1図及び
第10−2図は各々UMO3FETの使用例を示すブロ
ック線図、第11図はデバイスの安全動作領域を示すグ
ラフ、第12−1図はUMO8IGBTの寄生デバイス
を示す構造図、第12−2図はその等価回路図である。
1・・・基板
2・・・ドレイン領域
3・・・チャネル領域
4・・・ソース領域
5・・・ゲート電極
6・・・絶縁膜
7・・・ソース電極
8・・・フィールドSiO□層
9・・・ゲート5iQ2層(ゲート酸化膜)10・・・
チャネル
11・・・ソース電極
特許出願人 日産自動車株式会社FIG. 1 is a structural diagram showing one embodiment of a MOSFET according to the present invention, FIG. 2 is a plan view thereof, and FIGS. 3-1 and 3-
Figure 2 is an energy band diagram, and Figure 4 is an MO according to the present invention.
Graphs showing static characteristics of SFET, Figures 5-1 and 5-
2 is an equivalent circuit diagram of the MOSFET according to the present invention, FIG. 6 is a graph showing the safe operating area of the MOSFET according to the present invention, and FIGS. 7(a) to (j) are equivalent circuit diagrams of the MOSFET according to the present invention.
FIG. 8 is a structural diagram showing a conventionally known 1MO3FET, FIG. 9-1 is a structural diagram showing a parasitic device of the 1MO3FET shown in FIG. 8, and FIG. 9- Figure 2 is its equivalent circuit diagram, Figures 10-1 and 10-2 are block diagrams showing usage examples of UMO3FET, Figure 11 is a graph showing the safe operating area of the device, and Figure 12-1 is a graph showing the safe operating area of the device. A structural diagram showing a parasitic device of the UMO8 IGBT, and FIG. 12-2 is an equivalent circuit diagram thereof. 1... Substrate 2... Drain region 3... Channel region 4... Source region 5... Gate electrode 6... Insulating film 7... Source electrode 8... Field SiO□ layer 9 ...Gate 5iQ2 layer (gate oxide film) 10...
Channel 11... Source electrode patent applicant Nissan Motor Co., Ltd.
Claims (1)
ル領域と、前記チャネル領域を貫通して前記ドレイン領
域に達する溝を有し、前記溝の内側壁にゲート絶縁膜を
介して設けられたゲート電極によって前記チャネル領域
の電導状態を制御する縦型電界効果トランジスタに於て
、 前記チャネル領域の一部にオーミック接合され且前記ゲ
ート絶縁膜に接するように設けられた金属或いはシリサ
イド製のソース電極を有し、前記ソース電極自体が電界
効果トランジスタのソース領域とされていることを特徴
とする縦型電界効果トランジスタ。[Claims] 1. It has a drain region of a first conductivity type, a channel region of a second conductivity type, and a groove that penetrates the channel region and reaches the drain region, and a gate is provided on the inner wall of the groove. In a vertical field effect transistor in which the electrical conductivity state of the channel region is controlled by a gate electrode provided through an insulating film, the gate electrode is provided in an ohmic contact with a part of the channel region and in contact with the gate insulating film. 1. A vertical field effect transistor having a source electrode made of metal or silicide, the source electrode itself serving as a source region of the field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63153768A JPH023980A (en) | 1988-06-22 | 1988-06-22 | Perpendicular field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63153768A JPH023980A (en) | 1988-06-22 | 1988-06-22 | Perpendicular field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH023980A true JPH023980A (en) | 1990-01-09 |
Family
ID=15569711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63153768A Pending JPH023980A (en) | 1988-06-22 | 1988-06-22 | Perpendicular field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH023980A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0620588A2 (en) * | 1993-04-01 | 1994-10-19 | Philips Electronics Uk Limited | A method of manufacturing a recessed insulated gate field-effect semiconductor device |
US5508534A (en) * | 1994-02-24 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Trench gate type insulated gate bipolar transistor |
EP1120834A3 (en) * | 1994-02-21 | 2001-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
US6441434B1 (en) * | 2000-03-31 | 2002-08-27 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator body-source contact and method |
US6525381B1 (en) | 2000-03-31 | 2003-02-25 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator body-source contact using shallow-doped source, and method |
JP2012009522A (en) * | 2010-06-23 | 2012-01-12 | Mitsubishi Electric Corp | Semiconductor device for electric power |
US8393334B2 (en) | 2008-06-02 | 2013-03-12 | Philip Morris Usa Inc. | Smoking article with transparent section |
JP2014053633A (en) * | 2013-10-28 | 2014-03-20 | Rohm Co Ltd | Method for manufacturing trench type semiconductor element |
CN105470304A (en) * | 2014-09-26 | 2016-04-06 | 丰田合成株式会社 | Semiconductor device and method of manufacturing the same |
ITUB20154024A1 (en) * | 2015-09-30 | 2017-03-30 | St Microelectronics Srl | INTEGRATED ELECTRONIC DEVICE FOR VERTICAL CONDUCTION PROTECTED AGAINST LATCH-UP AND ITS MANUFACTURING PROCESS |
-
1988
- 1988-06-22 JP JP63153768A patent/JPH023980A/en active Pending
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0620588A3 (en) * | 1993-04-01 | 1996-08-14 | Philips Electronics Uk Ltd | A method of manufacturing a recessed insulated gate field-effect semiconductor device. |
EP0620588A2 (en) * | 1993-04-01 | 1994-10-19 | Philips Electronics Uk Limited | A method of manufacturing a recessed insulated gate field-effect semiconductor device |
EP1120834A3 (en) * | 1994-02-21 | 2001-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
US6323508B1 (en) | 1994-02-21 | 2001-11-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
US5508534A (en) * | 1994-02-24 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Trench gate type insulated gate bipolar transistor |
US6441434B1 (en) * | 2000-03-31 | 2002-08-27 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator body-source contact and method |
US6525381B1 (en) | 2000-03-31 | 2003-02-25 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator body-source contact using shallow-doped source, and method |
US6790750B1 (en) | 2000-03-31 | 2004-09-14 | Advanced Micro Devices, Inc. | Semiconductor-on-insulator body-source contact and method |
US8393334B2 (en) | 2008-06-02 | 2013-03-12 | Philip Morris Usa Inc. | Smoking article with transparent section |
JP2012009522A (en) * | 2010-06-23 | 2012-01-12 | Mitsubishi Electric Corp | Semiconductor device for electric power |
US8421145B2 (en) | 2010-06-23 | 2013-04-16 | Mitsubishi Electric Corporation | Power semiconductor device |
JP2014053633A (en) * | 2013-10-28 | 2014-03-20 | Rohm Co Ltd | Method for manufacturing trench type semiconductor element |
CN105470304A (en) * | 2014-09-26 | 2016-04-06 | 丰田合成株式会社 | Semiconductor device and method of manufacturing the same |
ITUB20154024A1 (en) * | 2015-09-30 | 2017-03-30 | St Microelectronics Srl | INTEGRATED ELECTRONIC DEVICE FOR VERTICAL CONDUCTION PROTECTED AGAINST LATCH-UP AND ITS MANUFACTURING PROCESS |
EP3151282A1 (en) * | 2015-09-30 | 2017-04-05 | STMicroelectronics S.r.l. | A vertical conduction integrated electronic device protected against the latch-up and relating manufacturing process |
US9711640B2 (en) | 2015-09-30 | 2017-07-18 | Stmicroelectronics S.R.L. | Vertical conduction integrated electronic device protected against the latch-up and relating manufacturing process |
US9882045B2 (en) | 2015-09-30 | 2018-01-30 | Stmicroelectronics S.R.L. | Vertical conduction integrated electronic device protected against the latch-up and relating manufacturing process |
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