JPH023980A - Perpendicular field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a vertical MOSFET freed of parasitic bipolar effect, by providing a source electrode of a metal or silicide in a part of a channel region such that it is in ohmic junction with the channel region and in contact with a gate insulating film. CONSTITUTION:Instead of a conventional source region, a source electrode 11 formed of a metal or silicide is provided in direct contact with a gate oxide film 9. The electrode 11 is ohmically joined with a channel region 3 and a channel 10 produced in the channel region 3 is formed by electrons emitted directly from the source electrode 11. According to such construction in which the source region is not provided by an N<+> diffused layer, no parasitic effect is caused by the source and channel regions 3 or by the drain region 2. Accordingly, the MOSFET is allowed to exhibit its maximum performance.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to vertical field effect transistors (MOSFETs).

(Prior Art) A conventionally known vertical MO8FET has a structure as shown in FIG. 8, for example. This has a structure called UMO3FET, and n
+ type or p+ type substrate 1, n″′ type drain region 2, p type channel region 3, and n+ type source region 4
, a gate electrode 5, an insulating film 6, a source electrode 7, a field SiO□ layer 8, and a gate SiO2 layer (gate oxide M) 9, and the gate electrode 5 is connected to the source region 4. It is provided along the inner wall of the U-groove that penetrates the three regions of the channel region 3 and the drain region 2, and is designed to control the generation of the channel 10 by the inversion layer generated in the channel region 3 along this.

In a MOSFET with this structure, current can be passed through the channel 10 from the source region 4 to the drain region 2 in the direction through these layers, that is, in the vertical direction in the figure, and this causes an increase in area due to microfabrication. This tJMO has the advantage of reducing the on-resistance of the device without
3FET is another vertical MO3FET, UMOSFET
It is said that the limit of miniaturization is higher than that of

In the above-mentioned 1MO8FET, if the conductivity type of the substrate 1 is made p+ type, it becomes a so-called IGBT (conductivity modulated MO3FE).
This is a type of MOSFET called T). This I
The GBT has a structure that is effective for lowering the on-resistance of a high-voltage device in which the specific resistance of the n-type drain region 2 needs to be increased, and various GBTs have been published in the past.

(Problem to be Solved by the Invention) However, the conventional vertical MO3FET as described above also has a woody drawback. This means that a parasitic npn transistor is formed by the source region 4, channel region 3, and drain region 2. When this parasitic npn type transistor operates, the MOSFET cannot perform its original operation, which causes device destruction.

The parasitic bipolar effect in the vertical MO8FET described above will be explained in detail using FIGS. 9 to 12.

Figure 9-1 is the same 1MO8FET shown in Figure 8.
The main parts of MO8FET are shown enlarged. In addition, No. 9-
In FIG. 1, parts corresponding to those in FIG. 1 are designated by the same reference numerals as in FIG. The 1MO8FET shown in FIG. 9-1 is a normal type 0MO3FET in which the n+ type substrate 1 is used as the drain electrode. , base resistance rB, and pn junction capacitance C4 between drain region 2 and channel region 3.
Contains. Also, this is a diode Di formed by the channel region 3 and the drain region 2 directly under the source electrode 7.
have. Therefore, the equivalent circuit of this UMOSFET is shown as shown in FIG. 9-2.

As is clear from FIG. 9-2, the base of the parasitic npn transistor Qp is connected to the source electrode 7 through the base resistor rn.
Since the transistor Qp is connected to
Controlled only by T's original channel. But the 10th
As shown in Figure 1, the spike voltage that occurs when switching an inductive load, or as shown in Figure 10-2, commutation noise that occurs during bridge drive of motor M, etc. parasitic npn type transistor Qp
It becomes a trigger to operate. In addition to flowing a displacement current into the base resistor 1''a through the ρn junction capacitance 1C, these voltages cause the breakdown voltage of the pn junction between the drain region 2 and the channel region 3 (BVcn of Qp −
(equal to ), it causes avalanche breakdown, which also causes a large current to flow through the base resistor ra, causing the parasitic npn transistor Qp to operate. - degree, when the parasitic npn transistor Qp operates, its safe operating area ASO is limited to the MOSFET due to the bipolar secondary breakdown limit, as shown in FIG.
Since it is much smaller than that of ET, when the energy is large, there is a risk that the device will be destroyed instantly.

Figure 12-1 shows a 1MO8F with a p+ type substrate 1'.
ET, or IGBT, which is free from the above-mentioned parasitic n
In addition to the pn-type transistor Qp, it includes a parasitic pnp-type transistor Qn formed by a substrate 1', a drain region 2, and a channel region 3.

As is clear from the equivalent circuit in Figure 12-2, this transistor Qn is thyristor-coupled (positive feedback coupling) with another transistor Qp, so when the transistor Qp operates due to the above-mentioned trigger, the parasitic thyristor This causes latch-up and makes it impossible to turn off.

(Objective of the Invention) In view of the above-mentioned problems in the conventional vertical MO3FET, an object of the present invention is to provide an improved vertical MO8FET that does not have parasitic bipolar effects and does not malfunction.

(Means for Solving the Problems) According to the present invention, the above objects are achieved by replacing the n-type semiconductor with metal or silicide for the source region, and the vertical field effect transistor according to the present invention has the following features: A gate electrode having a conductivity type drain region, a second conductivity type channel region, and a groove penetrating the channel region and reaching the drain region, and provided on an inner wall of the groove with a gate insulating film interposed therebetween. In a vertical field effect transistor in which the conduction state of the channel region is controlled by
A source electrode made of metal or silicide is provided in an ohmic contact with a part of the channel region and in contact with the gate insulating film, and the source electrode itself is used as a source region of a field effect transistor. It is a feature.

(Example) The present invention will be described in detail below with reference to the accompanying drawings.

1 and 2 show one embodiment of a vertical field effect transistor (MOSFET) according to the present invention. In addition, in FIGS. 1 and 2, the parts corresponding to FIG. They are indicated by the same reference numerals as those shown in FIG.

The vertical MO3FET according to the present invention differs from the conventional type in that, instead of the conventional source region 4, a source electrode 11 made of metal or silicide is in direct contact with the gate oxide M9. Source electrode 11
is in ohmic contact with the channel region 3, and the channel 10 generated in the channel region 3 is formed by electrons directly emitted from the source electrode 11.

For lateral MO8FETs, a Schottky source type device has already been proposed, but since the gate and source are insulated on a plane, an offset between the two is unavoidable. There is a problem that the on-state voltage and threshold voltage of the device become high.

On the other hand, in the vertical aMosFEr according to the present invention, since the Si oxide film formed on the inner wall surface of the vertical trench is used as an insulating film, it is possible to eliminate the offset, and moreover, it is possible to eliminate the offset from the source region to the drain region. As will become clear from the manufacturing process described below, the oxide film up to
A major advantage is that it is an extremely high-quality oxide film made by oxidizing the silicon substrate itself.

FIGS. 3-1 and 3-2 are energy band diagrams when the MOSFET is in the on state and when it is in the on state.

Gate electrode■. 3 is lower than the threshold voltage Vth, that is, when Vos<Vih, the MOSFET is in the on state. At this time, as shown in Figure 3-1,
Metal source M (source electrode 11) and channel region P (3
), a barrier of φBn exists between the channel region P
No electron injection takes place. Therefore, at this time, the channel region P remains non-conductive, and no current flows between the source electrode 11 and the drain region 2.

Gate voltage■. 3 is higher than the threshold voltage Vth, that is, V. When s>Vth, the MOSFET is in an on state. At this time, as shown in Figure 3-2,
The potential of the channel region P decreases, and the source electrode 1
Electrons are directly injected into the channel region P from the channel region P, thereby forming a channel 1.0 in the channel region P by an inversion layer. The channel 10 becomes a conductive path connecting the source electrode 11 and the drain region 2, and a current flows between the source electrode 11 and the drain region 2.

The substrate 1 is composed of a P+ type substrate, and the MOSFET is I
In the case of forming a GBT, holes are injected from the substrate 1 to the drain region 2, causing conductivity modulation, and the on-resistance further decreases. FIG. 4 shows the static characteristics of this MOSFET.

The MOSFET according to the present invention does not include a parasitic bipolar transistor because it does not use a source region formed by an N+ diffusion layer. Therefore, the equivalent circuit of the MOSFET according to the present invention is shown in FIG. 5-1 or 5-2, and becomes an ideal MOSFET or IGBT. Since the MOSFET according to the present invention does not include a parasitic bipolar transistor, the safe operating area ASO of the device becomes a wider area than MO3, as shown in FIG.

Since the IGBT does not include a parasitic bipolar transistor, the latch-up resistance is greatly improved, and in addition, holes can be sufficiently injected into the N-drain region 2, so the on-resistance is reduced. becomes significantly lower than the conventional one. In addition, in conventional IGBTs, hole injection is suppressed to avoid latch-up, and the hole concentration is controlled using a lifetime killer.
On-resistance was sacrificed.

Further, in the MOSFET according to the present invention, since source N+ diffusion is not required, productivity is improved and manufacturing costs are reduced.

Next, an example of the manufacturing procedure of the MOSFET according to the present invention as shown in FIG. 1 will be explained using FIGS. 7(a) to (j).

(a) As shown in the figure, first the n+ substrate or the p
A wafer is prepared on which an n- layer is epitaxially grown on a + substrate, and a SiO□ film is deposited on it by thermal oxidation to
Grow less than 0.0 mL, and then add a 5iyN4 film on top of it.
It is deposited by the V-D method to form a mask pattern for forming grooves. Note that the resistivity and thickness of the n-layer may be selected according to the required drain withstand voltage of the device, and when the required drain withstand voltage is approximately 100 V, the resistivity may be 10Ω1 and the thickness may be approximately 10 μm. .

Next, as shown in Figure (b), a substantially perpendicular groove is cut in the n-layer by a reactive ion etching technique. The depth of this layer may be approximately 2.5 μm. Lightly etch the groove and remove the damaged layer.

Next, as shown in Figure (C), the inner wall surface of the trench is dry oxidized to grow a gate oxide film (9).

The thickness of the gate oxide film may be about 1,000 or less. Note that the portion covered with Si3N4M is not oxidized.

Next, as shown in the figure (d), polycrystalline Si is
It is deposited by the D method and the grooves are filled with polycrystalline Si.

Next, as shown in the figure (e), the polycrystalline Si is etched back so that the polycrystalline Si remains only in the grooves.

Next, as shown in Figure U), only the polycrystalline Si is selectively oxidized using the 5tiN4 layer as a mask.

The thickness of this oxide layer may be about 5,000 or less.

Next, (g) as shown in the figure, 5i
The 5Na layer is removed, and then the 5
Etch fO2 to expose the n-layer Si surface.

Next, as shown in the figure (h), the Si surface of the n-layer is lightly etched to sufficiently expose the oxide film in the groove. Here, if an alkaline solution such as hydrazine is used as the etching solution, Si can be removed leaving only SiO2.

Next, (i) as shown in the figure, B+ for the n- layer.
A channel region (3) is formed by implanting (boron) ions and diffusing them. This channel area (3)
The thickness may be about 2 μm.

This step determines the threshold voltage Vth of the device, and the ion implantation and diffusion conditions are determined so that the surface impurity concentration becomes a desired value. Note that the diffusion depth may be determined to such an extent that the channel region 3 does not bunch through at the drain breakdown voltage.

Next, l) As shown in the figure, a part of the oxide film on the polycrystalline Si that is the gate electrode (5) is opened (indicated by reference numeral 12 in Figure 2), and then electrode metal is deposited. , a source electrode (11) and a gate wiring electrode (indicated by reference numeral 5' in FIG. 2) are formed. After this, the source electrode (11)
A heat treatment is performed to form an ohmic contact between the silicon layer and the Si forming the channel region (3).

Here, a silicide alloy layer or a p-type or n-type transition region is formed between the electrode metal and the channel region, and it is desirable that this transition region be as thin as possible. This is because when this transition region becomes thicker, the threshold voltage Vth changes significantly and also causes an offset voltage.

Therefore, the electrode metal is preferably a high melting point metal such as W, Ti, or Pt.

In the above manufacturing procedure example, the metal is left even after the heat treatment, but only the silicide layer remains, the metal is removed, and a new wiring electrode is taken out of only a part of the silicide layer using AI etc. The same effect can be obtained. In this case, the silicide layer functions as a source.

Depending on the metal, the difference in work function with Si may be too large and it may be difficult to form an ohmic contact directly with the channel region (3). Just set it up.

Also, the source electrode (11) near the gate which becomes the source region
For example, even if a barrier such as a Schottky junction exists, there is no problem because the barrier can be easily removed by the surface potential modulation effect of the gate voltage.

(Effects of the Invention) As described above, in the MOSFET according to the present invention, since the source region is provided by the source electrode itself made of metal or silicide, the performance of the MOSFET is maximized without causing parasitic bipolar effects. Moreover, since the manufacturing process is simple, manufacturing costs can be reduced.

Furthermore, if the gate oxide film is formed by oxidizing a part of the Si substrate itself, a high quality gate oxide film can be obtained, and MO
The performance of SFET will improve.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram showing one embodiment of a MOSFET according to the present invention, FIG. 2 is a plan view thereof, and FIGS. 3-1 and 3-
Figure 2 is an energy band diagram, and Figure 4 is an MO according to the present invention.
Graphs showing static characteristics of SFET, Figures 5-1 and 5-
2 is an equivalent circuit diagram of the MOSFET according to the present invention, FIG. 6 is a graph showing the safe operating area of the MOSFET according to the present invention, and FIGS. 7(a) to (j) are equivalent circuit diagrams of the MOSFET according to the present invention.
FIG. 8 is a structural diagram showing a conventionally known 1MO3FET, FIG. 9-1 is a structural diagram showing a parasitic device of the 1MO3FET shown in FIG. 8, and FIG. 9- Figure 2 is its equivalent circuit diagram, Figures 10-1 and 10-2 are block diagrams showing usage examples of UMO3FET, Figure 11 is a graph showing the safe operating area of the device, and Figure 12-1 is a graph showing the safe operating area of the device. A structural diagram showing a parasitic device of the UMO8 IGBT, and FIG. 12-2 is an equivalent circuit diagram thereof. 1... Substrate 2... Drain region 3... Channel region 4... Source region 5... Gate electrode 6... Insulating film 7... Source electrode 8... Field SiO□ layer 9 ...Gate 5iQ2 layer (gate oxide film) 10...
Channel 11... Source electrode patent applicant Nissan Motor Co., Ltd.

Claims (1)

[Claims] 1. It has a drain region of a first conductivity type, a channel region of a second conductivity type, and a groove that penetrates the channel region and reaches the drain region, and a gate is provided on the inner wall of the groove. In a vertical field effect transistor in which the electrical conductivity state of the channel region is controlled by a gate electrode provided through an insulating film, the gate electrode is provided in an ohmic contact with a part of the channel region and in contact with the gate insulating film. 1. A vertical field effect transistor having a source electrode made of metal or silicide, the source electrode itself serving as a source region of the field effect transistor.