JP4746169B2 - Power semiconductor device and driving method thereof - Google Patents

Power semiconductor device and driving method thereof Download PDF

Info

Publication number
JP4746169B2
JP4746169B2 JP2000130648A JP2000130648A JP4746169B2 JP 4746169 B2 JP4746169 B2 JP 4746169B2 JP 2000130648 A JP2000130648 A JP 2000130648A JP 2000130648 A JP2000130648 A JP 2000130648A JP 4746169 B2 JP4746169 B2 JP 4746169B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
layer
type
semiconductor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000130648A
Other languages
Japanese (ja)
Other versions
JP2001313393A (en
Inventor
渉 齋藤
一郎 大村
常雄 小倉
弘通 大橋
健一 都鹿野
芳彦 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000130648A priority Critical patent/JP4746169B2/en
Publication of JP2001313393A publication Critical patent/JP2001313393A/en
Application granted granted Critical
Publication of JP4746169B2 publication Critical patent/JP4746169B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、大電力の制御に用いられる電力用半導体装置及びその素子の駆動方式に関し、特にパワーＭＯＳＦＥＴ及びその駆動方式に関する。
【０００２】
【従来の技術】
最近、電力制御用の電力用半導体装置としてユニポーラ動作のパワーＭＯＳＦＥＴが広く用いられているが、ＭＯＳＦＥＴは、高速動作が期待できるが、バイポーラ動作のＩＧＢＴに比べて耐圧が高くなるにしたがって、オン状態でので電圧降下が高くなり、通電損失が大きくなる問題がある。この問題を解決するＭＯＳＦＥＴの一例として、例えば特開平９−１９１１０９号公報に開示されたものが知られている。
【０００３】
図１０は、この種のＭＯＳＦＥＴの構成を模式的に示す断面図である。
【０００４】
このＭＯＳＦＥＴは、ｎ−型ドリフト層１１１の一方の表面にｎ＋型ドレイン層１１２が形成され、このｎ＋型ドレイン層１１２上にはドレイン電極１１３が形成されている。またそのｎ−型ドリフト層１１１の他方の表面には複数のｐ型ベース層１１４が選択的に形成され、この各ｐ型ベース層１１４表面にはｎ＋型ソース層１１５が選択的に形成されている。また前記ｐ型ベース層１１４及び前記ｎ＋型ソース層１１５から前記ｎ−型ドリフト層１１１を介して他方の前記ｐ型ベース層１１４及び前記ｎ＋型ソース層１１５に至る領域上には、ゲート絶縁膜１１６を介してゲート電極１１７が形成されている。またこのゲート電極１１７を挟むように、一方の前記ｐ型ベース層１１４及びｎ＋型ソース層１１５上と、他方の前記ｐ型ベース層１１４及びｎ＋型ソース層１１５上には、各々ソース電極１１８が形成されている。そして、前記ｐ型ベース層１１４と前記ドレイン電極１１２との間の前記ｎ−型ドリフト層１１１中には、３層のｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃが、互いに間隔をおいて選択的に埋込み形成されている。またこのｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃは、いずれも電気的に浮遊状態にされている。
【０００５】
【発明が解決しようとする課題】
このようなＭＯＳＦＥＴでは、オフ状態の際には、ｎ−型ドリフト層１１１内の電界を、ｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃにより分割されたｎ−型ドリフト層１１１の分割数に応じて分割することができる。例えば、ｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃが３層の場合には、ｎ−型ドリフト層１１１の電界は４分割され、耐圧６００Ｖの素子と仮定すると、ｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃ間に必要な耐圧は１５０Ｖとなる。このように耐圧が低くなったことにより、ｎ−型ドリフト層１１１の不純物濃度は、ｐ＋型埋込み層１１９ａ，１１９ｂ，１１９ｃがない場合に比べて４倍にでき、ｎ−型ドリフト層１１１中の電気抵抗を低減することが可能となり、そのため素子のオン抵抗を１／４程度まで低減させることが可能となる。
【０００６】
しかし、このような構造のＭＯＳＦＥＴでは、オフ状態においてｐ＋型埋込み層が一旦空乏化すると、ターンオン時にｐ＋型埋込み層の空乏化が解消されるまで正常なオン状態にならなず、ターンオン時間が約１００μｓ以上と時間が長い。
【０００７】
また、ターンオン直後、ｐ＋型埋込み層から周辺に空乏層が延び、実効的にキャリアが伝導する面積が減るため、素子自体は高抵抗となってスイッチング損失が大きくなる。
【０００８】
本発明は、このような課題に鑑みなされたもので、ターンオン時間を短縮し高速動作が可能で、スイッチング損失の少ない大電力用半導体素子及びその素子の駆動方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
上記目的を解決するために、請求項１に対応する発明の電力用半導体装置は、第１導電型の第１の半導体層と、前記第１の半導体層に一方の表面に電気的に接続された第１の主電極と、前記第１の半導体層の他方の表面に選択的に形成された第２導電型の第２の半導体層と、前記第２の半導体層の表面に選択的に形成された第１導電型の第３の半導体層と、前記第２の半導体層と前記第３の半導体層とに電気的に接続された第２の主電極と、前記第１の半導体層と前記第２の半導体層と前記第３の半導体層の表面上に絶縁膜を介して形成された第１の制御電極と、前記第１の半導体層中であって、前記第２の半導体層と前記第１の主電極との間に選択的に埋込まれた少なくとも１つ以上の電位の浮いた第２導電型埋込み層と、前記第１の半導体層の他方の表面に選択的に形成された第２導電型の第５の半導体層と、前記第５の半導体層に電気的に接続された第２の制御電極と、前記第１の半導体層の一方の表面と前記第１の主電極との間に、前記第１の半導体層よりも高不純物濃度をもつ第１導電型の高濃度半導体層が形成され、前記第５の半導体層は、前記高濃度半導体層に選択的に形成され、且つ前記第１の主電極側の一端が前記高濃度半導体層と同一平面をなし、他端が前記高濃度半導体層を貫通して前記第１の半導体層中に達する形状に形成されてなることを特徴としている。
【００１０】
また、請求項２に対応する発明の電力用半導体装置は、前記第１の主電極と前記第２の制御電極とが電気的に共通接続されてなることを特徴としている。
【００１１】
さらにまた、請求項３に対応する発明の電力用半導体装置は、前記第１の主電極と前記第２の制御電極とが電気的に独立に形成されてなることを特徴としている。
【００１２】
さらにまた、請求項４に対応する発明の電力用半導体装置は、前記第５の半導体層は、前記第１の半導体層の一方の表面、または前記第１の主電極側の前記高濃度半導体層表面において、前記第５の半導体層の表面積とこの層に隣接する前記１の半導体層部分部、または隣接する前記高濃度半導体層部分の表面積とが同一面積であることを特徴としている。
【００１３】
さらにまた、請求項５に対応する発明の電力用半導体装置は、前記第５の半導体層は、前記第１の半導体層の一方の表面、または前記第１の主電極側の前記高濃度半導体層表面において、前記第５の半導体層の表面積がこの層に隣接する前記１の半導体層部分部、または隣接する前記高濃度半導体層部分の表面積より広面積であることを特徴としている。
【００１４】
さらにまた、請求項６に対応する発明の電力用半導体装置は、第1導電型の第1の半導体層と、前記第１の半導体層の一方の表面に電気的に接続された第１の主電極と、前記第1の半導体層の他方の表面に選択的に形成された第２導電型の第２の半導体層と、前記第２の半導体表面に選択的に形成された第1導電型の第3の半導体層と、前記第２の半導体層と前記第３の半導体層の表面に電気的に接続された第２の主電極と、前記第１の半導体層と前記第2の半導体層と前記３の半導体層上に絶縁膜を介して形成された第1の制御電極と、前記第1の半導体層の他方の表面に前記第2の半導体層と離間して選択的に形成された第２導電型の第６の半導体層と、前記第６の半導体層の表面に選択的に形成された第1導電型の第７の半導体層と、前記第６の半導体層と前記第７の半導体層とに電気的に接続された電位の浮遊したフローティング電極と、前記第1の半導体層と前記第６の半導体層と前記第７の半導体層上に絶縁膜を介して形成された第２の制御電極と、前記第1の半導体層中に選択的に埋込み形成された少なくとも１つ以上の電位の浮いた第2導電型埋め込層とを有することを特徴としている。
【００１５】
さらにまた、請求項７に体操する発明の電力用半導体装置は、前記第１の半導体層の素子形成領域の周辺部における不純物濃度が、素子形成領域の不純物濃度より低濃度に形成れていることを特徴としている。
【００１６】
さらにまた、請求項８に対応する発明の電力用半導体装置は、前記第５の半導体層は、前記第１の半導体層の一方の表面、または前記第１の主電極側の前記高濃度半導体層表面において、前記第５の半導体層の表面積がこの層に隣接する前記１の半導体層部分部、または隣接する前記高濃度半導体層部分の表面積より広面積であることを特徴としている。
【００１７】
さらにまた、請求項９に対応する発明の電力用半導体装置は、第1導電型の第1の半導体層と、前記第１の半導体層の一方の表面に電気的に接続された第１の主電極と、前記第1の半導体層の他方の表面に選択的に形成された第２導電型の第２の半導体層と、前記第２の半導体表面に選択的に形成された第1導電型の第3の半導体層と、前記第２の半導体層と前記第３の半導体層の表面に電気的に接続された第２の主電極と、前記第１の半導体層と前記第2の半導体層と前記３の半導体層上に絶縁膜を介して形成された第1の制御電極と、前記第1の半導体層の他方の表面に前記第2の半導体層と離間して選択的に形成された第2導電型の第６の半導体層と、前記第６の半導体層の表面に選択的に形成された第1導電型の第７の半導体層と、前記第６の半導体層と前記第７の半導体層とに電気的に接続された電位の浮遊したフローティング電極と、前記第1の半導体層と前記第６の半導体層と前記第７の半導体層上に絶縁膜を介して形成された第2の制御電極と、前記第1の半導体層中に選択的に埋込み形成された少なくとも１つ以上の電位の浮いた第2導電型埋め込層とを有することを特徴としている。
【００１８】
さらにまた、請求項１０に対応する発明の電力用半導体装置は、第1導電型の第1の半導体層と、前記第１の半導体層の一方の表面に電気的に接続された第１の主電極と、前記第1の半導体層の他方の表面に選択的に形成された第2導電型の第2の半導体層と、前記第２の半導体層の表面に選択的に形成された第1導電型の第3の半導体層と、前記第２の半導体層と前記第３の半導体層とに電気的に接続された第2の主電極と、前記第１の半導体層と前記第２の半導体層と前記第３の半導体層の表面上に絶縁膜を介して形成された制御電極と、前記第1の半導体層中であって、前記第２の半導体層と前記第１の主電極との間に選択的に埋込まれた少なくとも１つ以上の電位の浮いた第２導電型埋め込層と、前記第２導電型埋込み層より低不純物濃度に形成され、且つ前記第２の半導体層と前記第２導電型埋込み層とを接続する接続層とを有することを特徴としている。
【００１９】
さらにまた、請求項１１に対応する発明の電力用半導体装置は、前記第１の半導体層の素子形成領域の周辺部における不純物濃度が、素子形成領域の不純物濃度より低濃度に形成れていることを特徴としている。
【００２０】
さらにまた、請求項１２に対応する発明の駆動方式は、電力用半導体半導体装置を駆動する駆動方法であって、前記第２の制御電極に流す電流を、ターンオン時のみ定常時より大きくすることを特徴としている。
【００２１】
【発明の実施の形態】
以下、本発明の実施の形態について図面を参照しながら説明する。なお、以下の実施形態では第1導電型をｎ型、第2導電型をｐ型としている。また、図面中の同一部分には同一番号を付している。
【００２２】
（第１の実施形態）
図1は本発明の第1の実施の形態に係わるパワーＭＯＳＦＥＴの構成を模式的に示す断面図である。
【００２３】
このＭＯＳＦＥＴは、第１の半導体層としてのｎ−型ドリフト層１の一方の表面に高濃度半導体層、例えばｎ＋型ドレイン層２が形成され、このｎ＋型ドレイン層２上には、第１の主電極としてのドレイン電極３が形成されている。このｎ−型ドリフト層１は、一例として、約１×１０15ｃｍ-3の不純物濃度で、約６０μｍの厚さに形成され、ｎ＋型ドレイン層２は、一例として、約６×１０18ｃｍ-3の不純物濃度で、約１８０μｍの厚さに形成されている。なお、前記ｎ＋型ドレイン層２は、必要に応じて形成すれば良い。
【００２４】
また前記ｎ−型ドリフト層１の他方の表面には、第２の半導体層としての複数の第１のｐ型ベース層４が、互いに間隔をおいて選択的に、且つストライプ形状に拡散形成され、この各第１のｐ型ベース層４表面には、第３の半導体層としてのｎ＋型ソース層５が、各々選択的に、且つストライプ形状に拡散形成されている。この第１のｐ型ベース層４は、一例として、約３×１０17ｃｍ-3の不純物濃度で、約２．０μｍの深さに形成され、また前記ｎ＋型ソース層５は、一例として、約1×１０20cm-3の不純物濃度で、約０．２μｍの深さに形成されている。
【００２５】
また前記第１のｐ型ベース層４及び前記ｎ＋型ソース層５から前記ｎ−型ドリフト層１を介して他方の前記第１のｐ型ベース層４及び前記ｎ＋型ソース層５に至る領域上には、膜厚約０．１μｍのゲート絶縁膜、例えばＳｉ酸化膜６を介して第１の制御電極としての第１のゲート電極７がストライプ形状に形成されている。この第１のゲート電極７を挟むように、一方の前記第１のｐ型ベース層４及びｎ＋型ソース層５上と、他方の前記第１のｐ型ベース層４及びｎ＋型ソース層５上には、第２の主電極としてのソース電極８がストライプ形状に形成されている。そして、前記ドレイン電極３と前記ｐ型ベース層４との間の前記ｎ−型ドリフト層１中には、ストライプ形状をもつ例えば３層のｐ＋型埋込み層９ａ，９ｂ，９ｃが、選択的に埋込み形成されている。このｐ＋型埋込み層９ａ，９ｂ，９ｃは、例えば、横方向に長軸をもつ楕円形状に形成され、一例として、約1×１０18ｃｍ-3のピーク濃度で、約３．０μｍの長軸、約２．５μｍの短軸を持つ楕円形に形成され、縦方向の間隔を１５．５μｍ、横方向の間隔を約６．０μｍに形成されている。
【００２６】
またこのｐ＋型埋込み層９ａ，９ｂ，９ｃは、いずれも電気的に浮遊状態にされている。
【００２７】
そして、この実施形態に係わるＭＯＳＦＥＴでは、さらに、前記第１のｐ型ベース層周辺部の前記ｎ−型ドリフト層１表面には、ストライプ形状をもつ第６の半導体層として第２のｐ＋型ベース層１０（ｐ＋型キャリア注入層）が形成され、このｐ＋型キャリア注入層１０上には、第２の制御電極、例えば第２のゲート電極１１が形成されている。このｐ＋型キャリア注入層１０は、一例として、深さが約２．０μｍ、不純物濃度のピーク値が３×１０19ｃｍ-3に形成されている。
【００２８】
上記第１の実施形態のＭＯＳＦＥＴでは、第１のｐ型ベース層４周辺部のｎ−型ドリフト層１中にｐ＋型キャリア注入層１０を形成し、このｐ＋型キャリア注入層１０上に第２のゲート電極１１を設けて制御電圧を印加できるようにしている。このため、ターンオン時に、この第２のゲート電極１１に正バイアス電圧を加えることにより、ｐ＋型キャリア注入層１０とｎ−型ドリフト層１が形成するダイオードがオンとなり、ｐ＋型キャリア注入層１０からホールがｎ−型ドリフト層１中に注入される。このホール注入により、ｐ＋型埋込み層９ａ，９ｂ，９ｃの空乏化が速やかに解消され、直ちにＭＯＳＦＥＴはオン状態となる。そのためターンオン時間は約５０ｎｓと短く、高速動作が可能となり、しかもスイッチング損失は極めて小さい。
【００２９】
（第2の実施形態）
次に、本発明の第２の実施の形態に係わるパワーＭＯＳＦＥＴについて説明する。
【００３０】
図２は、このパワーＭＯＳＦＥＴの構成を模式的に示す断面図であり、図１と同一部分には同一番号を付してその詳しい説明は省略し、ここでは異なる部分についてのみ説明する。
【００３１】
この実施形態では、ドレイン電極側のｎ−型ドリフト層表面にｐ＋型キャリア注入層を設け、ドレイン電極側よりホールの注入をおこなうようにしたものである。すなわち、このＭＯＳＦＥＴは、ｎ−型ドリフト層１の一方の表面にｎ＋型ドレイン層２が形成され、このｎ＋型ドレイン層２上には、ドレイン電極３が形成され、また前記ｎ−型ドリフト層１の他方の表面には、複数のｐ型ベース層４が選択的に形成され、この各ｐ型ベース層４表面には、ｎ＋型ソース層５が選択的に形成されている。
【００３２】
また前記ｐ型ベース層４及び前記ｎ＋型ソース層５から前記ｎ−型ドリフト層１を介して他方の前記ｐ型ベース層４及び前記ｎ＋型ソース層５に至る領域上には、ゲート絶縁膜６を介してゲート電極７が形成され、このゲート電極７を挟むように、一方の前記ｐ型ベース層４及びｎ＋型ソース層５上と他方の前記ｐ型ベース層４及びｎ＋型ソース層５上とには、ソース電極８が形成されている。
【００３３】
また前記ドレイン電極３と前記ｐ型ベース層４との間の前記ｎ−型ドリフト層１中には、３層のｐ＋型埋込み層９ａ，９ｂ，９ｃが、選択的に埋込み形成され、且ついずれも電気的に浮遊状態にされている。
【００３４】
そして、この実施形態に係わるＭＯＳＦＥＴでは、さらに、第５の半導体層としてのストライプ状のｐ＋型キャリア注入層２０が、前記ｎ＋型ドレイン層２中に選択的に形成されている。このｐ＋型キャリア注入層２０は、最下層のｐ＋型埋込み層９ｃとドレイン電極３との間に設けられ、且つこのｐ＋型キャリア注入層２０は、一端が前記ドレイン電極３に接続され、他端がｎ＋型ドレイン層２を貫通して前記ｎ−型ドリフト層１中に達するように形成されている。
【００３５】
このｐ＋型キャリア注入層２０は、一例として、前記ｎ−型ドリフト層１中に約５．０μｍくいこむように約１８５μｍの深さで、約1×１０19ｃｍ-3の不純物濃度に形成されている。また、このｐ＋型キャリア注入層２０と隣接するｎ＋型ドレイン層２部分とは、いずれも約３．０μｍの幅で、表面積が同一に形成されている。
【００３６】
上記第２の実施形態のＭＯＳＦＥＴでは、ドレイン電流が流れることにより、前記ｎ−型ドリフト層１と前記ｐ＋型キャリア注入層２０とで形成するｐｎ接合に電圧が加わり前記ｐ＋型キャリア注入層２０から前記ｎ−型ドリフト層１にホールが注入される。このホール注入により、ｐ＋型埋込み層９ａ，９ｂ，９ｃの空乏化が速やかに解消され、直ちにＭＯＳＦＥＴはオン状態となる。しかも前記ｐ＋型キャリア注入層２０をｐ＋型埋込み層の直下で、且つ近接させて配置しているため、ターンオン時間が約７０ｎｓと短く、高速動作が可能となり、しかもスイッチング損失は極めて小さい。また、前記ｐ＋型キャリア注入層２０を第１のｐ型ベース層の下方に形成されるので、第１の実施形態のＭＯＳＦＥＴに比べて、装置を小型化できる。
【００３７】
（第3の実施形態）
次に、本発明の第３の実施の形態に係わるパワーＭＯＳＦＥＴについて説明する。
【００３８】
図３は、このパワーＭＯＳＦＥＴの構成を模式的に示す断面図であり、図２と同一部分には同一番号を付してその詳しい説明は省略し、ここでは異なる部分についてのみ説明する。
【００３９】
すなわち、このパワーＭＯＳＦＥＴは、本発明の第２の実施形態の変形構成であり、図3に示すように、第５の半導体層としてのストライプ状のｐ＋型キャリア注入層３０は、最下層のｐ＋型埋込み層９ｃとドレイン電極３との間に位置する前記ｎ＋型ドレイン層２部分に選択的に、且つ前記ｎ＋型ドレイン層２と同じ層厚に設けられ、一端が前記ドレイン電極側のｎ＋型ドレイン層２表面と同一平面をなし、且つ他端が前記ｎ−型ドリフト層１に接触するように形成された構成となっている。しかもこのｐ＋型キャリア注入層３０及びこれに隣接するｎ＋型ドレイン層２部分は、一例として、それぞれ幅約５．０μｍ及び幅約１．０μｍに形成され、前記ｎ＋型ドレイン層２表面におけるｐ＋型キャリア注入層３０の表面積が隣接するｎ＋型ドレイン層２部分より広面積に形成されている。
【００４０】
上記第3の実施形態のＭＯＳＦＥＴでは、ｐ＋型キャリア注入層３０の表面積が広く形成されており、そのためｐ＋型キャリア注入層３０と前記ｎ−型ドリフト層１とで形成するｐｎ接合に印加される電圧が大きくなり、ｐ＋型キャリア注入層３０から前記ｎ−型ドリフト層１へのホール注入が促進され、上記第２の実施形態と同様に、高速動作が可能となり、またスイッチング損失も小さい。
【００４１】
（第4の実施形態）
次に、本発明の第４の実施の形態に係わるパワーＭＯＳＦＥＴについて説明する。
【００４２】
図４はこのパワーＭＯＳＦＥＴの構成を模式的に示す断面図である。
【００４３】
このＭＯＳＦＥＴは、第１の半導体層としてのｎ−型ドリフト層１の一方の表面に高濃度半導体層、例えばｎ＋型ドレイン層２が形成され、このｎ＋型ドレイン層２上には、第１の主電極としてのドレイン電極３が形成されている。
【００４４】
また前記ｎ−型ドリフト層１の他方の表面には、第２の半導体層としての第１のｐ型ベース層４が選択的に形成され、この第１のｐ型ベース層４表面には、第３の半導体層としてのｎ＋型ソース層５が選択的に形成されている。
【００４５】
また前記ｎ−型ドリフト層１、前記第１のｐ型ベース層４及び前記ｎ＋型ソース層５上には、ゲート絶縁膜、例えばＳｉ酸化膜６を介して第１の制御電極としての第１のゲート電極７が形成され、この第１のゲート電極７の外側で、前記第１のｐ型ベース層４及びｎ＋型ソース層５に第２の主電極としてのソース電極８が形成されている。
【００４６】
さらに前記ｎ−型ドリフト層１の他方の表面には、前記第６の半導体層としての第２のｐ型ベース層４４が、前記第１のｐ型ベース層４と離間して選択的に拡散形成され、この第２のｐ型ベース層４４表面には、第７の半導体層としての第２のｎ＋型ソース層４５が選択的に形成されている。
【００４７】
また前記ｎ−型ドリフト層１、前記第２のｐ型ベース層４４及び前記第２のｎ＋型ソース層４５上には、ゲート絶縁膜、例えばＳｉ酸化膜４６を介して第２の制御電極としての第２のゲート電極４７が形成され、この第２ゲートｄ電極４７は、ここでは、前記第１のゲート電極７と電気的に接続されている。またこの第２のゲート電極４７の内側、即ち前記第１のゲート電極７側で、前記第２のｐ型ベース層４４及び第２のｎ＋型ソース層４５上に電位の浮遊したフローティング電極としてのソース電極４８が形成されている。
【００４８】
そして、また前記ドレイン電極３と前記ｐ型ベース層４、４４との間の前記ｎ−型ドリフト層１中には、例えば３層のｐ＋型埋込み層９ａ，９ｂ，９ｃが、選択的に埋込み形成されている。またこのｐ＋型埋込み層９ａ，９ｂ，９ｃは、いずれも電気的に浮遊状態にされている。
【００４９】
上記第４の実施形態のＭＯＳＦＥＴでは、フローティング電極は、第２のゲート電極に閾値電圧以上の電圧が印加されると、第２のゲート電極下にチャンネルができ、第２のｎ＋型ソース層４５から前記ｎ−型ドリフト層１中に電子が注入される。このため、フローティング電極の電位が上昇し、フローティング電極に接続された前記第２のｐ型ベース層４４と前記ｎ−型ドリフト層１とにより形成されるｐｎ接合に正バイアス電圧が加わり、前記第２のｐ型ベース層４４から前記ｎ−型ドリフト層１にホールが注入される。その結果、ｐ＋型埋込み層９ａ，９ｂ，９ｃの空乏化が速やかに解消され、直ちにＭＯＳＦＥＴがオン状態となる。そのため高速動作が可能となり、しかもスイッチング損失も小さくなる。
【００５０】
また第１及び第２のｐ型ベース層４及び４４、第１及び第２のソース層５及び４５、ゲート絶縁膜６，４６、第１及び第２のゲート電極７及び４７、並びにソース電極７及びフローティング電極４７は、それぞれ同一工程で形成できるため、ＭＯＳＦＥＴの製造が容易である。
【００５１】
（第5の実施形態）
次に、本発明の第５の実施の形態に係わるパワーＭＯＳＦＥＴについて説明する。
【００５２】
図５は、このパワーＭＯＳＦＥＴの構成を模式的に示す断面図であり、図１と同一部分には同一番号を付してその詳しい説明は省略し、ここでは異なる部分についてのみ説明する。
【００５３】
すなわち、このパワーＭＯＳＦＥＴは、本発明に係わる第１の実施形態の変形構成であり、図５に示すように、ｐ型ベース層４と最上層の前記ｐ＋型埋め込み層９ａ間、この最上層のｐ＋型埋め込み層９ａと中間層の前記ｐ＋型埋め込み層９ｂ間、この中間層のｐ＋型埋め込み層９ｂと最下層の前記ｐ＋型埋め込み層９ｃ間をｐ−型の接続層５０ａ、５０ｂ、５０ｃによって順次接続した構成となっている。このｐ−型の接続層５０ａ、５０ｂ、５０ｃは、いずれも、一例として、約１×１０15ｃｍ-3の不純物濃度で、約２．０μｍの幅に形成されている。またｎ−型ドリフト層１の不純物濃度は約２×１０15ｃｍ-3 である。
【００５４】
この第５の実施形態のＭＯＳＦＥＴでは、前記ｐ−型の接続層５０ａ、５０ｂ、５０ｃは、高電圧が印加されると完全に空乏化し、前記ｎ−型ドリフト層１内の電界は、ｐ＋型埋め込み層９ａ、９ｂ、９ｃが接続されていない場合と同様に各ｐ＋型埋め込み層毎に分割されるので、第１の実施形態と同様な耐圧が保持される。それに加え、ターンオン時には前記ｐ−型の接続層５０ａ、５０ｂ、５０ｃを通じて直接ｐ＋型埋め込み層９ａ，９ｂ，９ｃにソース電極よりキャリアが効率よく、しかも即座に供給されて各ｐ＋型埋め込み層は充電される。その結果、上記各実施形態のＭＯＳＦＥＴに比べて、ｐ＋型埋め込み層９ａ、９ｂ、９ｃの空乏化の解消が速く、ＭＯＦＥＴのオン状態も早く、そのためターンオン時間は約４００ｎｓと極めて短く、より高速動作が可能となる。
【００５５】
（第６の実施形態）
次に、本発明の第５の実施の形態に係わるパワーＭＯＳＦＥＴの製造方法について説明する。
【００５６】
図６は、このＭＯＳＦＥＴの製造工程を示す模式的な工程図である。
【００５７】
まず、図６（ａ）に示すように、ドレイン層としてのｎ＋型基板２上に第１の半導体層としてのｎ−型ドリフト層１をエピタキシャル成長させる。
【００５８】
続いて図６（ｂ）に示すように、前記ｎ−型ドリフト層１上にマスクを介してｐ型不純物としてのボロン並びにｎ型不純物としてのリンを順次イオン注入する。
【００５９】
イオン注入後、図６（ｃ）に示すように、イオン注入されたｎ−型ドリフト層１上に最終的にｐ−型接続層となるｐ−型層５０をエピタキシャル成長させる。このエピタキシャル成長工程において、ボロン及びリンが再拡散され最下層のｐ＋型埋め込み層９ｃが形成されると同時に、このｐ＋型埋め込み層９ｃ、９ｃ間に所定濃度のｎ−型ドリフト層１部分が形成される。
【００６０】
次に図６（ｄ）に示すように、このｐ＋型埋め込み層９ｃ、９ｃ間上に位置するｐ−型層５０部分の表面にリンをイオン注入する。
【００６１】
イオン注入後、図６（ｅ）に示すように、イオン注入されたｐ−型層５０上に、更にｐ−型層５０をエピタキシャル成長させる。このエピタキシャル成長工程において、リンが再拡散されて最初のｐ−型層５０が分断され、最下層のｐ＋型埋め込み層９ｃ上に延在するｐ−型接続層５０ｃが形成される。
【００６２】
続いて図６（ｆ）に示すように、ｐ＋型埋め込み層９ｃ及びｎ−型ドリフト層１部分に対応する前記ｐ−型層５０部分表面に、それぞれマスクを介してボロン並びにリンを順次イオン注入する。
【００６３】
イオン注入後、図６（ｇ）に示すように、イオン注入されたｐ−型層５０上に、更にｐ−型層５０をエピタキシャル成長させる。このエピタキシャル成長工程において、ボロン及びリンが再拡散され、ｐ−型接続層５０ｃ上に中間層のｐ＋型埋め込み層９ｂが形成されると同時に、このｐ＋型埋め込み層９ｂ、９ｂ間に所定濃度のｎ−型ドリフト層１部分が形成され、また最下層のｐ＋型埋め込み層９ｃと中間層のｐ＋型埋め込み層９ｂとの間に両層を接続するｐ−型接続層５０ｃが形成される。
【００６４】
以下同様に、図６（ｄ）乃至図６（ｇ）工程を繰り返すことにより、図６（ｈ）に示すような、ｐ−型接続層５０ｂ上に最上層のｐ＋型埋め込み層９ａが形成され、このｐ＋型埋め込み層９ａ、９ａ間に所定濃度のｎ−型ドリフト層１部分が形成され、また最上層のｐ＋型埋め込み層９ａ及びｎ−型ドリフト層１部分上にエピタキシャル成長されたｐ−型層５０を有する構造が形成される。
【００６５】
次に図６（ｉ）に示すように、このｐ＋型埋め込み層９ａ、９ａ間上に位置するｐ−型層５０部分の表面にリンをイオン注入する。
【００６６】
次に、図６（ｊ）に示すように、このｐ−型の接続層５０ａとｎ−型ドリフト層１との表面上に、さらにｎ−型ドリフト層１をエピタキシャル成長させる。このｎ−型ドリフト層１のエピタキシャル成長工程において、リンが再拡散され、ｐ＋型埋め込み層９ａ、９ｂ、９ｃがｐ−型の接続層５０ａ、５０ｂにより接続され、且つ最上層のｐ＋型埋め込み層９ａ上にｐ−型の接続層５０ａが縦方向に延在し、縦方向にｎ−型ドリフト層１が伸びる構造が形成される。
【００６７】
その後、図５に示すように、このｎ−型ドリフト層１表面に選択的に、ｐ型ベース層４を拡散形成し、続いてこのｐ型ベース層４表面に、ｎ＋型ソース層５を選択的に形成する。
【００６８】
最後に、ゲート絶縁膜６を形成した後、ゲート電極７、ソース電極８、ドレイン電極２をそれぞれ形成することにより、ＭＯＳＦＥＴが完成される。
【００６９】
（第７の実施形態）
次に本発明の第7の実施形態に係わるパワーＭＯＳＦＥＴについて説明する。
【００７０】
図7はこのパワ−ＭＯＳＦＥＴの構成を模式的に示す断面図であり、図1と同一部分には同一番号を付してその詳しい説明は省略し、ここでは異なる部分についてのみ説明する。
【００７１】
すなわち、このＭＯＳＦＥＴは、各実施形態の変形構成であり、素子終端部での耐圧劣化の阻止を図るものであって、具体的には図7に示すように、素子形成領域周辺部のドリフト層１’は、素子形成領域部分のｎ型ドリフト層１より低不純物濃度を有するｎ−型に形成された構成となっている。この実施形態のＭＯＳＦＥＴでは、耐圧６００Ｖと仮定して、素子形成領域部分のｎ型ドリフト層１は、一例として１×１０15ｃｍ-3の不純物濃度に形成し、且つ素子形成領域周辺部のドリフト層１’は、一例として、ｐ＋型埋め込み層を有しない構造のＭＯＳＦＥＴにおけるドリフト層の不純物濃度と同様の２×１０14ｃｍ-3の不純物濃度に形成している。
【００７２】
従って、上記第７の実施形態のＭＯＳＦＥＴでは、素子形成領域周辺部のドリフト層が低不純物濃度に形成されているため、この部分における電界分布は、通常のｐ＋型埋め込み層を有しない構造のＭＯＳＦＥＴと同様となり、この通常のＭＯＳＦＥＴによる耐圧と同様の素子周辺部の耐圧が得られる。
【００７３】
（第８の実施形態）
次に、本発明の第７の実施の形態に係わるパワーＭＯＳＦＥＴの製造方法について説明する。
【００７４】
図８は、このＭＯＳＦＥＴの製造工程を示す模式的な工程図である。
【００７５】
まず、図８（ａ）に示すように、ドレイン層としてのｎ＋型基板２上にｎ−型ドリフト層１’をエピタキシャル成長させる。
【００７６】
続いて図８（ｂ）に示すように、前記ｎ−型ドリフト層１’上にマスクを介して素子形成領域部分にｎ型不純物としてのリンをイオン注入する。
【００７７】
イオン注入後、図８（ｃ）に示すように、イオン注入されたｎ−型ドリフト層１’上に、更にｎ−型ドリフト層１’をエピタキシャル成長させる。このエピタキシャル成長工程において、リンが再拡散され素子形成領域上のｎ−型ドリフト層１’部分が所定不純物濃度のｎ型ドリフト層１に変換される。
【００７８】
続いて図８（ｄ）に示すように、前記ｎ−型ドリフト層１’上にマスクを介して素子形成領域部分にｐ型不純物としてのボロン並びにｎ型不純物としてのリンを順次イオン注入する。
【００７９】
イオン注入後、図８（ｅ）に示すように、イオン注入されたｎ−型ドリフト層１’上に、更にｎ−型ドリフト層１’をエピタキシャル成長させる。このエピタキシャル成長工程において、ボロン並びにリンが再拡散され、最下層のｐ＋型埋め込み層９ｃが形成され、このｐ＋型埋め込み層９ｃ，９ｃ間のｎ−型ドリフト層１部分はｎ型ドリフト層１に変換される。
【００８０】
次に図８（ｆ）に示すように、ｎ−型ドリフト層１’の素子形成領域部分上にリンをイオン注入する。
【００８１】
続いて図８（ｇ）に示すように、イオン注入されたｎ−型ドリフト層１’上に、更にｎ−型ドリフト層１をエピタキシャル成長させる。このエピタキシャル成長工程において、リンが再拡散され、ｐ＋型埋め込み層９ｃ及びｎ型ドリフト層１部分上のｎ−型ドリフト層１’部分がｎ型ドリフト層１に変換される。
【００８２】
次に図８（ｈ）に示すように、前記ｎ−型ドリフト層１’上にマスクを介して素子形成領域部分にボロン並びにリンを順次イオン注入する。
【００８３】
イオン注入後、図８（ｉ）に示すように、イオン注入されたｎ−型ドリフト層１’上に、更にｎ−型ドリフト層１’をエピタキシャル成長させると共に、中間層のｐ＋型埋め込み層９ｂ及びこの埋め込み層９ｂ間にｎ型ドリフト層１を形成する。
【００８４】
以下同様に、図８（ｆ）乃至図８（ｉ）工程を繰り返すことにより、図８（ｊ）に示すように、素子形成領域部分において、３層のｐ＋型埋め込み層９ａ、９ｂ、９ｃ及び各層間にｎ型ドリフト層１が、また最上層がエピタキシャル成長されたｎ−型ドリフト層１’からなる構造が形成される。
【００８５】
次に図８（ｋ）に示すように、前記ｎ−型ドリフト層１’上の素子形成領域部分にリンをイオン注入する。
【００８６】
イオン注入後、図８（Ｌ）に示すように、イオン注入されたｎ−型ドリフト層１’上に、更にｎ−型ドリフト層１’をエピタキシャル成長させる。このエピタキシャル成長工程において、リンを再拡散させて素子形成領域部分における前記ｎ−型ドリフト層１’部分をｎ型ドリフト層１に変換する。
【００８７】
その後、図７に示すように、素子形成領域部分のｎ型ドリフト層１表面に選択的に、ｐ型ベース層４を拡散形成し、続いてこのｐ型ベース層４表面に、ｎ＋型ソース層５を選択的に形成する。
【００８８】
最後に、ゲート酸化膜６を形成した後、ゲート電極７、ソース電極８、ドレイン電極２をそれぞれ形成することにより、ＭＯＳＦＥＴが完成される。
【００８９】
（第９の実施形態）
次に、パワーＭＯＳＦＥＴにおいて、ターンオン時のｐ型埋込み層の充電に関する例を、第９の実施形態として説明する。
【００９０】
図９（ａ）は本発明の第９の実施の形態に係わるパワーＭＯＳＦＥＴの駆動方法を説明するための回路図、図９（ｂ）はゲート電流と時間との関係を示す図である。この実施形態におけるパワーＭＯＳＦＥＴは、例えば、図１に示す第１実施形態のパワーＭＯＳＦＥＴである。
【００９１】
図９（ａ）に示すように、第９の実施形態に係わるＭＯＳＦＥＴの駆動回路は、ＭＯＳＦＥＴの第１のゲート電極Ｇ１が、入力信号Ｖｉｎ１が印可される第１の入力端子９１に直接接続されている。また、第２のゲート電極Ｇ２が、キャパシタＣと抵抗ｒｇ２とを並列接続したゲート入力回路９５とこのゲート入力回路９５に直接接続された抵抗ｒｇ１を介して入力信号Ｖｉｎ２が印可される第２の入力端子９２に接続されている。そしてドレイン電極ＤがＶｄｄ電源端子９３に負荷抵抗ＲＬを介して接続され、且つソース電極Ｓが接地（Ｖｇｎｄ）電源端子９４にそれぞれ接続されている。
【００９２】
次にこの駆動回路によるターンオン動作を説明する。
【００９３】
まず、図９（ｂ）に示すように、第１の入力端子９１に振幅１５Ｖの入力信号Ｖｉｎ１を印加し、第２の入力端子９２に振幅５Ｖの入力信号Ｖｉｎ２を印加すると、第１のゲート電極７直下のｐ型ベース層４にチャンネルができ、ｎ＋型ソース層５よりｎ−型ドリフト層１中に電子が注入され、ｎ−型ドリフト層１中の空乏化が解消される。これと同時に、第２の入力端子９２に入力信号Ｖｉｎ２が入力された瞬間に、キャパシタＣを通じて変位電流が流れるため、第２のゲート電極Ｇ２に、より大きなゲート電流Ｉｇ２が流れ、ｐ＋型埋込み層９ａ、９ｂ、９ｃにホールがより多く供給されて、ｐ＋型埋込み層９ａ、９ｂ、９ｃの空乏化が速やかに解消される。この結果、速やかにターンオンさせることができる。そして上記第２のゲート電極Ｇ２に流れるゲート電流Ｉｇ２は、キャパシタＣが充電された後は、極めて小さい値を示す。
【００９４】
上記の駆動回路によれば、純粋にユニポーラモードで動作するＭＯＳＦＥＴでは、ｐ＋型埋込み層にホールが供給することが無く、ｐ＋型埋込み層が空乏化は解消できなく、ターンオン時間が長くなってしまうが、本発明の実施形態に係わるＭＯＳＦＥＴでは、ターンオン時にゲート電流を大きく流して、バイポーラモードで動作させることが可能であり、ｐ＋型埋込み層にホールを供給することができる。そのため、より高速なターンオンが実現できる。
【００９５】
以上、本発明を第１乃至第９の実施形態により説明したが、この発明は、第１乃至第９の実施形態に限定されるものではない。
【００９６】
例えば、第１乃至第８の実施形態では、ｐ＋型埋込み層を三層として説明を行ったが、ｐ＋型埋込み層は一層以上有する構造であれば、同様の効果を得ることができる。
【００９７】
また各層の複数のｐ＋型埋込み層は、それぞれ、独立したストライプ状に形成したが、ストライプの終端で互いに接続した構造にしてもよい。
【００９８】
また各層のｐ＋型埋込み層は、ストライプ状に限らず、メッシュ状、またはドット状に形成してもよい。
【００９９】
またｐ型ベース層及びｎ＋型ソース層は、ストライプ状に形成したが、ドット状に形成してもよい。
【０１００】
また半導体としてシリコン（Ｓｉ）を用いたＭＯＳＦＥＴを説明したが、半導体としとは、例えばシリコンカーバイト（ＳｉＣ）等の化合物半導体を用いることができる。
【０１０１】
また第１の実施形態では、ｐ＋型キャリア層を複数のｐ型ベース層のうち、片側のｐ＋型キャリア層の側方にみ配置したが、両方のｐ＋型キャリア層の側方にそれぞれ配置してもよく、複数のｐ型ベース層を取り囲むように環状構造に形成してよい。
【０１０２】
また第２及び第３の実施形態では、ｐ＋型キャリア層をストライプ状に形成したが、環状、格子状、またはドット状に形成してもよい。
【０１０３】
また第２及び第３の実施形態では、ｐ＋型キャリア層は、ドレイン電極に接続されているが、ドレイン電極と電気的に分離し、ドレイン電極と独立した電位を印可するようにしてもよい。
【０１０４】
また第２の実施形態では、ｐ＋型キャリア層とこれと隣接するｎ＋型ドレイン層を同一表面積を有するように形成したが、ｐ＋型キャリア層の表面積が広面積に形成してもよい。
【０１０５】
また第３の実施形態では、ｐ＋型キャリア層の表面積を、これと隣接するｎ＋型ドレイン層の表面積より広く形成したが、ｐ＋型キャリア層とｎ＋型ドレイン層の表面積を同一面積に形成してもよい。
【０１０６】
また第９の実施形態では、第１及び第２の入力端子を別個に設けたが、第１及び第２の入力端子を共通にし、同一の入力信号を印加するようにすれば、駆動回路が簡単にできる。
【０１０７】
また第１乃至第９の実施形態では、プレナー型のパワーＭＯＳＦＥＴを例示したが、本発明は、トレンチ構造のパワーＭＯＳＦＥＴにも適用可能である。
【０１０８】
更には電位が浮遊した埋込層を有するＭＯＳＦＥＴのみで説明したが、本発明の構造及び駆動方法は、電位が浮遊した層を有する素子であれば、適用可能である。
【０１０９】
【発明の効果】
以上説明したように、本発明によれば、高耐圧を維持しつつ、ターンオン時間が短く、高速動作が可能で、しかもスイッチング損失が少ない電力用半導体装置と、この電力用半導体装置のターンオン時間の短縮に有効な駆動方法とを提供することができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図２】本発明の第２の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図３】本発明の第３の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図４】本発明の第４の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図５】本発明の第５の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図６】本発明の第６の実施形態に係るパワ-ＭＯＳＦＥＴの製造工程を示す模式的な工程図。
【図７】本発明の第７の実施形態に係るパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【図８】本発明の第８の実施形態に係るパワ-ＭＯＳＦＥＴの製造工程を示す模式的な工程図。
【図９】図９（ａ）は本発明の第９の実施形態に係るパワーＭＯＳＦＥＴの駆動回路を示す回路図、図９（ｂ）は入力電流と時間の関係を示す図。
【図１０】従来のパワ-ＭＯＳＦＥＴの構成を模式的に示す断面図。
【符号の説明】
１、１１１…ｎ−型ドリフト層（第１の半導体層）、
２、１１２…ｎ＋型ドレイン層（高濃度半導体層）、
３、１１３…ドレイン電極Ｄ（第１の主電極）、
４、１１４…第１のｐ型ベース層（第２の半導体層）、
５、１１５…ｎ＋型ソース層（第３の半導体層）、
６，１１６…Ｓｉ酸化膜（ゲート絶縁膜）、
７、１１７…第１のゲート電極Ｇ１（第１の制御電極）、
８，１１８…ソース電極Ｓ（第２の主電極）、
９ａ、９ｂ、９ｃ、１１９ａ、１１９ｂ、１１９ｃ…ｐ＋埋込み層、
１０…ｐ＋型 キャリア注入層（第４の半導体層）、
１１…第２のゲート電極（第２の制御電極）
２０，３０…ｐ＋型 キャリア注入層（第５の半導体層）、
４４…第２のｐ型ベース層（第６の半導体層）、
４５…ｎ＋型ソース層（第７の半導体層）、
４６…Ｓｉ酸化膜（ゲート絶縁膜）、
４７…ソース電極（フローティング電極）、
５０ａ、５０ｂ、５０ｃ…ｐ−型接続層、
９１…第１の入力端子、
９２…第２の入力端子、
９３…Ｖｄｄ電源端子、
９４…接地（Ｖｇｎｄ）電源端子、
９５…ゲート入力回路、
ｒｇ１，ｒｇ２…抵抗、
ＲＬ…負荷抵抗、
Ｃ…キャパシタ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device used for high power control and a driving method of the element, and more particularly to a power MOSFET and a driving method thereof.
[0002]
[Prior art]
Recently, power MOSFETs for unipolar operation are widely used as power semiconductor devices for power control, but MOSFETs can be expected to operate at high speed, but the on-state is increased as the withstand voltage becomes higher than bipolar operation IGBTs. Therefore, there is a problem that the voltage drop becomes high and the conduction loss becomes large. As an example of a MOSFET that solves this problem, for example, one disclosed in Japanese Patent Laid-Open No. 9-191109 is known.
[0003]
FIG. 10 is a cross-sectional view schematically showing the configuration of this type of MOSFET.
[0004]
In this MOSFET, an n + -type drain layer 112 is formed on one surface of an n − -type drift layer 111, and a drain electrode 113 is formed on the n + -type drain layer 112. A plurality of p-type base layers 114 are selectively formed on the other surface of the n − -type drift layer 111, and an n + -type source layer 115 is selectively formed on the surface of each p-type base layer 114. Yes. Further, a gate insulating film is formed on a region from the p-type base layer 114 and the n + type source layer 115 to the other p-type base layer 114 and the n + type source layer 115 through the n− type drift layer 111. A gate electrode 117 is formed via 116. A source electrode 118 is formed on one of the p-type base layer 114 and the n + -type source layer 115 and on the other of the p-type base layer 114 and the n + -type source layer 115 so as to sandwich the gate electrode 117. Is formed. In the n − -type drift layer 111 between the p-type base layer 114 and the drain electrode 112, three p + -type buried layers 119a, 119b, and 119c are selectively spaced apart from each other. It is embedded and formed. The p + type buried layers 119a, 119b, and 119c are all in an electrically floating state.
[0005]
[Problems to be solved by the invention]
In such a MOSFET, in the off state, the electric field in the n − type drift layer 111 is divided according to the number of divisions of the n − type drift layer 111 divided by the p + type buried layers 119a, 119b, and 119c. can do. For example, when the p + type buried layers 119a, 119b, and 119c are three layers, the electric field of the n− type drift layer 111 is divided into four, and assuming that the device has a withstand voltage of 600V, the p + type buried layers 119a, 119b, and 119c The withstand voltage required for this is 150V. Since the breakdown voltage is reduced in this way, the impurity concentration of the n − type drift layer 111 can be quadrupled compared to the case where the p + type buried layers 119a, 119b, and 119c are not provided. The electric resistance can be reduced, and therefore the on-resistance of the element can be reduced to about 1/4.
[0006]
However, in the MOSFET having such a structure, once the p + type buried layer is depleted in the off state, the p + type buried layer is not normally turned on at the time of turn-on until the depletion of the p + type buried layer is eliminated. Long time of 100 μs or longer.
[0007]
Further, immediately after the turn-on, a depletion layer extends from the p + type buried layer to the periphery, and an area where carriers are effectively conducted is reduced. Therefore, the element itself has a high resistance and a switching loss is increased.
[0008]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a high-power semiconductor device that can shorten the turn-on time, operate at high speed, and has low switching loss, and a method for driving the device.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, a power semiconductor device according to a first aspect of the present invention is electrically connected to a first semiconductor layer of a first conductivity type and one surface of the first semiconductor layer. A first main electrode, a second semiconductor layer of a second conductivity type selectively formed on the other surface of the first semiconductor layer, and a surface selectively formed on the surface of the second semiconductor layer. A first semiconductor layer of the first conductivity type, a second main electrode electrically connected to the second semiconductor layer and the third semiconductor layer, the first semiconductor layer, A first control electrode formed on the surfaces of the second semiconductor layer and the third semiconductor layer with an insulating film interposed therebetween; and in the first semiconductor layer, the second semiconductor layer and the At least one second conductive type buried layer having a potential floating and selectively buried between the first main electrode and the first semiconductor; A fifth semiconductor layer of a second conductivity type selectively formed on the other surface of the layer, and a second control electrode which is electrically connected to the semiconductor layer of the fifth, A first conductivity type high concentration semiconductor layer having a higher impurity concentration than the first semiconductor layer is formed between one surface of the first semiconductor layer and the first main electrode, and The semiconductor layer 5 is selectively formed on the high-concentration semiconductor layer, and one end on the first main electrode side is flush with the high-concentration semiconductor layer, and the other end penetrates the high-concentration semiconductor layer. And formed into a shape reaching the first semiconductor layer. It is characterized by that.
[0010]
A power semiconductor device according to a second aspect of the present invention is characterized in that the first main electrode and the second control electrode are electrically connected in common.
[0011]
Furthermore, the power semiconductor device of the invention corresponding to claim 3 is characterized in that the first main electrode and the second control electrode are formed electrically independently.
[0012]
Furthermore, in the power semiconductor device of the invention corresponding to claim 4, the fifth semiconductor layer is one surface of the first semiconductor layer or the high concentration semiconductor layer on the first main electrode side. On the surface, the surface area of the fifth semiconductor layer and the surface area of the first semiconductor layer portion adjacent to this layer or the adjacent high concentration semiconductor layer portion are the same area.
[0013]
Furthermore, in the power semiconductor device of the invention corresponding to claim 5, the fifth semiconductor layer is one surface of the first semiconductor layer or the high-concentration semiconductor layer on the first main electrode side. On the surface, the surface area of the fifth semiconductor layer is wider than the surface area of the first semiconductor layer portion adjacent to this layer or the adjacent high concentration semiconductor layer portion.
[0014]
Furthermore, the power semiconductor device of the invention corresponding to claim 6 is the first main layer electrically connected to the first semiconductor layer of the first conductivity type and one surface of the first semiconductor layer. An electrode, a second conductivity type second semiconductor layer selectively formed on the other surface of the first semiconductor layer, and a first conductivity type selectively formed on the second semiconductor surface. A third semiconductor layer; a second main electrode electrically connected to surfaces of the second semiconductor layer and the third semiconductor layer; the first semiconductor layer and the second semiconductor layer; A first control electrode formed on the third semiconductor layer via an insulating film, and a first control electrode selectively formed on the other surface of the first semiconductor layer, spaced from the second semiconductor layer; A second conductive type sixth semiconductor layer; a first conductive type seventh semiconductor layer selectively formed on a surface of the sixth semiconductor layer; and the sixth semiconductor layer A floating electrode having a potential floating electrically connected to the body layer and the seventh semiconductor layer; and an insulating film on the first semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer. And a second control electrode buried in the first semiconductor layer, and at least one second conductivity type buried layer having a floating potential. Yes.
[0015]
Furthermore, in the power semiconductor device according to the seventh aspect of the present invention, the impurity concentration in the periphery of the element formation region of the first semiconductor layer is lower than the impurity concentration of the element formation region. It is characterized by.
[0016]
Furthermore, in the power semiconductor device of the invention corresponding to claim 8, the fifth semiconductor layer is one surface of the first semiconductor layer, or the high-concentration semiconductor layer on the first main electrode side. On the surface, the surface area of the fifth semiconductor layer is wider than the surface area of the first semiconductor layer portion adjacent to this layer or the adjacent high concentration semiconductor layer portion.
[0017]
Furthermore, the power semiconductor device of the invention corresponding to claim 9 is a first main layer electrically connected to the first semiconductor layer of the first conductivity type and one surface of the first semiconductor layer. An electrode, a second conductivity type second semiconductor layer selectively formed on the other surface of the first semiconductor layer, and a first conductivity type selectively formed on the second semiconductor surface. A third semiconductor layer; a second main electrode electrically connected to surfaces of the second semiconductor layer and the third semiconductor layer; the first semiconductor layer and the second semiconductor layer; A first control electrode formed on the third semiconductor layer via an insulating film, and a first control electrode selectively formed on the other surface of the first semiconductor layer, spaced from the second semiconductor layer; A second conductive type sixth semiconductor layer; a first conductive type seventh semiconductor layer selectively formed on a surface of the sixth semiconductor layer; and the sixth semiconductor layer A floating electrode having a potential floating electrically connected to the first semiconductor layer and the seventh semiconductor layer, and an insulating film on the first semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer. And a second conductivity type buried layer having a potential floating at least one or more selectively buried in the first semiconductor layer. .
[0018]
Furthermore, a power semiconductor device according to a tenth aspect of the invention includes a first conductive type first semiconductor layer and a first main electrically connected to one surface of the first semiconductor layer. An electrode; a second semiconductor layer of a second conductivity type selectively formed on the other surface of the first semiconductor layer; and a first conductor selectively formed on the surface of the second semiconductor layer. A third semiconductor layer of the mold, a second main electrode electrically connected to the second semiconductor layer and the third semiconductor layer, the first semiconductor layer and the second semiconductor layer And a control electrode formed on the surface of the third semiconductor layer via an insulating film, and in the first semiconductor layer, between the second semiconductor layer and the first main electrode. And at least one second conductivity type buried layer floating in potential selectively embedded in the semiconductor layer and having a lower impurity concentration than the second conductivity type buried layer. It is, is characterized by and having a connecting layer for connecting the second semiconductor layer and the second conductivity type buried layer.
[0019]
Furthermore, in the power semiconductor device according to the invention corresponding to claim 11, the impurity concentration in the periphery of the element formation region of the first semiconductor layer is lower than the impurity concentration of the element formation region. It is characterized by.
[0020]
Furthermore, the drive system of the invention corresponding to claim 12 is a drive method for driving a power semiconductor semiconductor device, wherein the current flowing through the second control electrode is set larger than the steady state only at the time of turn-on. It is a feature.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. Moreover, the same number is attached | subjected to the same part in drawing.
[0022]
(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a configuration of a power MOSFET according to the first embodiment of the present invention.
[0023]
In this MOSFET, a high-concentration semiconductor layer, for example, an n + -type drain layer 2 is formed on one surface of an n − -type drift layer 1 as a first semiconductor layer. A drain electrode 3 as a main electrode is formed. As an example, the n − type drift layer 1 is about 1 × 10 10. 15 cm -3 As an example, the n + -type drain layer 2 is formed to have a thickness of about 60 × m. 18 cm -3 The thickness is about 180 μm. The n + type drain layer 2 may be formed as necessary.
[0024]
Also, a plurality of first p-type base layers 4 as second semiconductor layers are selectively formed on the other surface of the n − -type drift layer 1 at a distance from each other and diffused in a stripe shape. On the surface of each first p-type base layer 4, n + -type source layers 5 as third semiconductor layers are selectively formed in a diffused manner in a stripe shape. The first p-type base layer 4 is about 3 × 10 10 as an example. 17 cm -3 As an example, the n + -type source layer 5 is formed to have a depth of about 2.0 μm. 20 cm -3 And a depth of about 0.2 μm.
[0025]
Further, on the region from the first p-type base layer 4 and the n + -type source layer 5 to the other first p-type base layer 4 and the n + -type source layer 5 through the n − -type drift layer 1. A first gate electrode 7 as a first control electrode is formed in a stripe shape through a gate insulating film having a thickness of about 0.1 μm, for example, a Si oxide film 6. On one of the first p-type base layer 4 and n + -type source layer 5 and on the other of the first p-type base layer 4 and n + -type source layer 5 so as to sandwich the first gate electrode 7 The source electrode 8 as the second main electrode is formed in a stripe shape. In the n − -type drift layer 1 between the drain electrode 3 and the p-type base layer 4, for example, three p + -type buried layers 9 a, 9 b and 9 c having a stripe shape are selectively formed. It is embedded and formed. The p + type buried layers 9a, 9b, 9c are formed in, for example, an elliptical shape having a long axis in the lateral direction, and as an example, about 1 × 10 18 cm -3 With a major axis of about 3.0 μm and a minor axis of about 2.5 μm, with a vertical interval of 15.5 μm and a horizontal interval of about 6.0 μm. Yes.
[0026]
The p + type buried layers 9a, 9b, 9c are all in an electrically floating state.
[0027]
In the MOSFET according to this embodiment, the surface of the n − type drift layer 1 in the periphery of the first p type base layer has a second p + type base as a sixth semiconductor layer having a stripe shape. A layer 10 (p + type carrier injection layer) is formed, and a second control electrode, for example, a second gate electrode 11 is formed on the p + type carrier injection layer 10. As an example, the p + type carrier injection layer 10 has a depth of about 2.0 μm and an impurity concentration peak value of 3 × 10 5. 19 cm -3 Is formed.
[0028]
In the MOSFET of the first embodiment, the p + type carrier injection layer 10 is formed in the n − type drift layer 1 around the first p type base layer 4, and the second layer is formed on the p + type carrier injection layer 10. The gate electrode 11 is provided so that a control voltage can be applied. Therefore, by applying a positive bias voltage to the second gate electrode 11 at the time of turn-on, the diode formed by the p + -type carrier injection layer 10 and the n − -type drift layer 1 is turned on, and the p + -type carrier injection layer 10 Holes are injected into the n − type drift layer 1. By this hole injection, depletion of the p + type buried layers 9a, 9b, and 9c is quickly eliminated, and the MOSFET is immediately turned on. Therefore, the turn-on time is as short as about 50 ns, high speed operation is possible, and switching loss is extremely small.
[0029]
(Second embodiment)
Next, a power MOSFET according to a second embodiment of the present invention will be described.
[0030]
FIG. 2 is a cross-sectional view schematically showing the configuration of the power MOSFET. The same parts as those in FIG. 1 are denoted by the same reference numerals, detailed description thereof is omitted, and only different parts will be described here.
[0031]
In this embodiment, a p + type carrier injection layer is provided on the surface of the n − type drift layer on the drain electrode side, and holes are injected from the drain electrode side. That is, in this MOSFET, an n + type drain layer 2 is formed on one surface of an n − type drift layer 1, a drain electrode 3 is formed on the n + type drain layer 2, and the n − type drift layer is formed. A plurality of p-type base layers 4 are selectively formed on the other surface of 1, and an n + -type source layer 5 is selectively formed on the surface of each p-type base layer 4.
[0032]
Further, a gate insulating film is formed on a region from the p-type base layer 4 and the n + type source layer 5 to the other p-type base layer 4 and the n + type source layer 5 through the n− type drift layer 1. 6, a gate electrode 7 is formed, and on the one p-type base layer 4 and the n + -type source layer 5 and the other p-type base layer 4 and the n + -type source layer 5 so as to sandwich the gate electrode 7. On the top, a source electrode 8 is formed.
[0033]
In the n − type drift layer 1 between the drain electrode 3 and the p type base layer 4, three p + type buried layers 9 a, 9 b, 9 c are selectively buried, and Is also in an electrically floating state.
[0034]
In the MOSFET according to this embodiment, a striped p + type carrier injection layer 20 as a fifth semiconductor layer is selectively formed in the n + type drain layer 2. The p + type carrier injection layer 20 is provided between the lowermost p + type buried layer 9c and the drain electrode 3, and one end of the p + type carrier injection layer 20 is connected to the drain electrode 3 and the other end. Is formed so as to penetrate the n + -type drain layer 2 and reach the n − -type drift layer 1.
[0035]
As an example, the p + type carrier injection layer 20 has a depth of about 185 μm and a depth of about 1 × 10 6 so as to be inserted into the n − type drift layer 1 by about 5.0 μm. 19 cm -3 The impurity concentration is formed. In addition, the p + type carrier injection layer 20 and the adjacent n + type drain layer 2 are both about 3.0 μm wide and have the same surface area.
[0036]
In the MOSFET of the second embodiment, when a drain current flows, a voltage is applied to the pn junction formed by the n − type drift layer 1 and the p + type carrier injection layer 20, and the p + type carrier injection layer 20 Holes are injected into the n − type drift layer 1. By this hole injection, depletion of the p + type buried layers 9a, 9b, and 9c is quickly eliminated, and the MOSFET is immediately turned on. In addition, since the p + type carrier injection layer 20 is disposed immediately below and adjacent to the p + type buried layer, the turn-on time is as short as about 70 ns, enabling high-speed operation, and switching loss is extremely small. Further, since the p + type carrier injection layer 20 is formed below the first p type base layer, the device can be miniaturized compared to the MOSFET of the first embodiment.
[0037]
(Third embodiment)
Next, a power MOSFET according to a third embodiment of the present invention will be described.
[0038]
FIG. 3 is a cross-sectional view schematically showing the configuration of the power MOSFET. The same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.
[0039]
That is, this power MOSFET is a modified configuration of the second embodiment of the present invention. As shown in FIG. 3, the striped p + -type carrier injection layer 30 as the fifth semiconductor layer is formed of the lowermost layer p +. The n + type drain layer 2 located between the type buried layer 9c and the drain electrode 3 is selectively provided at the same layer thickness as the n + type drain layer 2 and one end is n + type on the drain electrode side. The drain layer 2 has the same plane as the surface and the other end is in contact with the n − type drift layer 1. Moreover, the p + type carrier injection layer 30 and the n + type drain layer 2 adjacent to the p + type carrier injection layer 30 are formed to have a width of about 5.0 μm and a width of about 1.0 μm, respectively, and p + type on the surface of the n + type drain layer 2. The surface area of the carrier injection layer 30 is larger than that of the adjacent n + type drain layer 2 portion.
[0040]
In the MOSFET of the third embodiment, the surface area of the p + type carrier injection layer 30 is wide, and therefore, it is applied to the pn junction formed by the p + type carrier injection layer 30 and the n− type drift layer 1. The voltage is increased, hole injection from the p + type carrier injection layer 30 to the n − type drift layer 1 is promoted, high speed operation is possible, and switching loss is small as in the second embodiment.
[0041]
(Fourth embodiment)
Next, a power MOSFET according to a fourth embodiment of the present invention will be described.
[0042]
FIG. 4 is a cross-sectional view schematically showing the configuration of this power MOSFET.
[0043]
In this MOSFET, a high-concentration semiconductor layer, for example, an n + -type drain layer 2 is formed on one surface of an n − -type drift layer 1 as a first semiconductor layer. A drain electrode 3 as a main electrode is formed.
[0044]
Further, a first p-type base layer 4 as a second semiconductor layer is selectively formed on the other surface of the n − -type drift layer 1, and on the surface of the first p-type base layer 4, An n + type source layer 5 as a third semiconductor layer is selectively formed.
[0045]
On the n − type drift layer 1, the first p type base layer 4, and the n + type source layer 5, a first control electrode serving as a first control electrode is interposed via a gate insulating film, for example, a Si oxide film 6. The gate electrode 7 is formed, and the source electrode 8 as the second main electrode is formed on the first p-type base layer 4 and the n + -type source layer 5 outside the first gate electrode 7. .
[0046]
Further, a second p-type base layer 44 as the sixth semiconductor layer is selectively diffused on the other surface of the n − -type drift layer 1 while being separated from the first p-type base layer 4. A second n + -type source layer 45 as a seventh semiconductor layer is selectively formed on the surface of the second p-type base layer 44.
[0047]
On the n − type drift layer 1, the second p type base layer 44, and the second n + type source layer 45, a gate insulating film, for example, a Si oxide film 46 is used as a second control electrode. The second gate electrode 47 is formed, and the second gate d electrode 47 is electrically connected to the first gate electrode 7 here. As a floating electrode in which a potential is floated on the second p-type base layer 44 and the second n + -type source layer 45 inside the second gate electrode 47, that is, on the first gate electrode 7 side. A source electrode 48 is formed.
[0048]
In the n − type drift layer 1 between the drain electrode 3 and the p type base layers 4 and 44, for example, three p + type buried layers 9a, 9b and 9c are selectively buried. Is formed. The p + type buried layers 9a, 9b, 9c are all in an electrically floating state.
[0049]
In the MOSFET of the fourth embodiment, the floating electrode forms a channel under the second gate electrode when a voltage equal to or higher than the threshold voltage is applied to the second gate electrode, and the second n + -type source layer 45 is formed. Then, electrons are injected into the n − type drift layer 1. Therefore, the potential of the floating electrode rises, and a positive bias voltage is applied to the pn junction formed by the second p-type base layer 44 and the n − -type drift layer 1 connected to the floating electrode, and the first Holes are injected into the n − -type drift layer 1 from the two p-type base layers 44. As a result, depletion of the p + type buried layers 9a, 9b, and 9c is quickly eliminated, and the MOSFET is immediately turned on. As a result, high-speed operation is possible and switching loss is reduced.
[0050]
The first and second p-type base layers 4 and 44, the first and second source layers 5 and 45, the gate insulating films 6 and 46, the first and second gate electrodes 7 and 47, and the source electrode 7 Since the floating electrode 47 and the floating electrode 47 can be formed in the same process, the MOSFET can be easily manufactured.
[0051]
(Fifth embodiment)
Next, a power MOSFET according to a fifth embodiment of the present invention will be described.
[0052]
FIG. 5 is a cross-sectional view schematically showing the configuration of the power MOSFET. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.
[0053]
That is, this power MOSFET is a modified configuration of the first embodiment according to the present invention. As shown in FIG. 5, the uppermost layer is formed between the p-type base layer 4 and the uppermost p + type buried layer 9a. Between the p + type buried layer 9b and the p + type buried layer 9b of the intermediate layer, and between the p + type buried layer 9b of the intermediate layer and the p + type buried layer 9c of the lowermost layer by p− type connection layers 50a, 50b, 50c. It is the structure which connected sequentially. As an example, each of the p-type connection layers 50a, 50b, and 50c is about 1 × 10. 15 cm -3 And a width of about 2.0 μm. The impurity concentration of the n − type drift layer 1 is about 2 × 10. 15 cm -3 It is.
[0054]
In the MOSFET of the fifth embodiment, the p− type connection layers 50a, 50b, and 50c are completely depleted when a high voltage is applied, and the electric field in the n− type drift layer 1 is p + type. Since the buried layers 9a, 9b, and 9c are divided for each p + type buried layer as in the case where the buried layers 9a, 9b, and 9c are not connected, the same breakdown voltage as in the first embodiment is maintained. In addition, at the time of turn-on, carriers are efficiently supplied from the source electrode directly to the p + type buried layers 9a, 9b, and 9c through the p− type connection layers 50a, 50b, and 50c, and the p + type buried layers are charged immediately. Is done. As a result, the depletion of the p + type buried layers 9a, 9b and 9c is faster than the MOSFETs of the above embodiments, and the ON state of the MOFET is faster, so that the turn-on time is extremely short, about 400 ns, and the operation is faster. Is possible.
[0055]
(Sixth embodiment)
Next, a method for manufacturing a power MOSFET according to the fifth embodiment of the present invention will be described.
[0056]
FIG. 6 is a schematic process diagram showing the manufacturing process of this MOSFET.
[0057]
First, as shown in FIG. 6A, an n − type drift layer 1 as a first semiconductor layer is epitaxially grown on an n + type substrate 2 as a drain layer.
[0058]
Subsequently, as shown in FIG. 6B, boron as a p-type impurity and phosphorus as an n-type impurity are sequentially ion-implanted onto the n − -type drift layer 1 through a mask.
[0059]
After the ion implantation, as shown in FIG. 6C, a p − type layer 50 which finally becomes a p − type connection layer is epitaxially grown on the ion implanted n − type drift layer 1. In this epitaxial growth step, boron and phosphorus are re-diffused to form the lowermost p + type buried layer 9c, and at the same time, a portion of the n− type drift layer 1 having a predetermined concentration is formed between the p + type buried layers 9c, 9c. The
[0060]
Next, as shown in FIG. 6D, phosphorus is ion-implanted into the surface of the p − type layer 50 portion located between the p + type buried layers 9c and 9c.
[0061]
After the ion implantation, as shown in FIG. 6E, the p − type layer 50 is further epitaxially grown on the ion implanted p − type layer 50. In this epitaxial growth step, phosphorus is re-diffused to divide the first p-type layer 50, and a p-type connection layer 50c extending on the lowermost p + type buried layer 9c is formed.
[0062]
Subsequently, as shown in FIG. 6 (f), boron and phosphorus are sequentially ion implanted into the surface of the p + type layer 50 corresponding to the p + type buried layer 9c and the n− type drift layer 1 through a mask, respectively. To do.
[0063]
After the ion implantation, as shown in FIG. 6G, the p − type layer 50 is further epitaxially grown on the ion implanted p − type layer 50. In this epitaxial growth step, boron and phosphorus are re-diffused to form a p + type buried layer 9b as an intermediate layer on the p− type connection layer 50c, and at the same time n having a predetermined concentration between the p + type buried layers 9b and 9b. A − type drift layer 1 portion is formed, and a p − type connection layer 50c is formed between the lowermost p + type buried layer 9c and the intermediate layer p + type buried layer 9b.
[0064]
Similarly, by repeating the steps of FIGS. 6D to 6G, the uppermost p + type buried layer 9a is formed on the p− type connection layer 50b as shown in FIG. 6H. A p − type buried layer 9a is formed with a portion of the n − type drift layer 1 having a predetermined concentration, and is epitaxially grown on the uppermost p + type buried layer 9a and the n − type drift layer 1 portion. A structure having a layer 50 is formed.
[0065]
Next, as shown in FIG. 6 (i), phosphorus is ion-implanted into the surface of the p− type layer 50 portion located between the p + type buried layers 9a and 9a.
[0066]
Next, as shown in FIG. 6J, the n − type drift layer 1 is further epitaxially grown on the surfaces of the p − type connection layer 50 a and the n − type drift layer 1. In the epitaxial growth process of the n − type drift layer 1, phosphorus is re-diffused, the p + type buried layers 9 a, 9 b and 9 c are connected by the p − type connection layers 50 a and 50 b, and the uppermost p + type buried layer 9 a is formed. A structure in which the p− type connection layer 50a extends in the vertical direction and the n− type drift layer 1 extends in the vertical direction is formed.
[0067]
Thereafter, as shown in FIG. 5, a p-type base layer 4 is selectively diffused on the surface of the n − -type drift layer 1, and then an n + -type source layer 5 is selected on the surface of the p-type base layer 4. Form.
[0068]
Finally, after forming the gate insulating film 6, the gate electrode 7, the source electrode 8, and the drain electrode 2 are formed, thereby completing the MOSFET.
[0069]
(Seventh embodiment)
Next, a power MOSFET according to a seventh embodiment of the present invention will be described.
[0070]
FIG. 7 is a cross-sectional view schematically showing the configuration of this power MOSFET. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.
[0071]
That is, this MOSFET is a modified configuration of each embodiment, and is intended to prevent breakdown resistance degradation at the element termination portion. Specifically, as shown in FIG. 7, the drift layer around the element formation region 1 ′ has a configuration in which it is formed in an n − type having a lower impurity concentration than the n type drift layer 1 in the element forming region portion. In the MOSFET of this embodiment, assuming that the breakdown voltage is 600 V, the n-type drift layer 1 in the element formation region portion is 1 × 10 5 as an example. 15 cm -3 As an example, the drift layer 1 ′ around the element formation region is 2 × 10 2, which is the same as the impurity concentration of the drift layer in the MOSFET having a structure having no p + type buried layer. 14 cm -3 The impurity concentration is formed.
[0072]
Therefore, in the MOSFET of the seventh embodiment, since the drift layer around the element formation region is formed with a low impurity concentration, the electric field distribution in this portion is a MOSFET having a structure without a normal p + type buried layer. Thus, the breakdown voltage of the peripheral portion of the element similar to the breakdown voltage of this normal MOSFET can be obtained.
[0073]
(Eighth embodiment)
Next, a method for manufacturing a power MOSFET according to the seventh embodiment of the present invention will be described.
[0074]
FIG. 8 is a schematic process diagram showing the manufacturing process of this MOSFET.
[0075]
First, as shown in FIG. 8A, an n − type drift layer 1 ′ is epitaxially grown on an n + type substrate 2 as a drain layer.
[0076]
Subsequently, as shown in FIG. 8B, phosphorus as an n-type impurity is ion-implanted into the element formation region portion through the mask on the n − -type drift layer 1 ′.
[0077]
After the ion implantation, as shown in FIG. 8C, an n − type drift layer 1 ′ is further epitaxially grown on the ion implanted n − type drift layer 1 ′. In this epitaxial growth step, phosphorus is re-diffused and the n − type drift layer 1 ′ portion on the element formation region is converted into the n type drift layer 1 having a predetermined impurity concentration.
[0078]
Subsequently, as shown in FIG. 8D, boron as a p-type impurity and phosphorus as an n-type impurity are sequentially ion-implanted into the element formation region through the mask on the n − -type drift layer 1 ′.
[0079]
After the ion implantation, as shown in FIG. 8E, an n − type drift layer 1 ′ is further epitaxially grown on the ion implanted n − type drift layer 1 ′. In this epitaxial growth step, boron and phosphorus are re-diffused to form the lowermost p + type buried layer 9c, and the n − type drift layer 1 portion between the p + type buried layers 9c and 9c is converted to the n type drift layer 1 Is done.
[0080]
Next, as shown in FIG. 8F, phosphorus is ion-implanted onto the element formation region of the n − type drift layer 1 ′.
[0081]
Subsequently, as shown in FIG. 8G, the n − type drift layer 1 is further epitaxially grown on the ion-implanted n − type drift layer 1 ′. In this epitaxial growth step, phosphorus is re-diffused, and the n − type drift layer 1 ′ portion on the p + type buried layer 9 c and the n type drift layer 1 portion is converted into the n type drift layer 1.
[0082]
Next, as shown in FIG. 8H, boron and phosphorus are sequentially ion-implanted into the element formation region through the mask on the n − type drift layer 1 ′.
[0083]
After the ion implantation, as shown in FIG. 8 (i), an n − type drift layer 1 ′ is further epitaxially grown on the ion implanted n − type drift layer 1 ′, and an intermediate layer p + type buried layer 9b and An n-type drift layer 1 is formed between the buried layers 9b.
[0084]
Similarly, by repeating the steps of FIGS. 8 (f) to 8 (i), as shown in FIG. 8 (j), three p + type buried layers 9a, 9b, 9c and An n-type drift layer 1 is formed between the layers, and an n− type drift layer 1 ′ with the uppermost layer epitaxially grown is formed.
[0085]
Next, as shown in FIG. 8K, phosphorus is ion-implanted into the element formation region on the n − type drift layer 1 ′.
[0086]
After the ion implantation, as shown in FIG. 8L, an n − type drift layer 1 ′ is further epitaxially grown on the ion implanted n − type drift layer 1 ′. In this epitaxial growth step, phosphorus is re-diffused to convert the n − type drift layer 1 ′ portion in the element formation region into the n type drift layer 1.
[0087]
Thereafter, as shown in FIG. 7, a p-type base layer 4 is selectively diffused on the surface of the n-type drift layer 1 in the element formation region, and then an n + -type source layer is formed on the surface of the p-type base layer 4. 5 is formed selectively.
[0088]
Finally, after the gate oxide film 6 is formed, the gate electrode 7, the source electrode 8, and the drain electrode 2 are formed, thereby completing the MOSFET.
[0089]
(Ninth embodiment)
Next, an example relating to charging of the p-type buried layer at turn-on in the power MOSFET will be described as a ninth embodiment.
[0090]
FIG. 9A is a circuit diagram for explaining a power MOSFET driving method according to the ninth embodiment of the present invention, and FIG. 9B is a diagram showing the relationship between the gate current and time. The power MOSFET in this embodiment is, for example, the power MOSFET of the first embodiment shown in FIG.
[0091]
As shown in FIG. 9A, in the MOSFET drive circuit according to the ninth embodiment, the first gate electrode G1 of the MOSFET is directly connected to the first input terminal 91 to which the input signal Vin1 is applied. ing. The second gate electrode G2 is applied with the input signal Vin2 via the gate input circuit 95 in which the capacitor C and the resistor rg2 are connected in parallel and the resistor rg1 directly connected to the gate input circuit 95. The input terminal 92 is connected. The drain electrode D is connected to the Vdd power supply terminal 93 via the load resistor RL, and the source electrode S is connected to the ground (Vgnd) power supply terminal 94.
[0092]
Next, the turn-on operation by this drive circuit will be described.
[0093]
First, as shown in FIG. 9B, when an input signal Vin1 having an amplitude of 15V is applied to the first input terminal 91 and an input signal Vin2 having an amplitude of 5V is applied to the second input terminal 92, the first gate is applied. A channel is formed in the p-type base layer 4 immediately below the electrode 7, electrons are injected from the n + -type source layer 5 into the n − -type drift layer 1, and depletion in the n − -type drift layer 1 is eliminated. At the same time, since the displacement current flows through the capacitor C at the moment when the input signal Vin2 is input to the second input terminal 92, a larger gate current Ig2 flows to the second gate electrode G2, and the p + type buried layer More holes are supplied to 9a, 9b, and 9c, and depletion of the p + type buried layers 9a, 9b, and 9c is quickly eliminated. As a result, it is possible to quickly turn on. The gate current Ig2 flowing through the second gate electrode G2 shows a very small value after the capacitor C is charged.
[0094]
According to the drive circuit described above, in a MOSFET that operates purely in the unipolar mode, holes are not supplied to the p + type buried layer, and the depletion of the p + type buried layer cannot be eliminated, and the turn-on time becomes long. However, the MOSFET according to the embodiment of the present invention can be operated in the bipolar mode by flowing a large gate current at the time of turn-on, and holes can be supplied to the p + type buried layer. Therefore, faster turn-on can be realized.
[0095]
Although the present invention has been described with reference to the first to ninth embodiments, the present invention is not limited to the first to ninth embodiments.
[0096]
For example, in the first to eighth embodiments, the p + type buried layer is described as three layers, but the same effect can be obtained if the structure has one or more p + type buried layers.
[0097]
The plurality of p + type buried layers in each layer are formed in independent stripes, but may be connected to each other at the end of the stripe.
[0098]
Further, the p + type buried layer of each layer is not limited to a stripe shape, and may be formed in a mesh shape or a dot shape.
[0099]
The p-type base layer and the n + -type source layer are formed in a stripe shape, but may be formed in a dot shape.
[0100]
Further, although a MOSFET using silicon (Si) as a semiconductor has been described, a compound semiconductor such as silicon carbide (SiC) can be used as the semiconductor.
[0101]
In the first embodiment, the p + type carrier layer is arranged only on the side of the p + type carrier layer on one side of the plurality of p type base layers, but is arranged on the side of both p + type carrier layers. It may be formed in an annular structure so as to surround a plurality of p-type base layers.
[0102]
In the second and third embodiments, the p + type carrier layer is formed in a stripe shape, but may be formed in a ring shape, a lattice shape, or a dot shape.
[0103]
In the second and third embodiments, the p + type carrier layer is connected to the drain electrode, but may be electrically separated from the drain electrode and applied with a potential independent of the drain electrode.
[0104]
In the second embodiment, the p + type carrier layer and the adjacent n + type drain layer are formed to have the same surface area. However, the p + type carrier layer may be formed to have a large surface area.
[0105]
In the third embodiment, the surface area of the p + type carrier layer is larger than the surface area of the n + type drain layer adjacent to the p + type carrier layer, but the surface area of the p + type carrier layer and the n + type drain layer is formed to the same area. Also good.
[0106]
In the ninth embodiment, the first and second input terminals are provided separately. However, if the first and second input terminals are made common and the same input signal is applied, the drive circuit is provided. Easy to do.
[0107]
In the first to ninth embodiments, the planar type power MOSFET is exemplified, but the present invention is also applicable to a trench type power MOSFET.
[0108]
Further, although only a MOSFET having a buried layer with a floating potential has been described, the structure and driving method of the present invention can be applied to any element having a layer with a floating potential.
[0109]
【The invention's effect】
As described above, according to the present invention, a power semiconductor device capable of high-speed operation with a short turn-on time while maintaining a high breakdown voltage, and a low switching loss, and the turn-on time of the power semiconductor device can be reduced. It is possible to provide a driving method effective for shortening.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a fifth embodiment of the present invention.
FIG. 6 is a schematic process diagram showing a manufacturing process of a power MOSFET according to a sixth embodiment of the present invention.
FIG. 7 is a sectional view schematically showing a configuration of a power MOSFET according to a seventh embodiment of the present invention.
FIG. 8 is a schematic process diagram showing a manufacturing process of a power MOSFET according to an eighth embodiment of the present invention.
FIG. 9A is a circuit diagram showing a drive circuit for a power MOSFET according to a ninth embodiment of the present invention, and FIG. 9B is a diagram showing the relationship between input current and time.
FIG. 10 is a cross-sectional view schematically showing a configuration of a conventional power MOSFET.
[Explanation of symbols]
1, 111... N-type drift layer (first semiconductor layer),
2, 112... N + type drain layer (high concentration semiconductor layer),
3, 113 ... drain electrode D (first main electrode),
4, 114 ... first p-type base layer (second semiconductor layer),
5, 115... N + type source layer (third semiconductor layer),
6, 116 ... Si oxide film (gate insulating film),
7, 117 ... 1st gate electrode G1 (1st control electrode),
8, 118 ... source electrode S (second main electrode),
9a, 9b, 9c, 119a, 119b, 119c ... p + buried layer,
10 ... p + type carrier injection layer (fourth semiconductor layer),
11: Second gate electrode (second control electrode)
20, 30... P + type carrier injection layer (fifth semiconductor layer),
44. Second p-type base layer (sixth semiconductor layer),
45... N + type source layer (seventh semiconductor layer),
46: Si oxide film (gate insulating film),
47 ... Source electrode (floating electrode),
50a, 50b, 50c ... p-type connection layer,
91: First input terminal,
92 ... second input terminal,
93 ... Vdd power supply terminal,
94: Ground (Vgnd) power supply terminal,
95: Gate input circuit,
rg1, rg2 ... resistance,
RL: Load resistance,
C ... Capacitor

Claims (7)

第１導電型の第１の半導体層と、
前記第１の半導体層に一方の表面に電気的に接続された第１の主電極と、
前記第１の半導体層の他方の表面に選択的に形成された第２導電型の第２の半導体層と、
前記第２の半導体層の表面に選択的に形成された第１導電型の第３の半導体層と、
前記第２の半導体層と前記第３の半導体層とに電気的に接続された第２の主電極と、
前記第１の半導体層と前記第２の半導体層と前記第３の半導体層の表面上に絶縁膜を介して形成された第１の制御電極と、
前記第１の半導体層中であって、前記第２の半導体層と前記第１の主電極との間に選択的に埋込まれた少なくとも１つ以上の電位の浮いた第２導電型埋込み層と、
前記第１の半導体層の他方の表面に選択的に形成された第２導電型の第５の半導体層と、
前記第５の半導体層に電気的に接続された第２の制御電極と、
前記第１の半導体層の一方の表面と前記第１の主電極との間に、前記第１の半導体層よりも高不純物濃度をもつ第１導電型の高濃度半導体層が形成され、前記第５の半導体層は、前記高濃度半導体層に選択的に形成され、且つ前記第１の主電極側の一端が前記高濃度半導体層と同一平面をなし、他端が前記高濃度半導体層を貫通して前記第１の半導体層中に達する形状に形成されてなることを特徴とする電力用半導体装置。A first semiconductor layer of a first conductivity type;
A first main electrode electrically connected to the first semiconductor layer on one surface;
A second semiconductor layer of a second conductivity type selectively formed on the other surface of the first semiconductor layer;
A third semiconductor layer of a first conductivity type selectively formed on the surface of the second semiconductor layer;
A second main electrode electrically connected to the second semiconductor layer and the third semiconductor layer;
A first control electrode formed on the surfaces of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via an insulating film;
In the first semiconductor layer, at least one potential-filled second conductivity type buried layer selectively buried between the second semiconductor layer and the first main electrode. When,
A second conductivity type fifth semiconductor layer selectively formed on the other surface of the first semiconductor layer;
A second control electrode electrically connected to the fifth semiconductor layer;
A first conductivity type high concentration semiconductor layer having a higher impurity concentration than the first semiconductor layer is formed between one surface of the first semiconductor layer and the first main electrode, and The semiconductor layer 5 is selectively formed on the high-concentration semiconductor layer, and one end on the first main electrode side is flush with the high-concentration semiconductor layer, and the other end penetrates the high-concentration semiconductor layer. Then , the power semiconductor device is formed in a shape reaching the first semiconductor layer . 前記第１の主電極と前記第２の制御電極とが電気的に共通接続されてなることを特徴とする請求項１に記載の電力用半導体装置。The power semiconductor device according to claim 1 , wherein the first main electrode and the second control electrode are electrically connected in common. 前記第１の主電極と前記第２の制御電極とが電気的に独立に形成されてなることを特徴とする請求項１に記載の電力用半導体装置。The power semiconductor device according to claim 1 , wherein the first main electrode and the second control electrode are electrically formed independently. 前記第５の半導体層は、前記第１の半導体層の一方の表面、または前記第１の主電極側の前記高濃度半導体層表面において、前記第５の半導体層の表面積とこの層に隣接する前記１の半導体層部分部、または隣接する前記高濃度半導体層部分の表面積とが同一面積
であることを特徴とする請求項１に記載の電力用半導体装置。The fifth semiconductor layer is adjacent to the surface area of the fifth semiconductor layer and this layer on one surface of the first semiconductor layer or on the surface of the high-concentration semiconductor layer on the first main electrode side. 2. The power semiconductor device according to claim 1 , wherein a surface area of the one semiconductor layer portion or the adjacent high-concentration semiconductor layer portion is the same area. 前記第５の半導体層は、前記第１の半導体層の一方の表面、または前記第１の主電極側の前記高濃度半導体層表面において、前記第５の半導体層の表面積がこの層に隣接する前記１の半導体層部分部、または隣接する前記高濃度半導体層部分の表面積より広面積であることを特徴とする請求項１に記載の電力用半導体装置。In the fifth semiconductor layer, the surface area of the fifth semiconductor layer is adjacent to one surface of the first semiconductor layer or the surface of the high-concentration semiconductor layer on the first main electrode side. The power semiconductor device according to claim 1 , wherein the power semiconductor device has a larger area than a surface area of the one semiconductor layer portion or the adjacent high-concentration semiconductor layer portion. 第1導電型の第1の半導体層と、
前記第１の半導体層の一方の表面に電気的に接続された第１の主電極と、
前記第1の半導体層の他方の表面に選択的に形成された第２導電型の第２の半導体層と、
前記第２の半導体表面に選択的に形成された第1導電型の第3の半導体層と、
前記第２の半導体層と前記第３の半導体層の表面に電気的に接続された第２の主電極と、
前記第１の半導体層と前記第2の半導体層と前記３の半導体層上に絶縁膜を介して形成された第1の制御電極と、
前記第1の半導体層の他方の表面に前記第2の半導体層と離間して選択的に形成された第２導電型の第６の半導体層と、
前記第６の半導体層の表面に選択的に形成された第1導電型の第７の半導体層と、
前記第６の半導体層と前記第７の半導体層とに電気的に接続された電位の浮遊したフローティング電極と、
前記第1の半導体層と前記第６の半導体層と前記第７の半導体層上に絶縁膜を介して形成された第２の制御電極と、
前記第1の半導体層中に選択的に埋込み形成された少なくとも１つ以上の電位の浮いた第2導電型埋め込層とを有することを特徴とする電力用半導体装置。A first semiconductor layer of a first conductivity type;
A first main electrode electrically connected to one surface of the first semiconductor layer;
A second semiconductor layer of a second conductivity type selectively formed on the other surface of the first semiconductor layer;
A third semiconductor layer of a first conductivity type selectively formed on the second semiconductor surface;
A second main electrode electrically connected to surfaces of the second semiconductor layer and the third semiconductor layer;
A first control electrode formed on the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer via an insulating film;
A sixth semiconductor layer of a second conductivity type selectively formed on the other surface of the first semiconductor layer so as to be separated from the second semiconductor layer;
A seventh semiconductor layer of a first conductivity type selectively formed on the surface of the sixth semiconductor layer;
A floating electrode having a floating potential electrically connected to the sixth semiconductor layer and the seventh semiconductor layer;
A second control electrode formed on the first semiconductor layer, the sixth semiconductor layer, and the seventh semiconductor layer via an insulating film;
A power semiconductor device comprising: at least one second-conductivity-type buried layer with a floating potential selectively embedded in the first semiconductor layer. 前記第１の半導体層の素子形成領域の周辺部における不純物濃度が、素子形成領域の不純物濃度より低濃度に形成れていることを特徴とする請求項６に記載の電力用半導体装置。The power semiconductor device according to claim 6 , wherein an impurity concentration in a peripheral portion of the element formation region of the first semiconductor layer is formed to be lower than an impurity concentration of the element formation region.
JP2000130648A 2000-04-28 2000-04-28 Power semiconductor device and driving method thereof Expired - Fee Related JP4746169B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000130648A JP4746169B2 (en) 2000-04-28 2000-04-28 Power semiconductor device and driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000130648A JP4746169B2 (en) 2000-04-28 2000-04-28 Power semiconductor device and driving method thereof

Publications (2)

Publication Number Publication Date
JP2001313393A JP2001313393A (en) 2001-11-09
JP4746169B2 true JP4746169B2 (en) 2011-08-10

Family

ID=18639700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000130648A Expired - Fee Related JP4746169B2 (en) 2000-04-28 2000-04-28 Power semiconductor device and driving method thereof

Country Status (1)

Country Link
JP (1) JP4746169B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108780806A (en) * 2016-03-22 2018-11-09 通用电气公司 Superjunction power semiconductor arrangement with fast switching capability
CN109659359A (en) * 2013-07-11 2019-04-19 英飞凌科技股份有限公司 Bipolar transistor and the method for manufacturing bipolar transistor

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006332199A (en) * 2005-05-24 2006-12-07 Shindengen Electric Mfg Co Ltd SiC SEMICONDUCTOR DEVICE
JP2008108962A (en) 2006-10-26 2008-05-08 Toshiba Corp Semiconductor device
JP6338134B2 (en) * 2012-03-30 2018-06-06 富士電機株式会社 Silicon carbide vertical MOSFET and manufacturing method thereof
CN103390545A (en) * 2012-05-08 2013-11-13 上海华虹Nec电子有限公司 Method for increasing drain-source breakdown voltage of trench NMOS and structure of trench NMOS
KR101437275B1 (en) 2013-03-25 2014-10-27 고려대학교 산학협력단 Semiconductor device having a multi floating island
US10468510B2 (en) 2015-07-16 2019-11-05 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of the same
CN106024863A (en) * 2016-06-27 2016-10-12 电子科技大学 High-voltage power device terminal structure
TWI699887B (en) * 2017-04-20 2020-07-21 聚積科技股份有限公司 Power semiconductor device with segmented concentration
JP7052330B2 (en) 2017-12-13 2022-04-12 富士電機株式会社 Insulated gate type semiconductor device and its manufacturing method
US11056586B2 (en) * 2018-09-28 2021-07-06 General Electric Company Techniques for fabricating charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0267766A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Bipolar-type semiconductor switching device
JPH09191109A (en) * 1995-11-06 1997-07-22 Toshiba Corp Semiconductor device
JPH10256550A (en) * 1997-01-09 1998-09-25 Toshiba Corp Semiconductor device
JP2000101082A (en) * 1998-09-02 2000-04-07 Siemens Ag Edge structure and drift region for semiconductor constituent element and manufacture thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414263A (en) * 1990-05-07 1992-01-20 Fuji Electric Co Ltd Insulated gate type bipolar transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0267766A (en) * 1988-09-01 1990-03-07 Mitsubishi Electric Corp Bipolar-type semiconductor switching device
JPH09191109A (en) * 1995-11-06 1997-07-22 Toshiba Corp Semiconductor device
JPH10256550A (en) * 1997-01-09 1998-09-25 Toshiba Corp Semiconductor device
JP2000101082A (en) * 1998-09-02 2000-04-07 Siemens Ag Edge structure and drift region for semiconductor constituent element and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109659359A (en) * 2013-07-11 2019-04-19 英飞凌科技股份有限公司 Bipolar transistor and the method for manufacturing bipolar transistor
CN108780806A (en) * 2016-03-22 2018-11-09 通用电气公司 Superjunction power semiconductor arrangement with fast switching capability

Also Published As

Publication number Publication date
JP2001313393A (en) 2001-11-09

Similar Documents

Publication Publication Date Title
US9852910B2 (en) Vertical power transistor with dual buffer regions
JP4857566B2 (en) Insulated gate type semiconductor device and manufacturing method thereof
EP0854518A1 (en) Trench insulated gate bipolar transistor
US20140231865A1 (en) Insulated gate semiconductor device and method for manufacturing the same
CN105122458A (en) Semiconductor device and manufacturing method therefor
CN111201611B (en) Power switching device with high DV/DT capacity and method for manufacturing such a device
JP4746169B2 (en) Power semiconductor device and driving method thereof
US9806152B2 (en) Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base
US8067797B2 (en) Variable threshold trench IGBT with offset emitter contacts
JP2003303965A (en) Semiconductor element and its fabricating method
US11699744B2 (en) Semiconductor device and semiconductor apparatus
JPH0851197A (en) Mos control thyristor having electric current saturation property
US9806181B2 (en) Insulated gate power device using a MOSFET for turning off
WO1999056323A1 (en) Semiconductor device and process for manufacturing the same
JP4177229B2 (en) Semiconductor device and manufacturing method thereof
US10600898B2 (en) Vertical bidirectional insulated gate turn-off device
US11114552B2 (en) Insulated gate turn-off device with designated breakdown areas between gate trenches
JP2001274414A (en) Power semiconductor element and drive method thereof
US11011629B2 (en) Power semiconductor switch with improved controllability
US11114553B2 (en) Lateral insulated gate turn-off device with induced emitter
TWI607563B (en) With a thin bottom emitter layer and in the trenches in the shielded area and the termination ring Incoming dopant vertical power transistors
JP2000077657A (en) Insulated gate bipolar transistor and power converter using the same

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050414

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20050606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070125

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110126

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110128

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110329

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110419

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110513

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140520

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140520

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees