TWI607563B - With a thin bottom emitter layer and in the trenches in the shielded area and the termination ring Incoming dopant vertical power transistors - Google Patents

With a thin bottom emitter layer and in the trenches in the shielded area and the termination ring Incoming dopant vertical power transistors Download PDF

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TWI607563B
TWI607563B TW106113414A TW106113414A TWI607563B TW I607563 B TWI607563 B TW I607563B TW 106113414 A TW106113414 A TW 106113414A TW 106113414 A TW106113414 A TW 106113414A TW I607563 B TWI607563 B TW I607563B
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region
substrate
conductivity type
top surface
layer
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TW106113414A
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TW201839991A (en
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Mohamed N Darwish
Jun Zeng
Shih Tzung Su
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Maxpower Semiconductor Inc
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Description

Has a thin bottom emitter layer and is implanted in the trench in the shielded area and the termination ring Vertical power transistor

The present invention relates to isolation gate devices, such as insulated gate bipolar transistors (IGBTs), and more particularly to device structures and fabrication techniques for improving efficiency and increasing breakdown voltage.

Although the present invention is applicable to a variety of vertical isolation gate devices, IGBTs will be used as examples.

One type of common vertical IGBT contains a vertical pnp bipolar transistor (formed by a number of cells in parallel) driven by a MOSFET that initiates the injection of the carrier, which then fully turns on the pnp transistor. At high current levels, the forward voltage drop (Vce-sat) in a vertical IGBT is typically lower than a vertical MOSFET. In high power IGBTs that handle high currents and high voltages (eg, for industrial motor control, induction heating, etc.), the n-type base requires relatively light doping to create a broad depletion layer to withstand in the off state The high voltage. This thick and lightly doped n-type base layer reduces the bottleneck of the Vcs-sat. When the transistor is switched from on to off, it is important to quickly remove the hole from the n-type base to quickly stop the current flow.

A thinner, higher concentration doped p-type emitter (which may be the bottom semiconductor layer of the IGBT) is intended to increase hole injection efficiency and reduce the Vce-sat of the IGBT. However, there are trade-offs between increasing the injection efficiency and the cut-off speed of the IGBT. The thin p-type emitter layer is usually formed after the front end processes are completed (ie, after the formation of the transistor layers), wherein the bottom surface of the wafer (germanium substrate) is mechanically polished and connected The p-type emitter dopant implanted in the bottom surface is followed by an annealing step. Laser annealing is required because the resulting heat does not cause any further diffusion of such positive dopants. This annealing step adds complexity to the process and requires specialized equipment.

The device required has a high breakdown voltage but a low Vce-sat. A crash in the region of the active cells (in the off state) can result in a permanent device failure, so it is desirable that the device provide a crash path away from the fine active cell array. The effective treatment of high voltage without damage is generally referred to as robustness.

The area near the edges of the die is particularly prone to collapse due to crowding of the electric field and should not be the bottleneck of the overall breakdown voltage of the device. The termination structure is typically used for high power devices around the edges of the die.

Improvements in all of the above mentioned areas are required to produce a more robust and efficient IGBT.

The present disclosure illustrates an IGBT structure and method of fabrication that reduces forward voltage drop (Vce-sat), improves turn-off time, and improves the robustness of the active cell array. These teachings are applicable to a variety of other types of power devices.

In a specific embodiment, a relatively shallow and narrow trench gate is formed in the active cell array region to form a MOSFET or IGBT, and a wider deep trench filled with the gate material surrounds the active region Formed in the shield area. Deep floating p-regions are formed beneath the deep trenches (by implantation in the trenches) to create an equipotential ring around the active region to improve the breakdown voltage of the device. Short-circuiting the shallower p-region between the deep trenches in the shield region to the top source metal to quickly remove the hole from the n-type base after the IGBT gate has been turned off Accelerate the cutoff of current flow. The deep floating p-region region is designed to shield the shallow p-region from normal shutdown and IGBT cutoff modes to avoid collapse.

If there are multiple segments of the cell array, there may be a shielded area around each cell array. Termination structures around the edges of the die may surround the cell array and the shield region.

The shields are designed for breakdown voltages having a breakdown voltage that is lower than the active region and the edge termination structure of the IGBT device. The shield is very strong so there is typically no permanent damage to the device in the event of a crash, wherein the shield distinguishes the flow current from the active region.

In addition, a "hole bypass p+ region" adjacent to the deep trench (in the shield region) is safely supplied to the drain hole in the n-type drift region away from the shallow trench MOSFET or IGBT Parasitic npn bipolar transistors to prevent triggering of the 4-layer npnp parasitic thyristor inherent in such device structures. The MOSFET or IGBT device formed in accordance with the present invention will have a enhanced safe operating region due to the formation of such "hole bypass p+ regions" and deep p-region results below the deep trenches in the shield region. Area, SOA), which is defined as such voltage and current conditions that the device can be expected to operate without damage.

In another embodiment, after the p-type dopants are implanted in the deep trenches in the shield region, the trenches are filled with a dielectric. A metal ring is formed on the top end surface above the dielectric body and serves as a floating field plate. The dielectric filled trenches serve as a vertical gap layer between the metal rings and the deep p-regions for controlling the shape of the depletion region (which controls the breakdown voltage). The difference in vertical depth between the deep p-intersection and its associated floating metal field plate sets the voltage in the associated metal ring.

In another embodiment of the IGBT structure, a segmented highly doped n+ buffer layer (forming a strip or dot) is formed over the conventional n-buffer layer. The n+ segmented buffer layer portion increases the pass voltage to increase the breakdown voltage, but does not significantly reduce the bottom due to the gaps in the n+ segmented buffer layer The hole injection efficiency of the p-type emitter. The n+ segmentation buffer layer also reduces Vce-sat. This also allows the overlying n-type drift region to be thinner. Thus, the double buffer layers cause Vce-sat to decrease and the breakdown voltage to increase.

In another embodiment, the IGBT structure is formed with a highly doped and thin p-type emitter, eliminating the need for laser annealing. A thinner p-type emitter (the bottom semiconductor layer of the IGBT) increases hole injection efficiency and reduces the Vce-sat of the IGBT. A method of forming a thin highly doped p-type emitter includes implanting a unit (e.g., a dot) or a strip region of a p-type dopant into a top surface of a p-type germanium substrate using a mask to form a plurality of p+ regions. Then, the various epitaxial layers are grown over the top surface and doped regions are formed to actually complete the front side processing of the IGBT. The various heating steps for the front side treatment provide some drive-in and start-up of the p-type dots/strips, which may merge the dots/strips to some extent, but still at the top of the growth substrate High and low p-dopant concentrations are caused in the surface region. After the front side processing, the surface of the tantalum wafer is mechanically polished to about 80-90% of its final thickness, followed by wet etching to expose the p-type dots on the bottom surface. The highly doped p+ regions serve as an etch stop layer for the wet etch (optically detected by color). The bottom surface does not have to be further heated by the laser to spread the p-type points, thereby reducing processing requirements. Since the wet etch rate is somewhat dependent on the dopant concentration, the resulting thinned substrate has a roughened bottom surface that provides excellent electrical contact to the bottom electrode. The metal electrode layer is then deposited on the back surface that is in direct contact with the exposed p-type dots. The metal layer may be annealed to improve contact resistance. The resulting p-type emitter layer is highly doped (referred to as p+) and is extremely thin, which results in a more efficient IGBT.

A termination structure around the edges of the die is illustrated, including a trench and a deep p-region below the trench, which is formed by implantation through the trenches. In some embodiments, the channels are filled with a conductive material to provide an equipotential ring. In other embodiments, the trenches are filled with a dielectric. In a specific embodiment in which the trenches are filled with a dielectric body, the iso-p-regions are connected for use as The top metal ring of the floating field plate used to extend the electric field. The dopant concentrations of the various deep p-regions can be varied by varying the spacing between the trenches such that the dopant concentration decreases toward the edge of the die to optimize the breakdown voltage.

Other specific embodiments are described.

10,17‧‧‧Insulated gate bipolar transistor (IGBT)

12‧‧‧ outer edge; grain edge

14‧‧‧ unit; cell array

15‧‧‧High voltage termination area

16‧‧‧Shielded area

18‧‧‧ strips; narrow strips

19‧‧‧ load

20‧‧‧Top source metal; source metal; aluminum source metal; second metal electrode; second electrode

22‧‧‧Bottom emitter metal; emitter metal; back metal; metal layer; bottom metal layer; first metal electrode; first electrode

24‧‧‧channel-type gate; gate; shallow gate

26‧‧‧thin dielectric

28‧‧‧p-body; p-body area; first conductivity type

29‧‧‧n+ source region; second conductivity type

30‧‧‧p+ body contact area; p+ contact area

32‧‧‧Ti/W metal connectors

34‧‧‧ dielectric layer

36‧‧‧n-base layer; n-type base layer; first semiconductor material

42‧‧‧ bottom p-type emitter layer; emitter layer; p-type emitter layer; second semiconductor material; substrate

44‧‧‧Ditch; deep channel; concentric channel

46‧‧‧gate material; conductive material

47‧‧‧ dielectric

48‧‧‧Metal joints

50‧‧‧ gate metal

56‧‧‧deep p-zone; p-zone; deep zone

57‧‧‧lighter p-zone; p-zone; shallower p-zone; shallower zone

58, 62‧‧‧p+ contact area

60‧‧‧shallow p-zone; p-zone

66, 68, 70‧‧‧ arrows

74‧‧‧n type buffer layer; buffer layer; n-buffer layer; first buffer layer

76‧‧‧n+ points; n+ strips; n+ points/strips; second buffer layer

80‧‧‧ starting substrate

82‧‧‧ more highly doped n-layer; layer; n-layer

84‧‧‧ more highly doped n-layer; layer; n-layer

86‧‧‧p-trap

88‧‧‧SiO 2 /Si 3 N 4 /SiO 2 hard mask layer; mask layer

90‧‧‧deep trench; deep trench

92‧‧‧ shallower trench; shallow trench

93‧‧‧Bon-phosphorus glass (BPSG) mask; mask

94‧‧‧Oxide/nitride passivation layer

98‧‧‧Repetitive active areas

100‧‧‧Shielded area

102‧‧‧Deep channel

106‧‧‧p type starting substrate; substrate; p-substrate

108‧‧‧Small strips or dots; points; p-type implant points; p+ points

110‧‧‧High concentration doping p+ center; p+ center

112‧‧‧ Less doped p shell

114‧‧‧Deep p+ center; wider p+ center

116‧‧‧p shell; p-shell

118‧‧‧ epitaxial layer

119‧‧ ‧

120‧‧‧Mechanically polished

122‧‧‧Slow anisotropic etchant

124‧‧‧n+ points

130‧‧‧deep p-zone; deep zone

132‧‧‧Metal joints

134‧‧‧p-type zone; p-zone

136‧‧‧conductive ring; metal ring

136A-136D‧‧‧Floating metal ring

136B‧‧‧ Ring

138, 140‧‧‧ channel stop area

142‧‧‧n+ district

146‧‧‧dielectric material; dielectric

148‧‧‧Ditch channel stop zone

150‧‧‧Metal floating field plate; metal field plate

154‧‧‧ trench; dielectric filled trench; concentric trench

156‧‧‧p-zone; merged p-zone

158‧‧‧n-zone

159, 162, 168‧‧‧p-zone

160‧‧‧External field board

170‧‧‧Chamfered edge; beveled sawing; etching beveled edge

172‧‧‧ Passivation layer (oxide); oxide/nitride layer

D1-D4‧‧‧ Division

1A is a plan view of a die having a shield region along the periphery of the center cell array (the active region) and a high voltage termination region along an edge of a die forming an IGBT.

[Fig. 1B] is a plan view of an IGBT die in which each active cell is surrounded by a deep floating p-shield region and a high voltage termination region is along the edge of the die.

[Fig. 2] is a cross-sectional view showing an example of an active cell array and a deep floating p-shield region surrounding the active cell array. The active cell array shown may be a short version of a larger cell array at the center of the die (as shown in Figure 1A) or a strip of cells (as shown in Figure 1B). The p-type dopants for the deep p-regions in the shielded region are implanted through the deep and wide trenches. The high voltage termination region along the edge of the die is not shown in Figure 2, but is shown in other figures.

[Figs. 3-10] Illustrate the manufacturing steps in the formation of the IGBT of Fig. 2.

[Fig. 11] A variation of the IGBT of Fig. 2 is exemplified in which there is no shallow p-region between the deep trenches in the shield region for removing holes from the n-base layer after the turn-off.

12-14 illustrate the steps for forming the highly doped and very thin bottom p-type emitter layer.

[Fig. 15 and Fig. 16] exemplifying another embodiment of the embodiment for forming the highly doped and very thin bottom p+ emitter layer, wherein an additional n+ region is formed to be provided through the IGBT when the voltage polarities are reversed Reverse conduction.

[FIG. 17-19] exemplifying an alternative embodiment of a high voltage termination region along the edge of the die, wherein the gate material fills a wide and deep trench surrounding the cell array, and wherein the deep p-region is Below each trench. These various alternatives use different numbers of masks, which can affect manufacturing costs.

[Fig. 20-26] An alternative embodiment exemplifying a termination region in which a dielectric material fills a wide and deep trench surrounding the cell array, and wherein a deep p-region is below each trench. These various alternatives use different numbers of masks, which can affect manufacturing costs.

[FIG. 27-29] exemplifying the spacing of the deep trenches in the termination region to achieve a cone-embedded p-dopant concentration of the iso-p-region to further improve the breakdown voltage. The p-dopants are implanted through the channels.

[FIG. 30] The edge of the die is slanted to improve the breakdown voltage for a very high voltage IGBT (eg, >1700V).

Equivalent or similar elements in the various figures are identified by the same number.

Although vertical pnp IGBT devices are shown in these figures, npn IGBTs may be fabricated by reversing the polarities of the various regions/layers. Such teachings of this disclosure can be readily applied to vertical MOSFETs by replacing the p-type substrate with an n-type substrate.

1A is a top plan view of an IGBT 10 in accordance with an embodiment of the present invention. The germanium grain has an outer edge 12. The IGBT 10 has a central portion containing an array of cells 14 that are connected in parallel. As an overview, each vertical cell region includes one of the top p-type collectors of the pnp transistors; a p-body for inverting the MOSFET portion to initiate turn-on; a top n+ source region; An n-base layer (including an n-type buffer layer); a bottom p-type emitter layer; and a trench gate adjacent to the n+ source region and the p-body. A sufficiently high gate voltage produces an n-channel in the p-body to initiate electron flow from the n+ source In the p-type emitter of the vertical pnp transistor. As a result, a hole from the p-type emitter is injected into the n-base layer. Injecting holes from the p-type emitter and electrons from the n+ source region of the MOSFET will cause electrons and holes to be stored inside the thick n-base region, which is referred to as the base conduction modulation effect. Due to the base conduction modulation effect, the Vce-sat of the IGBT will be reduced. However, if too many pairs of electrons and holes are stored inside the n-base layer, the IGBT turn-off speed becomes very slow, and the IGBT dissipates too much power so that it cannot be used for many applications even if Vce-sat is low.

When the IGBT is turned off, there will typically be a high voltage between the top source metal and the bottom emitter metal. A large depletion region is formed in the thick n-base layer (drift region) to withstand the voltage. By design, the shield unit (shield region 16) surrounding the active cells has the lowest breakdown voltage, so it clamps the overall breakdown voltage of the IGBT. The shield region 16 around the interior of the high voltage termination region 15 (along the die edge 12) provides a safe path for the holes in the n-base layer to discharge during the turn-off period to accelerate the stop current flow. The breakdown voltage of the shielded region 16 is made slightly less than the collapse voltage of the active region to avoid damaging the active region. Therefore, the IGBT is more robust. More details are provided below with reference to FIG. 2.

1B is a top plan view of another embodiment of an IGBT 17 in which the cells are formed in a strip 18 with a shield region 16 surrounding each strip 18. The high voltage termination region 15 along the edge of the die is different from the shield region 16 between the stripes 18. Imagine other configurations.

Deep and shallow P-zone in the shielded area surrounding the active unit

2 is a cross-sectional view of IGBT 10 or 17 showing a shorthand array of cells 14 (in the case of FIG. 1A) or a narrow strip 18 of cells (in the case of FIG. 1B). The shield region 16 surrounds the array of cells 14 and is continuous around the array of cells 14. The shielding area 16 around the cell group depends on the shape of the array of cells 14, possibly forming a square ring (as shown in Figure 1A), a rectangular ring (as shown in Figure 1B), or other shapes, such as hexagons, circles, etc. .

In a typical application, a load 19 (eg, a motor) has one terminal coupled to ground and the other terminal connected to the top source metal 20 of IGBT 10. A positive voltage (e.g., 500V) is connected to the bottom emitter metal 22. When the IGBT 10 is turned on, approximately 500 V is connected across the load 19 at both ends. The IGBT 10 is typically a package die.

To turn on the IGBT 10, a sufficient potential is applied across the source metal 20 and the emitter metal 22, with a sufficiently positive gate-source voltage applied to the trench gate 24 in the cell 14. Gate 24 may be doped with polysilicon. The gate 24 is isolated by a thin dielectric body 26. The p-body 28 and the upper n+ source region 29 are between adjacent gates 24. The source metal 20 is connected to the n+ source region 29 and the p+ body contact region 30 by a Ti/W metal connector 32 extending through the dielectric layer 34.

Bias gate 24 inverts adjacent p-body regions 28 to create a vertical n-channel between n+ source region 29 and lightly doped n-base layer 36. The current then flows vertically between the n+ source region 29 and the bottom p-type emitter layer 42 (forming a forward biased pnp bipolar transistor driven by an n-channel MOSFET). The high doping of the emitter layer 42 results in a preferred degree of doping of p+.

Since the initial current of the MOSFET action causes a hole to be implanted into the n-base layer 36, this turns on the vertical formed by the p+ contact region 30, the p-body region 28, the n-type base layer 36, and the p-type emitter layer 42. A pnp bipolar transistor to further reduce the forward voltage drop Vce-sat.

To turn off the IGBT, the positive gate-source voltage is removed and the n-base layer 36 is discharged by the p-body region 28, the p+ contact region 30, and the source metal 20. Gate 24 may be shorted to source metal 20 or connected to a slightly negative voltage.

The trench gates 24 in the array of cells 14 are relatively shallow and need only be slightly deeper than the p-body regions 28.

The shield region 16 contains a deeper and wider trench 44 filled with a gate material 46 (e.g., doped polysilicon). The dielectric body 47 has a line in the deep trench 44. Gate material 46 is electrically coupled to various shallow gates 24 via metal contacts 48 and gate metal 50. In one example, the gate 24 may be on the order of 1.5 [mu]m deep, while the gate material 46 in the deep trench 44 may be about 2-2.5 [mu]m deep and wider than the gate 24. As will be explained later, these larger widths of the deep trenches 44 (defined in the masking step) cause them to etch deeper than the narrow trenches during the same etching step, thus forming no deep trenches 44 without additional step.

Lightly doped p-regions between deep trenches 44 and below deep trenches 44, including deep p-regions 56, which are below deep trenches 44; and a shallower p-region 57, which are in deep trenches Between the grooves 44. The deep p-zone 56 may extend downwardly, for example to 2 μm below the deep trench 44. Deep p-region 56 is also referred to as p-shield. The deep p-region 56 has a high resistivity due to the low doping concentration and is weakly biased by the p+ contact region 58 that is connected to the source metal 20 and distributed around the shield region 16.

In this off state, the shallower p-region 57 and the n-base layer 36 are reverse biased. The deep p-region 56 reduces the electric field below the trench 44 because the p-region 56 is completely depleted prior to collapse, which results in a higher breakdown voltage (given a particular dopant concentration of the n-base layer 36). The p-region 56 is also used to laterally deplete the n-base layer 36 to further increase the breakdown voltage. The p-region 56 region can be completely floated, but in order to switch the device from the off state to the on state, the parasitic capacitance due to the depletion layer must be discharged. Accordingly, it is preferred to connect the p-region 56 "weakly" to the source metal 20 via the p+ contact region 58 at certain locations of the die to switch between the device switching from the turn-off to the turn-on state. Discharge the capacitor and reduce the switching delay.

When the IGBT 10 is turned off, the n-base layer 36 and the p-region 56/57 become depleted depending on the magnitude of the potential difference, and the doping causes the shield region 16 to be slightly smaller than the array region in the cell 14. The breakdown voltage is under the voltage of the crash. This prevents damage to the active units after a crash. The important thing is that unit 14 is not Will be affected by the crash, because the damaged unit may draw more current in the unit area and cause thermal runaway. Since these optimal doping levels are affected by many factors, they can be determined by simulation.

Between the deep trenches 44 is a shallow p-type region 57. When the IGBT 10 is turned off, the remaining holes in the n-type base layer 36 are extracted by the p-region 56/57 and mainly by the shallower p-region 57 distributed around the shield region 16 immediately adjacent to the p+ contact region 58. To turn off the IGBT 10 more quickly (ie, the n-type base layer 36 discharges). The holes are also extracted through the p-body region 28 in the array of cells 14.

In addition, another portion of the shield region 16 is formed between the innermost deep trench 44 and the array of cells 14. This region contains a shallow p-region 60 that has the same dopant concentration as the p-body region 28 and is more heavily doped than the p-region 56/57 around the deep trench 44. The holes are also swept away by the shallow p-region 60 via the p+ contact region 62 and the source metal 20. Since this is not a MOSFET region, there is no n+ source region above p-region 60.

2 illustrates some of the arbitrary hole collection trajectories (for improving the cut-off speed) in the shield region 16 by arrows 66, which are referred to as hole bypass regions because some of the holes are swept away by the holes swept by the unit 14. .

In addition, arrow 68 identifies the downward direction of electron injection from the n+ source region 29 region when the IGBT is turned "on". The upward direction of some of the holes injected by the p-type emitter layer 42 during this on time is indicated by arrow 70.

Since the lightly doped p-region 56/57 is depleted with the n-base layer 36 in the off state, the n-base layer 36 can be more highly doped than the conventional n-base layer to reduce the Vce-sat Without reducing the breakdown voltage.

The shielded region 16 can be positioned around the entire array of cells or around a group of cells (eg, a group of cells formed into a strip). In the example of Figure 2, the elements may be in parallel with the various strips of the various regions and gates of the Figure. The shielded area 16 can surround any number of units. Other shaped units are available Can be square, hexagonal, etc. In one embodiment in which the units are formed as a long strip set, the shielded area 16 surrounds up to twenty unit strips. Depending on the current requirements of the IGBT, there may be any number of strip groups connected in parallel.

Double n and n+ buffer layers

The n-type buffer layer 74 and the n+ point 76 (or n+ strip) formed on the buffer layer 74 are also novel. The buffer layer 74 and the n+ point/strip 76 reduce the on-resistance and saturation voltage Vce-sat across the IGBT while preventing the depletion region in the n-base layer 36 from reaching the p-type emitter layer 42 ( Stop penetration) to maximize the breakdown voltage (when the IGBT is turned off). Buffer layer 74 may be about 5 [mu]m thick. Arsenic or antimony n-type dopants are better than phosphorus due to this slower diffusion. The holes from the p-type emitter layer 42 are only implanted into the n-base layer 36 between the n+ dots/strips 76, as indicated by arrow 70. By extending the n+ dot/strip 76, the holes can be injected from the p-type emitter layer 42 through the n-buffer layer 74 between the n+ dots/strips 76, and the n+ dots/strips 76 are used to reduce this. The saturation voltage drops Vce-sat. The n+ dot/strip 76 also quickly sweeps the stored charge in the n-base layer 36 to speed up the turn-off time and allows the n-buffer layer 74 to be thinner for reduced Vce-sat. In addition, a combination of n-buffer layer 74 and n+ dot/strip 76 can be used to customize Vce-sat by adjusting the doping density of buffer layer 74 and the spacing between n+ dots/strips 76. The trade-offs between switching speeds with deadlines.

The fabrication of the apparatus of Figure 2 is described below, including a novel process for forming the bottom portion of the wafer and other features. Various other specific embodiments of termination regions and processing options are also described later.

Referring to Figure 3, the starting substrate 80 is p-type. The n-type buffer layer 74 is then grown in an epitaxial manner. The masking and implantation steps form an n+ point/strip 76. The high resistivity n-base layer 36 is subsequently grown. The thickness and doping are dependent on the desired breakdown voltage. A more highly doped n-layer 82 is then grown over the n-base layer 36, followed by The system is more highly doped with the n-layer 84. In one example, layers 82 and 84 form the top 6-9 μm of the semiconductor layers of the IGBT to form a conical dopant concentration to optimize Vce-sat and breakdown voltage.

The surface is then selectively masked and the p-dopant implant forms a p-well 86 after the drive-in step.

After the p-well 86 is formed, a SiO 2 /Si 3 N 4 /SiO 2 hard mask layer 88 is deposited.

Referring to Figure 4, mask layer 88 is patterned to form the trenches, and the trenches are etched using reactive ion etching (RIE). The equal width openings in the mask layer 88 will inherently form deeper trenches 90 while the narrow openings in the mask layer 88 will form shallower trenches 92. The etch stops after the shallower trench 92 reaches its target depth, which is approximately the depth of the n-layer 84. The depth of the shallower trench 92 may be about 1.5-2.5 [mu]m.

Referring to Figure 5, the shallower trenches 92 are filled with a masking material 94 (e.g., oxide or photoresist) using well known process techniques.

Referring to Figure 6, although shallow trenches 92 are still filled with masking material 94 (Fig. 5), p-type dopants are implanted through deep trenches 90 and driven to form deep p-regions 56. The p-well 86 from Figure 3 now forms a shallower p-region 57. The hard mask layer 88 is then removed. The n-layers 82 and 84 (Fig. 5) are not shown as separate layers in these subsequent illustrations because there is now a smooth n-type dopant concentration change from the top down to the n-base layer 36. All oxides are subsequently removed to expose the shallower trenches 92.

Referring to FIG. 7, the wafer is oxidized to form a gate dielectric 26 (500-1200 angstroms) and a dielectric body 47 on the sidewalls of the deep trench 44. Doped polysilicon is subsequently deposited to fill all of the trenches to form gate 24 and gate material 46 in deep trenches 44. The wafer is then planarized to remove the polysilicon from the top surface.

Referring to FIG. 8, a p-body mask (not shown) is formed to expose a region adjacent to the shallow trench 92, and the p-type dopant is implanted and driven so that the p-body 28 does not extend below the gate 24.

Referring to Figure 9, a mask (not shown) exposes the area between the shallower trenches 92, and the n-type dopant is implanted and driven to form a shallow top n+ source layer. A borophosphorus bismuth glass (BPSG) mask 93 is subsequently deposited to expose the central region of the n+ source layer. The RIE etch removes the isocenter portions of the n+ source layer to form an n+ source region 29 proximate to the shallow gate 24.

Referring to Figure 10, p-dopant implants (boron) are performed using the same mask 93 to form p+ contact regions 62. The boron dose is less than the source dopant implant dose.

Referring back to Figure 2, the Ti/W metal connector 32 is then deposited in the opening of the mask 93 (Figure 10) and the surface is planarized. The dielectric layer 34 in FIG. 2 is the BPSG mask 93 in FIG. The aluminum source metal 20 is then deposited and patterned to make electrical contact with the various n+ source regions 29 and p+ contact regions 62. The gate metal 50 electrically contacts the various gates 24 (in the shallower trenches) and the gate material 46 that fills the deeper trenches 44. The conductive polysilicon forming the gates may be used to electrically connect all of the gate materials together outside of the plane of Figure 2. The gate metal 50 is isolated from the source metal 20 and the gate/source metal layer 50/20 is covered with an oxide/nitride passivation layer 94 in addition to wire bonding the package terminals to the source metal 20 and the gate metal 50 pad pad opening area.

Figures 2-11 illustrate a shielded region 16 having narrow active regions (array of cells 14) between shielded regions 16, and wherein each of the shielded regions 16 has two deep trenches 44 in each of the trenches 44. There are deep p-regions 56 for improving the breakdown voltage, and a shallower p-region 57 between the trenches 44 for quickly sweeping the holes after the IGBTs are switched off to reduce the cut-off time. . As mentioned previously, the solid termination regions collapse at a voltage slightly less than the breakdown voltage of the active region (array of cells 14) to protect unit 14.

11 shows another embodiment of an IGBT having a repeating active region 98 surrounded by a shield region 100, wherein each shield region 100 has only one deep trench 102 for improving the breakdown voltage of the IGBT. All other aspects are the same as in Figure 2.

Forming back features including highly doped p-type dots or strips in the p-type emitter

A novel formation of the back side of the wafer will now be described. The required line has an extremely thin highly doped bottom p-type emitter layer for the most efficient hole injection. The disclosed process forms such a thin highly doped bottom p-type emitter layer without substantially diffusing dopants in the front side, and the resulting bottom surface is roughened by a wet etching process to improve the bottom Electrical contact of the metal electrodes.

Referring to Figure 12, a p-type starting substrate 106 (wafer) is used. Only a single crystal grain region is shown in the germanium wafer. A mask (not shown) is deposited over the top surface of the substrate 106 to create small openings over the central portions of the desired grain regions and to create wider openings at the edges of the die regions. The high energy p-type dopant implant (boron) was carried out at a dose of 5E14-1E16 cm -2 . This produces a smaller strip or dot 108 of higher concentration doped p-type material in the p-substrate 106. Point 108 has a high concentration of doped p+ center 110 and a less doped p shell layer 112. This implantation results in a deeper p+ center 114 and p-shell 116 due to the wider openings at the edges of each grain region. The dopants are not driven at this time.

Referring to FIG. 13, the various layers of the IGBT structure, either conventional or as shown in FIG. 2, may be epitaxially grown over the top surface of the substrate 106, and the various regions and gates are formed to complete the front surface. deal with. The front layers are not shown in detail in Figure 13, and are labeled 118 above the n-buffer layer 74 (which may include the double buffer layers previously described). The various thermal steps for the front side processing initiate initial driving of the p-dopants in the top surface region of the implant substrate 106, and the p-dopant extensions are displayed by layer 119, thus 108 can be combined to some extent. The bottom surface of the substrate 106 is then mechanically The buffing 120 is just below the bottom of the p-type implant site 108, which is about 80-90% of the final thickness of the substrate 106.

Referring to Fig. 14, a slow anisotropic etchant 122 such as potassium hydroxide (KOH), Tetramethyl ammonium hydroxide (TMAH), Ethylene diamine pyrochatechol (EDP) or a mixed solution The back surface is applied to remove the crucible until the p+ center 110 of the point 108 (having a dopant concentration of >1E19 cm -3 ) is optically detected (changing color). Therefore, the p+矽 acts as an etch stop layer and results in a minimum thickness of the p-type emitter of the IGBT. The wet etchant is preferably selective in that it has a different etch rate depending on the crystal orientation of the germanium. The bottom surface is relatively rough after the wet etch due to the different etch rates of the p and p+ regions, which improves the electrical contact of the metal. Additional boron implants may be performed to improve ohmic contact.

During the heating of the wafer during the various steps of fabrication, the dots 108 may merge or may extend to form closely spaced p+ regions. In any case, the bottom of the IGBT surface will essentially be a p+ type layer. The back metal 22 (Al/Ti/Ni/Ag) is subsequently deposited and sintered at a temperature of 450 ° C or lower, which further diffuses the p-dopants. The resulting p-type emitter layer 42 (Fig. 2) may be less than 2 [mu]m, and in one embodiment less than 1 [mu]m.

The wafer is then diced along the lines corresponding to the locations of the wider p+ center 114 and p-shell 116 to split the IGBT dies.

Referring to Figure 15, a modification of the underside structure is shown to form a reverse conducting IGBT, wherein n+ point 124 is near each surface by masking the surface of the substrate 106 (before the top layer is formed) using a 5E15-1E16 cm -2 phosphor implant The edges of the grain regions are formed. The substrate 106 is thinned/etched using the same process as described above and the dopants are driven in. The density of n+ points 124 can also be increased, for example, to completely fill the spaces between p+ points 108.

Referring to Figure 16, the bottom surface is then metallized to form a metal layer 22 that contacts the p+ and n+ portions of the bottom semiconductor layer. The n+ point 124 directly contacts the n-buffer layer 74 and the metal layer 22 to allow reverse current flow through the IGBT when there is a reverse polarity event because the forward biased dipole is reflected when the bottom metal layer 22 is opposite the top The source metal layer is formed when the source metal layer is sufficiently negative.

High voltage edge termination option

Various termination structures around the edges of the die or array of cells are described below, which are particularly useful for very high voltage IGBTs (e.g., over 500V). The edges of the grains used in high power transistors are particularly susceptible to collapse due to the asymmetry at the edges of the grains. Figure 17 - Figure 19 shows the filling of trench with doped polysilicon of termination options, and such illustrations show the remaining trenches with a dielectric material (e.g., an oxide (SiO 2)) filling of termination options.

Figure 17 shows a specific embodiment of an embedded field ring formed by a deep p-region 130 below a deep trench 44 filled with a gate material 46. The deep p-region 130 is formed by being implanted through the trench in the same manner as the deep p-region previously described. Deep p-region 130 may also be referred to as a floating guard ring. Between the trenches is a p-type region 134 formed simultaneously with the p-body region 28 (FIG. 2) of the IGBT. Gate material 46 and p-type region 134 are electrically connected using metal contacts 132 to associated floating metal rings 136A-136D, also referred to as field plates. The floating metal field plates are isolated from each other and equalized under each of the rings 136A-136D to limit the electric fields and maximize the breakdown voltage. An active area containing a cell array and a shielded region (not shown) is to the left of the termination structure. A channel stop region 138 near the outer edge of the die region prevents the formation of a parasitic channel and prevents the depletion region from extending to the extreme edge of the die. Floating the deep p-region 130 enables the n-base layer 36 to be more highly doped (to reduce Vce-sat) without reducing the breakdown voltage of the device.

As the n-base layer 36 is depleted, the depletion penetrates the various floating deep p-regions 130 (starting from the innermost floating p-region 130) and clamps the potential of the deep p-region 130. The p-region 130 injects a small number of holes, and the lost charge is replaced by the depletion of the n-base layer 36 from the outer edge of the p-region 130. Such actions occur continuously from the inner deep p-region 130 to the outer deep p-region 130. As such, there is a smooth depletion zone towards the edge of the die.

The various additional embodiments described below may be different from other embodiments by simply excluding one or more masks, resulting in similar performance, but with fewer manufacturing steps.

18 is similar to FIG. 17, but with the p-body implanted to extend the p-region 134 to the channel stop region 140. Thus, the masking step is saved by implanting the p-body without shielding the right edge of the grain region.

Figure 19 is similar to Figure 18 except that the n-dopant implant used to form the n+ source region 29 (Figure 2) also forms an n+ region 142 between the trenches, thus precluding another masking step.

The deep trench is filled with a dielectric body to vertically float the floating metal ring and the deep P-region

Figure 20 is similar to Figure 17, but with trenches 44 filled with dielectric 146 instead of conductive polysilicon. The trench 44 (before filling with the dielectric body 146) is implanted with a p-type dopant to form a deep p-region 130. The overlying metal forms the floating metal rings, such as ring 136B, that serve as floating field plates. The dielectric filled trenches serve as a vertical gap layer between the deep p-region 130 and the associated metal ring 136, which can be used to control the shape of the depletion region. In this configuration, the vertical depth difference between the depth of the junction of the deep p-region 130 and the depth of the dielectric filled trenches is set to the voltage in each floating field loop.

Figure 21 is similar to Figure 20 except that no p-region 134 (Figure 20) is formed during the p-body implantation and there are fewer metal field plates.

Figure 22 is similar to Figure 21 except that there is no intermediate metal field plate.

Figure 23 is similar to Figure 21 except that a p-region 134 is formed between the trenches filled with dielectric 146 during implantation of the p-body, thereby eliminating a masking step.

Figure 24 is similar to Figure 23, but with a channel-type channel stop zone 148.

Figure 25 is similar to Figure 24, but includes an n+ layer 142 that is formed during implantation of the n-type dopant used to form the n+ source regions of Figure 2, thereby excluding the p-body and the n+ source The implant mask step.

Figure 26 does not form a deep p-region, but instead relies on a p-region 134 connected to its associated metal floating field plate 150 by a metal contact 132 to provide a smooth transition for the edge of the die.

Figure 27 illustrates the termination region using a Junction Termination Extension (JTE) at the embedded junction. After the trench 154 is etched, the p-type boron is implanted in the range of 1-4E12 cm -2 for high energy implantation for deep implantation. After diffusion, those implant pockets of p-region 156 are merged together to form partitions (partitions D1-D4) having different average p-doping concentrations. The trenches 154 are spaced wider toward the edges of the die, and the size of the mesas between the trenches 154 determines the p-charge in each of the zones D1-D4. The relative percentages of the partitions D1-D4 and the p-dopant concentration overlap above the p-region 156, wherein the dopant concentration decreases toward the edge of the die. There is a smaller table in partition D1 and a larger table in partition D4. More partitions can be added to maximize the breakdown voltage and minimize process crash variances with process changes, as well as minimize the number of crash variations with different polarities and amounts of oxide charge. The conical dopant concentrations extend the electric field more evenly. The merged p-region 156 is electrically coupled to the metal field plate 150 via the p-region 159 and the metal contacts 132. Metal field plate 150 may be connected to a reference voltage or float. An n-region 158 (a portion of the n-base layer 36) between the surface and the p-region 156 is segmented by a dielectric filled trench 154. These floating n-regions 158 will assume the local potential of the adjacent partition. This will make the termination region insensitive to oxide charge changes and n-dopant concentration variations in the top region/surface.

28 is similar to FIG. 27 except that there is an additional external field plate 160 electrically coupled to the merged p-region 156 via p-region 162 and metal contacts 132.

Figure 29 is similar to Figure 28 except that there is a masking step to save the p-body implant forming the p-region 168.

The beveled edge of the die increases the breakdown voltage

Figure 30 illustrates the most edge of the die region, wherein the mask is used to etch the edges of the die regions on the wafer to form a slope along the saw streets for segmentation The edge 170 is cut. Mask wet etching will form such beveled edges. The surface is then passivated with an oxide/nitride layer 172. The grains are then split between the beveled edges 170 of adjacent grain regions. The beveled edges allow the IGBT to support voltages in excess of 1700V due to better electric field distribution due to the beveled edges.

in conclusion

Various inventions are disclosed herein to provide improvements for IGBTs or other power transistors, including but not limited to:

1. Periodically highly doped p-type emitter splices or strips (Figs. 12-14) are formed in the top surface region of the growth substrate, followed by growth of the various transistor layers. These points/strips may merge to some extent due to the various heating steps. The bottom surface of the substrate is then polished and then wet etched to expose the highly doped p-type germanium. The highly doped p-type emitter splices or strips (or merged layers) identify an etch stop layer during the wet etch, resulting in an extremely thin p-type emitter. This thin p-type emitter enables a highly efficient IGBT with a low Vce-sat. The dots/strips also create a roughened bottom surface after a wet etch to improve metal-to-substrate contact.

2. The termination structure (Figs. 20-25) is formed to surround the cell array, wherein the dielectric fills the deep trench, wherein the deep p-region is below each trench (by implantation into the trench), wherein A metal ring (field ring) is placed over each trench to provide a highly controllable termination characteristic, and wherein a vertical depth difference between the deep p-intersection and its associated metal ring sets each floating connection The voltage of the ring to improve the breakdown voltage.

3. A double buffer layer (Fig. 2) formed over the p-type substrate (emitter), comprising a first n layer overlying the substrate; and a thin second n+ layer over the first n layer Used to reduce the Vce-sat while maximizing the breakdown voltage by stopping penetration. The n+ layer may be formed by dots or strips, and holes from the p-type substrate are implanted between the dots/strips. Thus, the hole injection efficiency is not adversely affected by the n+ layer.

4. A deep and wide trench (Fig. 2) is formed, wherein deep p-regions are below the trenches surrounding the cell array for controlling the breakdown voltage, with shallower p-regions in the deep p-region Between, it is used to quickly remove the hole to quickly cut off the device and prevent the occurrence of thyristor action. A conductive material fills the trenches.

5. In the termination region (Figs. 27-29), the array of trenches is formed at varying pitches and then p-type dopants are implanted into the trenches. The trenches are spaced wider toward the edge of the die. After diffusion, the p-regions merge and form a lateral p-type partition with different average p-doping concentrations. The width of the mesa between the trenches is inversely proportional to the p-charge in each partition, so the p-doping concentration decreases toward the edge of the die. The p-zones are connected to the top metal field plate. The gradient of the p-doping concentration provides a more uniform electric field distribution to increase the breakdown voltage.

6. The miter saw channel 170 (Fig. 30) between the dies is formed by wet etching for very high voltage devices. A passivation layer (oxide 172) is formed over the beveled edge and the saw streets.

The above six points of invention are further summarized as follows:

1. A method of forming a vertical power device (Figs. 12-14) comprising: Providing a substrate 106 having a top surface and a bottom surface; doping a top surface area of the substrate with a dopant of a first conductivity type (eg, p-type) to align a top surface of the substrate a first conductivity type that is more highly doped than a bottom surface region of the substrate; a lift layer 118 of a second conductivity type is grown on the top surface of the substrate, and the first conductivity type 28 and the second conductive layer are formed a region of type 29 to form a vertical transistor structure; polishing the bottom surface of the substrate; wet etching the polished bottom surface of the substrate using the top surface region as an etch stop layer to expose the top surface region; After the etching, a first metal electrode 22 is formed on the exposed top surface region; and a second metal electrode 20 is formed on the epitaxial layer.

2. A termination structure for a transistor (Figs. 20-25) comprising: a cell array 14 formed in a first semiconductor material 36 of a first conductivity type (e.g., n-type); a concentric trench 44 Forming in a first semiconductor material surrounding the array of cells; a deep region 130 of a second conductivity type formed below the trenches, wherein each deep region is associated with one of the trenches; a dielectric material 146 at least partially filling the trenches; and a conductive ring 136 overlying each of the trenches, each of the conductive loops being a floating field loop, wherein each trench The dielectric material inside is used as a vertical space between the deep regions and the conductive ring A gap layer wherein a vertical depth difference between the deep junction and its associated metal ring sets a voltage for each of the rings.

3. A vertical transistor structure (Fig. 2) comprising: a first semiconductor material 36 of a first conductivity type (e.g., p-type); a first buffer layer 74 of a second conductivity type at which the first semiconductor material Above, the first buffer layer has a first dopant concentration; the second conductivity type is a second buffer layer 76 formed on the first buffer layer, the second buffer layer having a higher than the first a second dopant concentration of the dopant concentration, the second buffer layer forming a lateral first region separated by a second region of the first buffer layer; and a second semiconductor material 42 of the second conductivity type, Formed on the second buffer layer and having a third dopant concentration lower than the first dopant concentration; and a cell array 14 formed in the second semiconductor material.

4. A vertical transistor (Fig. 2) comprising: a cell array 14 formed in a first semiconductor material 36 of a first conductivity type (e.g., n-type); a concentric trench 44 surrounding the cell array Formed in the first semiconductor material; a second conductivity type deep region 56 formed under the trenches, wherein each deep region is associated with one of the trenches; a shallow region 57 between the trenches; a conductive material 46 filling the trenches; a substrate 42 of the second conductivity type, which is at least by the first semiconductor material Separated vertically from the shallower areas; a first electrode 22 formed on a bottom surface of the substrate; and a second electrode 20 formed on the cell array and at least a portion of the trenches, wherein the isobath region and the shallower The zone electrically couples 32/58 to the second electrode.

5. A method of forming a vertical transistor (Figs. 27-29) comprising: forming a cell array 14 in a first semiconductor material 36 of a first conductivity type (e.g., n-type); Forming a concentric trench 154 in a semiconductor material, wherein a space between the trenches increases with distance from the cell array; implanting a first dopant of a second conductivity type into the trenches, Forming a first region of the second conductivity type under each trench; diffusing the first dopants to combine the first regions and forming a partition of the first dopants (division D1-D4 The dopant concentration of one of the first dopants decreases laterally with distance from the cell array due to the varying spaces between the trenches; Coupling to a metal field plate; forming a first electrode 22 on one of the bottom surfaces of the transistor; and forming at least a portion of the cell array to form a second electrode 20.

6. A vertical transistor die (Fig. 30) comprising: a cell array 14 in a first semiconductor material 36 of a first conductivity type (e.g., n-type); an etched beveled edge 170 along which The outer edge of the die; and a passivation layer 172 formed over the beveled edge.

While the invention has been shown and described with reference to the embodiments of the present invention All such changes and modifications are intended to be included within the true spirit and scope of the invention.

10‧‧‧Insulated gate bipolar transistor (IGBT)

14‧‧‧ unit; cell array

16‧‧‧Shielded area

19‧‧‧ load

20‧‧‧Top source metal

22‧‧‧Bottom emitter metal

24‧‧‧Channel-type gate

26‧‧‧thin dielectric

28‧‧‧p-body area; first conductivity type

29‧‧‧n+ source region; second conductivity type

30‧‧‧p+ body contact area

32‧‧‧Ti/W metal connectors

34‧‧‧ dielectric layer

36‧‧‧n type base layer; first semiconductor material

42‧‧‧p-type emitter layer; second semiconductor material

44‧‧‧Ditch

46‧‧‧gate material; conductive material

47‧‧‧ dielectric

48‧‧‧Metal joints

50‧‧‧ gate metal

56‧‧‧Deep p-zone

57‧‧‧ lighter p-zone

58, 62‧‧‧p+ contact area

60‧‧‧shallow p-zone

66, 68, 70‧‧‧ arrows

74‧‧‧n type buffer layer; first buffer layer

76‧‧‧n+ points/strips; second buffer layer

94‧‧‧Oxide/nitride passivation layer

Claims (18)

  1. A method of forming a vertical power device includes: providing a substrate having a top surface and a bottom surface; doping a top surface area of the substrate with a dopant of a first conductivity type to make a top surface of the substrate a first conductivity type that is more highly doped than a bottom surface region of the substrate; a layer of epitaxial layer of a second conductivity type grown on a top surface of the substrate, and forming the first conductivity type and the second a region of conductivity type to form a vertical power device; forming a first metal electrode over the vertical power device; polishing the bottom surface of the substrate; wet etching the polished bottom surface of the substrate using a etchant, using the substrate a more highly doped first conductivity type top surface region as an etch stop layer to expose the top surface region on the bottom of the vertical power device; and a second metal electrode on the bottom of the vertical power device .
  2. The method of claim 1, wherein the step of growing the epitaxial layer on the top surface of the substrate and forming the regions of the first conductivity type and the second conductivity type comprises: forming in the epitaxial layer a body region of the first conductivity type; and forming a source region of the second conductivity type in the epitaxial layer, wherein the source region is coupled to the first metal electrode, wherein a bias gate is A conductive path is formed in the body region to conduct a current between the first metal electrode and the second metal electrode.
  3. The method of claim 2, wherein the vertical power device is an isolated gate bipolar transistor (IGBT).
  4. The method of claim 2, wherein the vertical power device is a metal oxide semiconductor field effect transistor (MOSFET).
  5. The method of claim 1, wherein the step of wet etching causes the exposed top surface region of the substrate to have a roughened surface to contact the second metal electrode, wherein the roughened surface has different doping Different etch rates of the first conductivity type material of the concentration.
  6. The method of claim 1, wherein the step of wet etching the bottom surface of the substrate using the top surface region of the substrate as the etch stop layer comprises optically detecting a highly doped top surface region of the first conductivity type One color change.
  7. The method of claim 1, wherein the step of doping the top surface region of the substrate with the dopant of the first conductivity type comprises: masking a top surface of the substrate to expose a plurality of regions of the top surface; The first conductivity type dopant is implanted into the plurality of exposed regions to create a segmented highly doped region of the first conductivity type in the top surface region of the substrate.
  8. The method of claim 7, further comprising heating the substrate to diffuse the dopants of the first conductivity type in the top surface region.
  9. The method of claim 1 wherein the step of polishing the substrate comprises polishing the substrate to greater than 80% of its final thickness after the wet etching.
  10. The method of claim 1, wherein the dopants of the first conductivity type comprise boron, and wherein a boron concentration in a top surface region of the substrate is greater than a step of doping a top surface of the substrate 1E19cm -3 .
  11. The method of claim 1, wherein the substrate is of the first conductivity type.
  12. The method of claim 1, further comprising doping the region of the top surface region of the substrate with the dopant of the second conductivity type to provide reverse conduction through the device when the voltage polarity is reversed.
  13. A vertical transistor includes: a substrate having a top end surface and a bottom surface; a top surface area of the substrate comprising a first region containing a dopant of a first conductivity type to enable the first region a first conductivity type that is more highly doped than a bottom surface region of the substrate, wherein the top surface region also includes a second region of the first conductivity type having a lower doping than the first regions a concentration; an epitaxial layer of a second conductivity type grown over a top surface of the substrate; a body region of a first conductivity type in the epitaxial layer; a second conductivity type in the epitaxial layer a source region; a gate separated from the body region, wherein a bias gate generates a conductive path in the body region; wherein a top surface of the substrate is polished and then wet etched to expose the top a surface region, wherein the top surface region is roughened by wet etching having different etch rates for the first regions and the second regions; a first metal electrode over the vertical transistor, wherein the source region is coupled to the first metal electrode; and a second metal electrode on the roughened tip surface region on the bottom of the vertical transistor .
  14. The transistor of claim 13, wherein the vertical electro-crystalline system is an IGBT.
  15. The transistor of claim 13, wherein the vertical transistor system is a MOSFET.
  16. The transistor of claim 13, wherein a concentration of a first conductivity type dopant in the first regions of the top surface region of the substrate is greater than 1E19 cm -3 .
  17. A transistor as claimed in claim 13 wherein the first regions comprise dots or strips and the second regions comprise regions between the dots or strips.
  18. The transistor of claim 13 further comprising a third region of the top surface region comprising dopants of the second conductivity type to provide reverse conduction through the transistor when the voltage polarity is reversed.
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TW201535712A (en) * 2014-02-04 2015-09-16 Maxpower Semiconductor Inc Vertical power MOSFET including planar channel
TW201537627A (en) * 2013-12-27 2015-10-01 Toyota Motor Co Ltd Semiconductor device and method for manufacturing same
TW201637214A (en) * 2015-04-14 2016-10-16 新唐科技股份有限公司 Semiconductor device and method of manufacturing the same
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US20140077253A1 (en) * 2011-06-08 2014-03-20 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same
TW201537627A (en) * 2013-12-27 2015-10-01 Toyota Motor Co Ltd Semiconductor device and method for manufacturing same
TW201535712A (en) * 2014-02-04 2015-09-16 Maxpower Semiconductor Inc Vertical power MOSFET including planar channel
US20160365250A1 (en) * 2014-09-04 2016-12-15 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
TW201637214A (en) * 2015-04-14 2016-10-16 新唐科技股份有限公司 Semiconductor device and method of manufacturing the same

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