TW201903956A - Power element with polycrystalline silicon filled trenches with tapered oxide thickness doping nitrogen into the trench walls to form tapered oxide - Google Patents

Abstract

In a specific embodiment, a power MOSFET conducts current vertically. The bottom electrode may be connected to a positive voltage, and the top electrode may be connected to a low voltage, such as a grounded load. Gates and/or field plates (e.g., polycrystalline silicon) are embedded in the trench. The trench has a tapered oxide layer that isolates the polycrystalline silicon from the silicon walls. The oxide is thicker in the bottom of the trench than in the top to increase the breakdown voltage. The tapered oxide is formed by doping nitrogen into the trench walls to form a tapered nitrogen-doped concentration. After annealing, a tapered silicon nitride layer is formed. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.

Description

Power element with polycrystalline germanium filled trench with tapered oxide thickness

This application claims the benefit of the assignee to the present assignee, the disclosure of which is incorporated by reference in its entirety in its entirety in its entirety in its entirety in its entirety in The priority of U.S. Provisional Patent Application Serial No. 62/215,563, filed on Jan.

The present invention relates to trench gate elements, such as certain vertical or lateral MOS-gated devices, and more particularly to techniques for forming trenches having a tapered oxide thickness, wherein the oxidation The object is thicker near the bottom of the trench to increase the breakdown voltage and reduce the capacitance. The tapered oxide can also be used in trench field plates.

A vertical MOS field effect transistor (MOSFET) using a trench gate is widely used in high voltage and high power due to its relatively thick, low dopant concentration drift layer that can achieve high breakdown voltage in the off state. Transistor. Typically, the MOSFET includes a highly doped n-type substrate, a thick low dopant concentration n-type drift region, a p-type body formed in the drift region, and an n-type source at the top of the body. And a vertical (drainage) gate separated by a thin gate oxide from the channel region. A source electrode is formed on the top surface, and a drain electrode is formed on the bottom surface of the substrate. When the gate is sufficiently positive with respect to the source, a vertical region in the p-type body between the n-type source and the n-type drift region is inverted to generate between the source and the drain Conductive path or channel.

In the off state of the MOSFET, when the gate is shorted to the source or is under a negative bias, the drift region is depleted, and a high breakdown voltage (eg, over 600 volts) can be maintained at the source and the drain between. However, the on-resistance is impaired due to the low doping required for the thick drift region. Increasing the doping of the drift region reduces the on-resistance but reduces the breakdown voltage.

Such conventional vertical MOSFETs use trenches with substantially parallel opposing sides, wherein thin gate oxides are grown on the walls of the trenches. The oxide has substantially the same thickness along the walls. The trench is then filled with doped polysilicon to form the gate. These filled trenches may also be used as field plates to provide a more uniform electric field distribution.

Kenya Kobayashi et al. entitled "100V Class Multiple Stepped Oxide Field Plate Trench MOSFET (MSO-FP-MOSFET) for 100V Classes to achieve the final structure) Aimed to Ultimate Structure Realization) (the 27th International Symposium on Power Semiconductor Components and Integrated Circuits Proceedings, pp. 141-144) illustrates a trench with a variable thickness oxide layer, wherein the oxide faces the channel The bottom of the trench is thicker. The trenches are then filled with doped polysilicon. Figure 1 is reproduced from this paper, showing an n-drain 12 (which may be the substrate), an n-drift region 14 of a generally rectangular trench 16, a tapered oxide 18 of the lining trench 16, and a blend of gates 20. a heteropolysilicon, a p-body 22, an n+ source 24 over the p-body 22, a top source metal layer 25 connected to the n+ source 24 and the p-body 22, and a gate 20 isolated from the source metal layer 25. The vertical MOSFET of oxide 26. A gate metal electrode (not shown) is connected to the gate 20. In normal operation, a positive voltage is applied to the drain 12 and one terminal of the load is connected to the source metal layer 25. The other terminal of the load is grounded. When the gate 20 is biased above the critical level, the p-body 22 is inverted to conduct current vertically between the source 24 and the drain 12. The thick drift region 14 supports the electric field when the gate 20 to the source metal layer 25 are shorted. A relatively low doped drift region 14 is required for a good breakdown voltage, but the on resistance is increased. When the gate 20 to the source metal layer 25 are short-circuited, they function as field plates as explained below.

By providing a thicker oxide 18 near the bottom of the trench 16, where the electric field is highest when the MOSFET is turned off, the oxide isolation layer can withstand higher voltage fields than conventional thin gate oxides. The oxide is nearly as thin as the top of the trench 16 beside the channel region (p-body). The grounding gate 20 acts like a field plate to evenly distribute the electric field in the drift region 14 by laterally depleting the drift region 14, which increases the breakdown voltage. In other words, the depletion region in the drift region 14 (in the mesa) between the trenches 16 is more uniform.

The Kobayashi paper shows how the oxide in the trench 16 is gradually thinned by continuously growing a new oxide layer in the trench and etching each new oxide layer back to a different depth, thus remaining after each etch The older oxide layers are applied to the overall thickness of the oxide layer at the different depths. This process is very time consuming and can only be used to form an oxide layer having only a few stepped thicknesses.

New techniques are needed for tapered oxides in trenches that form such shortcomings without the techniques described in the Kobayashi paper.

Various techniques are described herein for producing a tapered (including stepped) oxide layer that is isolated from the walls of trenches formed in tantalum, tantalum carbide (SiC) or other germanium containing wafers. The trench is then filled with a conductive material such as doped polysilicon. The filled trench may be used to control the gate of the current through a vertical transistor or other component, or as a field plate to increase the breakdown voltage.

In a specific embodiment, the trench is formed in a germanium wafer, wherein the trench has sidewalls that are vertically or inwardly inclined toward the bottom of the trench. Nitrogen is then implanted into the walls to create a tapered nitrogen dopant concentration along the walls, wherein the dopant concentration decreases with depth into the trench. A smooth or stepped taper of the dopant concentration is achieved by varying the angle of the nitrogen implant during the implantation process.

The nitrogen is chemically bonded to the ruthenium during the annealing step to form a tantalum nitride of the tapered layer. The nitride oxidizes at a much lower rate than ruthenium. Thus, during the oxidation step, the oxide growth near the bottom of the trench is much higher than near the top of the trench, resulting in a relatively thick oxide near the bottom of the trench in the channel region, while approaching The top of the trench produces a relatively thin oxide.

The trench is then filled with doped polysilicon to form a gate or field plate or a combination of gate and field plates.

The resulting component may be a vertical or lateral MOSFET, an insulated gate bipolar transistor (IGBT), a thyristor, or other controllable element.

In a specific embodiment, the substrate has a bottom n+ surface forming a drain (connected to a positive voltage), a thick n-drift region, a p-well/body capable of forming a channel region, and in the p-well/body n+ source (connected to the load). If the body portion capable of forming the channel region is vertical, the filled trench along the body region can be used as a vertical gate to invert the body region and form a vertical conductive path between the source and the drain ( aisle). When the transistor is turned off, by grounding the gate, the gate acts like a field plate to improve the breakdown voltage.

Alternatively, a top planar gate may overlie a lateral channel region in the p-well/body, and the fill trench surrounds the p-well/body to form a field plate ring (electrically connected to the source), The electric field can be more evenly distributed when the transistor is turned off to increase the breakdown voltage.

In either embodiment, the thicker oxide at the bottom of the trench is better able to withstand higher voltages than the thinner oxide near the top of the trench. Therefore, the breakdown voltage is increased. The parasitic capacitance is also reduced by the thicker oxide, so the cutoff time is reduced. A thin oxide near the top of the trench can follow the channel region, so the gate characteristics (e.g., threshold voltage) are not affected by the thicker oxide at the bottom of the trench.

A 25% increase in crash voltage can be achieved using this technique.

Accordingly, the tapered oxide in the trench is formed in a faster and more controllable manner than the technique described in the Kobayashi paper, thereby achieving a smoother taper of the oxide.

In one example of a vertical MOSFET formed in accordance with the present invention, the starting substrate is of the n+ or n++ type. The substrate may be tantalum, SiC or another material containing niobium which can grow oxides. This wafer will be used to simultaneously form many MOSFETs that are later divided. Such MOSFETs will typically be of a high power type, such as those that can withstand 600 volts. A relatively thick n-drift layer is then epitaxially grown on the substrate, wherein the dopant concentration and thickness are dependent on the desired breakdown voltage.

2 through 22 illustrate a small portion of a wafer corresponding to a single transistor region (or cell).

Figure 2 illustrates a trench 30 etched on the top surface 31 of the wafer. The trench 30 can be formed prior to any p-well and n+ source to limit the diffusion of dopants in those regions.

A patterned mask 32 (e.g., nitride, oxide, or photoresist) exposes the area of the germanium that will form the trench 30.

In the example of FIG. 2, the trenches 30 are etched using an anisotropic etch (eg, reactive ion etching (RIE)) to have tapered sides. The tapered sides enable nitrogen to be more easily implanted with tapered dopant concentrations along the sidewalls of the channels, as will be described later. The depths of the trenches will typically be a micron and extend into the drift region of the MOSFET. The sloping sidewalls that form the trench are well known. Some possible techniques include varying the temperature, pressure, and additives during the plasma etching process, as described in Robert Carlile et al., incorporated herein by reference, in the trench etching in a crucible with controllable sidewall angles ( Trench Etches in Silicon with Controllable Sidewall Angles) (1988, Journal of the Electrochemical Society). An alternative process for forming such sloping sidewalls is described in U.S. Patent No. 5,945,352, which is incorporated herein by reference. An alternative process for forming the sloped sidewalls involves tilting the wafer relative to the incident excitation ions (e.g., argon) during the etching process. Other technologies can be used.

In a specific embodiment, the side walls are at an angle of 5 to 20 degrees with respect to the centerline of the trench.

In Figure 3, a nitrogen implant 33 is performed (e.g., at a dose of 3 x 10E15 ions-cm ^-2 ) to implant nitrogen ions 34 just below the surface of the sidewalls of the channels. The implantation is performed over a range of angles such that the top portions of the trenches 30 have a higher nitrogen dopant concentration than the bottom portions of the trenches 30. The wafer is then annealed (e.g., over 1000 °C) under an argon atmosphere to form a tapered tantalum nitride layer along the sidewalls.

The implantation of nitrogen into the surface of the crucible to inhibit oxide growth (e.g., for forming an embedded nitride layer and for producing an oxide mask layer) is well known and incorporated by reference in the text of K. Schott et al. "Blocking of Silicon Oxidation by Low-Dose Nitrogen Implantation" (Appl. Phys. A 45, pp. 73-76) Description. Implantation of nitrogen has not been used to create a tapered oxide thickness in the trenches for MOSFETs.

Providing the slanted sidewalls preferably allows the tilt of the wafer to expose the varying areas of the sidewalls to the nitrogen ions. The tilt can vary smoothly or can be stepped.

As shown in FIG. 4, the wafer is then subjected to a dry oxygen atmosphere at a temperature of about 1020 ° C for a time required to grow the tapered oxide 36, for example, about 300 minutes. In the illustrated example, the oxide 36 has a maximum thickness of about 175 nm at the bottom of the trench 30 and drops to only about 10 nm at the top of the trench 30 (at the maximum nitrogen concentration), wherein the thin oxide is adjacent to the channel region.

5-7 illustrate a simplified technique for forming a stepped oxide wherein the trench 40 has vertical sidewalls. An n+ substrate 42 and an n-drift region 44 are shown. In FIG. 5, the nitrogen implant 33 is performed at a first angle, which substantially prevents nitrogen from being implanted below a certain depth in the trench 40. Figure 6 shows the implantation of the opposite side wall using the opposite implantation angle. Four or more different angle implants may be required to implant nitrogen in all of the sidewalls of the trench. After the annealing and oxidation, the oxide obtained in FIG. 7 includes a thick oxide layer 45 that is adjacent to the bottom of the trench 40; and a thinner oxide layer 46 that is near the top of the trench 40. Additional implant angles can be used to create more stepped oxide thickness or even smooth taper.

FIG. 8A illustrates the exposed trench 40A undergoing the nitrogen implant 33, while the other trench 40B is masked by the photoresist 47.

Figure 8B shows the substrate of Figure 8A after removal of the photoresist 47, followed by an annealing step and an oxidation step. It is assumed that the nitrogen has been uniformly implanted in the walls of the trench 40A. As a result, the oxide 48 in the trench 40A is much thinner than the oxide 49 in the trench 40B. In some applications, it is desirable to have different oxide thicknesses in the trenches of the same die, such as where the trenches perform different functions or are exposed to different electric fields.

Figure 9 is a variation of Figure 8A in which the nitrogen implant 33 (Figure 8A) is performed at a relatively shallow angle to the opposite sidewalls of the trench 40A, such that the bottom of the trench 40A does not contain or contain a point after the annealing step. Tantalum nitride. After the oxidation step, the oxide 50 in the upper portion of the trench 40A is much thinner than the oxide 51 at the bottom of the trench 40A.

The processes described herein thermally grow oxides in the trenches because the grown oxide is affected by tantalum nitride in the trench. In another embodiment, a composite thermally grown tapered oxide and a deposited oxide (eg, using a chemical vapor deposition (CVD) process for the deposition) are formed in the trench. The deposited oxide is not affected by the nitride and can form a layer of the same thickness. If the oxide grown is tapered, the resulting composite oxide will be tapered.

Figure 10 illustrates one possible element that may be formed using the tapered oxide techniques described herein. In FIG. 10, trenches 30 with tapered oxides 36 are filled with conductive doped polysilicon 52 to form vertical gates for MOSFETs or IGBTs. Assuming that the n-channel MOSFET is formed, the substrate 42 (dip) is of the n+ type and the drift region 44 is of the n-type. A p-well 54 is formed on the top surface with the p+ contact region 56 and the n+ source 58. The source metal layer 60 (source electrode) contacts the p+ contact region 56 and the n+ source 58. The drain metal layer 61 (the drain electrode) contacts the bottom of the substrate 42. The substrate 42 may be thinned before the formation of the gate metal layer 61. A gate metal (not shown) contacts the polysilicon 52 in the trenches. Assuming that the drain is connected to a positive voltage and the source is connected to a lower voltage, then a sufficient positive voltage is applied to the p-well 54 where the gate will reverse in the region immediately adjacent the gate to create a vertical current path. The thin oxide next to the channel region allows for a low threshold voltage. While the MOSFET is in its off state, while the ground gate (serving the field plate) laterally depletes the drift region 44, a much thicker oxide near the bottom of the trench 30 is tolerated in the drift region 44. The high electric field is deep to increase the breakdown voltage of the MOSFET.

If the substrate 42 is of the p+ type, a vertical PNP bipolar transistor is formed which is turned on by applying the threshold voltage to the gate. The initial flow of current due to the action of the MOSFET turns on the PNP transistor to conduct current between the top p-type emitter and the bottom p-type collector. This structure is an IGBT.

The polysilicon filling the trench can also be used as a dedicated field plate. Figure 11 illustrates a trench 30 in which the bottom polysilicon portion forms a field plate 62. Field plate 62 can be connected to the source or floated. Oxide layer 63 is then formed over field plate 62 for isolation, and then the remainder of trench 30 is partially filled with polysilicon, which is connected to the gate metal for use as gate 64 for the MOSFET or IGBT. If the gate 64 is shorted to the source in the off state, the gate 64 is also used as a field plate. The field plate laterally depletes the n-type layer 44 when the element is turned off to increase the breakdown voltage.

In another embodiment, the trench gate and the trench field plate may be formed separately, wherein the trench field plate surrounds the transistor or cell. The processes used to form the trench gate and the trench field plate may be the same, so they may be formed simultaneously.

12 through 22 illustrate a MOSFET in which the trench 30/40 has a sloped sidewall or a vertical sidewall. In either case, tapered oxides are formed in the trenches, and the trenches are then filled with conductive polysilicon (or other conductive material). In these examples, the main channel region is on the top surface of the wafer and the channel region is reversed by the lateral gate 70.

In FIGS. 12 to 19, 21 and 22, the polysilicon in the trench 30/40 is only used as the field plate 72. The trench 30/40 is formed much deeper than the p-well 54 to allow the polysilicon to perform its function as a field plate. Field plate 72 may be shorted to source metal layer 60 or to gate 70, or may be floating. Field plate 72 surrounds the MOSFET cell and extends the electric field to increase the breakdown voltage. The function of the field board is well known.

Figure 12 is a cross-sectional view of a single vertical double diffused metal oxide semiconductor (DMOS) transistor cell (which may be part of a strip) in an array of identical connected cells connected in parallel. The p+ contact region 74 contacts the source metal layer 60. The lateral gate 70 includes a vertical extension 76 that strengthens the adjacent n-layer 78 to reduce the on-resistance. Dielectric body 80 (e.g., oxide) isolates source metal layer 60.

In Figure 12, the illustrated monomers have a width of between about 5 and 15 microns. The monomer can have a breakdown voltage in excess of 600 volts, and the amount of monomer in the array of identical monomers determines the current handling capability, such as 20 amps. The array of cells may be in the form of strips, squares, hexagons or other known shapes.

In one general application, the bottom drain metal layer 61 is connected to a positive voltage supply and the top source metal layer 60 is connected to one terminal of the load. The other terminal of the load is grounded. When a positive voltage greater than the threshold voltage is applied to the gate 70, the top surface of the p-well 54 is reversed to create a lateral conductive path through the p-well 54. In addition, electrons accumulate in the n-layer 78 adjacent the vertical extension 76 of the gate 70 to extend the current and reduce the on-resistance of the n-layer 78. As a result, current is conducted between the source metal layer 60 and the gate metal layer 61.

The vertical extension 76 of the gate 70 can extend below the p-well 54, but reduces the gate-drain capacitance by extending the vertical extension 76 deeper into the trench 30/40 (by reducing its surface area) There are trade-offs between reducing the on-resistance and reducing the on-resistance.

In this off state, the field plate 72 laterally depletes the n-drift region 78 which is more highly doped than the lower n-drift region 44 to increase the breakdown voltage. As the n-drift region 78 becomes depleted, the bottom n-drift region 44 can be made thinner, so the on-resistance is reduced. The entire n-drift region 78 is preferably completely depleted at the beginning of the crash. The n-drift region 44 is preferably completely depleted at the beginning of the crash.

The combination of the lateral DMOS transistor portion, the higher doping of the n-layer 78, the vertical extension 76 of the gate 70, and the reduced thickness of the n-drift region 44 reduces the on-resistance compared to the prior art.

If the PN diodes of the MOSFETs become forward biased and then reverse biased, the utility of the vertical field plate 72 (connected to the source) also accelerates the switching time.

The thickness of the gate oxide 82 under the gate 70 and along the vertical extension 76 of the gate 70 is much thinner than the oxide 36 of the isolation field plate 72. Since the electric field near the top of the n-drift region 78 is much less than the electric field near the bottom of the n-drift region 78, the oxide can be thinner near the top of the MOSFET without reducing the breakdown voltage.

The utility of the vertical extension 76 of the gate 70 (accumulating electrons along the sidewall) allows for a reduction in the p-well to trench spacing, thereby reducing the cell spacing and active area while still resulting in lower on-resistance, which Lead to lower Rsp. The spacing can be, for example, less than 0.1 to 0.5 of the depth of the p-well junction. Field plate 72 may be electrically connected to gate 70 or source metal layer 60 or may be floating. Connecting the field plate 72 to the source metal layer 60 provides a lower gate-drain capacitance or a lower gate-drain charge Qgd, while the field plate 72 is connected to the gate 70 due to biasing of the gate 70. At positive voltages, electron accumulation layers are produced along the longer lengths of the sidewalls of the trenches, thus resulting in lower on-resistance.

The trench 30/40 may be 2-20 microns deep. The width of the trench 30/40 (between adjacent cells) may be 1-2 microns. The p-well 54 depth may be about 2.5 microns. These thicknesses of the n-drift region 78 and the n-drift region 44 are determined based on the desired breakdown voltage and can be determined using simulation.

If the single system encloses a monomer (e.g., a hexagon or a square), the vertical extension 76 of the gate 70 and the vertical field plate 72 surround the n-drift region 78. If the single system strip, the vertical extension 76 of the gate 70 and the vertical field plate 72 extend along the length of the n-drift region 78.

Figure 13 shows another embodiment similar to the embodiment of Figure 12, but with a self-aligned p-shielding region 90 under the trench 30/40. In this off state, the element is reverse biased and the p-shield region 90 reduces the electric field below the trench 30/40, since the p-shield 90 is completely depleted before the crash, which results in a higher breakdown voltage. The p-shielding region 90 is also used to laterally deplete the n-drift region 78 to further increase the breakdown voltage. The p-shielding region 90 can be floating, but if the component is to be switched from the off state to the on, parasitic from the depletion layer between the p-shielding region 90 and the n-drift regions 78 and 44 The capacitor must be discharged. Accordingly, it is preferred to connect the p-shielding region 90 to the source metal layer 60 via the p-well 54 and a p-type junction region at certain locations of the die (not shown). The connection of p-shield region 90 to source metal layer 60 provides a path for discharging current to the capacitor and improves switching delay during switching of the component from the turn-off to the turn-on state.

Figure 14 shows another embodiment similar to the embodiment of Figure 13, but with p and n charge balancing rows 94 and 95 to reduce the Rsp. The n-line 95 is more highly doped than the n-layer 78, thus helping to reduce the on-resistance. The n and p rows 94/95 are depleted when the device is turned off, and are preferably fully depleted at the beginning of the crash.

Figure 15 shows another embodiment similar to the embodiment of Figure 14, but with a self-aligned strengthened n-surface region 98 (n-Surf) surrounding the edge of p-well 54 and extending to the sidewall of the trench. . The n-surface region 98 has a higher doping concentration than the n-layer 78. The vertical extension 76 of the gate 70 accumulates electrons in the n-surface region 98 to further reduce its on-resistance. Thus, n-surface region 98 provides lower on-resistance and better current spreading. Preferably, p-shield 90 and p and n rows 94/95 are completely depleted at the beginning of the collapse.

Figure 16 shows another embodiment similar to the embodiment of Figure 15, but with multiple layers of p and n charge balancing rows 94/95, 94A/95A. By forming the p and n rows into a plurality of "thin" layers, there is less lateral dopant extension, so that the rows can be formed more accurately. It should be noted that the lower p-line 94A is wider than the higher p-line 94 due to this additional thermal budget. More than two layers of p and n rows can be formed. Preferably, p-shield 90, n-line 95, p-line 94, n-drift region 78, and n-drift region 44 are completely depleted at the beginning of the collapse.

Figure 17 shows another embodiment similar to the embodiment of Figure 15, but with an L-shaped gate 70 to minimize overlap of the gate 70 and a field for lower gate-drain capacitance The board 72 is used to increase the switching speed.

Figure 18 shows a particular embodiment of Figure 17, but through different cross-sections, showing the area of field plate 72 electrically connected to source metal layer 60. In other embodiments, field plate 72 can be connected to gate 70 (which will increase capacitance), or float.

Figure 19 shows another embodiment similar to the embodiment of Figure 13, but with a p-connection region 100 electrically connecting p-shield region 90 to p-well 54 and source metal layer 60 for improved switching Speed.

As in these other embodiments, the vertical extension 76 of the gate 70 can extend any distance into the trench 30/40, including below the p-well 54.

In FIG. 20, the lateral gate polysilicon is connected to the polysilicon filling the trench 30/40, so that the trench poly is at 0 volts when the MOSFET is turned off, assuming that the gate is shorted to the source in the off state. Thus, the trench polysilicon acts as the field plate 72 in the off state, but facilitates along the on state due to the thin (tapered) oxide 36 in the trench close to the channel region. Electrons accumulate in the sidewalls of the trenches in the n-surface region 98. Since the voltage is much closer to the top of the trench 30/40, the thickness of the oxide 36 near the top of the trench 30/40 (opposite the p-well 54) can be much less than the thickness near the bottom of the trench. .

21 and 22 show a particular embodiment of a p-well 54 with a sidewall of the coupling trench 30/40 such that there is no surface of the n-drift region 78 directly below the gate 70. This element has a long composite transverse and vertical channel, with one portion of the channel being flat and the other being vertical. The horizontal and vertical portions of the gate 70 are used to invert the area in the p-well 54. This structure reduces the gate-drain capacitance and reduces the cell pitch while also reducing the specific on-resistance. The devices of Figures 21 and 22 have longer channel lengths without increasing the active area. These components can have shallow junction depths and provide low channel leakage current and low saturation current as well as a wide Safe Operating Area (SOA). The longer channel also reduces the gain of the parasitic NPN transistor to improve the durability of the component by preventing secondary collapse. Vertical field plate 72 may be connected to source metal layer 60 or to gate 70, or to float.

Figure 22 shows gate 70 with no overlap field plate 72 to reduce capacitance.

In other embodiments, the gates of the vertical MOSFETs can be trench gates, such as shown in FIG. 10, and a separate field plate 72 surrounds the cell, including the trench gate. The trench gate can be formed as a strip or as a closed gate. The trench gate will then reverse the vertical channel to conduct vertical current.

Figure 23A is a top plan view of two cells of a lateral MOSFET, and Figure 23B is a cross-sectional view of the MOSFET along line A-A of Figure 23A, showing a portion of a single cell. All monomers are connected in parallel. The MOSFET is modified from the MOSFET described in U.S. Patent No. 7,704,842 to Richard Blanchard, incorporated herein by reference. The prior art MOSFET is modified to have the tapered oxide.

In FIGS. 23A and 23B, the lateral MOSFET includes an n+ drain 102; an n-drift region 104; a p-body region 106; an n+ source region 108; and an isolation gate 110 overlying p- The region of the body region 106 reverses the region to create a conductive via; and the trench 108 includes a conductive polysilicon 111 extending along the n-drift region 104. A polysilicon 111 in the trench 108 is connected to the gate 110. The thermally grown oxides 112 are aligned along the trenches 108. The substrate 114 is p-type.

In one embodiment, a high voltage is applied to the n+ drain region 102, and the n+ source region 108 and the p-body region 106 are coupled to a low voltage, such as to one terminal of the load, wherein the other terminal of the load is grounded. . When the gate 110 is sufficiently positively biased, current flows between the n+ source region 108 and the n+ drain region 102 via the channel.

In the on state of the MOSFET, the positive bias polysilicon 111 in the trench 108 is concentrated along the wall area of the trench 108 in the drift region 104 to reduce the effective resistance of the drift region 104 to reduce the The overall on-resistance of the MOSFET.

When the MOSFET is turned off, for example, when the gate 110 and the polysilicon 111 are grounded, the grounded polysilicon 111 across the drain region 102 and near the drain region 102 has a high voltage. Accordingly, the oxide 112 along the trench 108 becomes thicker as the trench 108 approaches the drain 102 to withstand the high voltage. The oxide 112 can be made very thin near the source region 108. Thinner oxides more efficiently accumulate electrons along the drift region 104 and are therefore desirable.

The tapered oxide 112 is formed using a tilted nitrogen implant that results in a higher concentration of tantalum nitride to form closer to the source region 108. Such tilting may be with respect to the top surface of the wafer and relative to the direction of the trench 108 such that the implant is generally directed toward the left end of the trench 108. Multiple tilt angles or continuous tilt changes can be used.

Thus, a higher breakdown voltage is achieved with a thicker oxide 112, while efficiency and on-resistance are improved by the thinner oxide 112.

Any of the disclosed features can be combined in any combination of MOSFETs, IGBTs, or other vertical components to achieve these particular benefits of the feature for a particular application.

While the invention has been shown and described with reference to the embodiments of the present invention All such variations and modifications as fall within the true spirit and scope of the invention are intended to be embraced.

12‧‧‧n+bungee; bungee

14, 104‧‧‧n-drift zone; drift zone

16‧‧‧Rectangular trench; trench

18, 112‧‧‧ cone oxide; oxide

20‧‧‧ gate

22‧‧‧p-main body

24‧‧‧n+ source; source

25, 60‧‧‧ top source metal layer; source metal layer

26‧‧‧Oxide

30, 40, 40B‧‧

31‧‧‧ top surface

32‧‧‧ patterned mask

33‧‧‧Nitrogen implantation

34‧‧‧Nitrogen ions

36‧‧‧Cone oxide; oxide; thin (taper) oxide

40A‧‧‧Exposure trench; trench

42‧‧‧n+ substrate; substrate

44‧‧‧n-drift zone; drift zone; n-type layer

45‧‧‧ Thick oxide layer

46‧‧‧Thin oxide layer

47‧‧‧Light resistance

48, 49, 50, 51‧ ‧ oxide

52‧‧‧ Conductive doped polysilicon; polysilicon

54‧‧‧p-well; p-well

56, 74‧‧‧p+ contact area

58‧‧‧n+ source

61‧‧‧汲metal layer; bottom bungee metal layer

62‧‧‧ Field Board

63‧‧‧Oxide layer

64‧‧‧ gate

70‧‧‧transverse gate; gate; L-shaped gate

72‧‧‧ field plate; vertical field plate

76‧‧‧Vertical extension

78‧‧‧n-layer; n-drift zone; n-layer

80‧‧‧ dielectric

90‧‧‧Self-aligned p-shielded area; p-shielded area; p-shielded

94, 94A‧‧‧p charge balance line; p line; p-row

95, 95A‧‧‧n charge balance line; n lines; n-row

98‧‧‧ Self-aligned strengthened n-surface region (n-Surf); n-surface region

100‧‧‧p-connection area

102‧‧‧n+bungee; n+bungee zone; bungee zone; bungee

106‧‧‧p-body area

108‧‧‧n+ source region; trench; source region

110‧‧‧Isolation gate; gate

111‧‧‧ Conductive polysilicon; polysilicon

114‧‧‧Substrate

[Fig. 1] is a cross-sectional view of a portion of a vertical MOSFET reproduced from the Kobayashi paper. [Fig. 2] A cross-sectional view of a top portion of an epitaxial layer grown on a ruthenium substrate in which a trench having a tapered side surface is formed. The trench can ultimately be used for a gate or field plate. [Fig. 3] A trench is illustrated after a nitrogen ion implantation step and an annealing step (to form tantalum nitride), wherein the nitrogen dopant concentration gradually decreases with a depth entering the trench. The taper can be smooth or stepped. [Fig. 4] Illustrates a trench after the wafer is subjected to an oxidation step to grow an oxide along the walls of the trench, wherein the nitride suppresses oxide growth, thereby causing the oxide to be gradually thinned. [Fig. 5] Illustrates nitrogen (N ₂ ) ions implanted at an angle to achieve a tapered implant with respect to a vertical wall surface of a groove. [6] opposite angles illustrated in FIG. 7, the implant angle to the opposite tapered in such implanted nitrogen (N ₂₎ sidewall ions reached. These nitrogen doses may be the same or different than in Figure 5. [Fig. 7] A highly stepped but tapered oxide grown in the trenches of Figs. 5 and 6 is exemplified. Additional nitrogen implant angles can be used to increase the number of steps or to make the oxide smooth. [Fig. 8A] Illustrates the photoresist of the trench while masking nitrogen in another trench on the same substrate. [Fig. 8B] The substrate of Fig. 8A after the photoresist removal and after the oxidation step is illustrated, showing a decrease in oxide growth in the nitrogen-doped trench. [Fig. 9] A variation of the substrate of Fig. 8A is exemplified in which the nitrogen is implanted at a more extreme tilt angle, resulting in a thick bottom oxide referred to as a stepped oxide and a thinner higher oxide. [Fig. 10] is a cross-sectional view showing a specific embodiment of a vertical MOSFET or IGBT using the filled trench as a gate, wherein the trench includes a tapered oxide. [FIG. 11] is a cross-sectional view of a specific embodiment of a vertical MOSFET or IGBT that uses the filled trench as a gate near the top of the trench and uses the filled trench as a field plate near the bottom of the trench, wherein the gate is The pole portion and the field plate portion are separated by an oxide layer. [Fig. 12] to [Fig. 19], Fig. 21, and Fig. 22 are cross-sectional views of a MOSFET in which a lateral gate is used to control the current, and wherein a trench type field plate is used to shape the electric field to enhance the Crash voltage. The field plate can be connected to the source or to the gate, or floating. [Fig. 20] is a cross-sectional view of a MOSFET in which a lateral gate is mainly used to control the current, and wherein a trench-type vertical gate strengthens a vertical portion of the channel region to further control the current and reduce on-resistance. In this off state, the trench gate is used as a field plate. [Fig. 23A] is a plan view of a lateral MOSFET using a trench having a tapered oxide. [Fig. 23B] A cross-sectional view of the MOSFET of Fig. 23A along line AA.

Claims (23)

A method of forming a semiconductor device includes: providing a germanium-containing substrate having a top end surface; epitaxially growing at least one first layer on a top surface of the substrate; etching a first trench into the at least one layer first Between the layers and a first depth; implanting nitrogen ions into at least sidewalls of the first trench at a plurality of angles to generate a tapered nitrogen dopant concentration along the sidewalls; annealing the sidewalls to The sidewalls form a tapered thickness of tantalum nitride; the sidewalls are oxidized to form cerium oxide along the sidewalls, wherein a thickness of one of the cerium oxides variably inhibits growth of the cerium oxide The tapered thickness of the tantalum nitride is gradually thinned along the sidewalls; at least partially filling the first trench with a conductive material; forming a first electrode overlying the at least one first layer; and forming a a second electrode, wherein current is conducted between the first electrode and the second electrode when the element is turned on. The method of claim 1, wherein the tapered nitrogen dopant concentration comprises a stepped nitrogen dopant concentration that gradually fades along the sidewalls. The method of claim 1 wherein the tapered nitrogen dopant concentration comprises a substantially smooth nitrogen dopant concentration that gradually fades along the sidewalls. The method of claim 1, wherein the second electrode contacts a bottom surface of the substrate, and wherein the conductive material in the first trench forms a field plate in a vertical transistor. The method of claim 1, wherein the second electrode contacts a bottom surface of the substrate, and wherein the conductive material in the first trench forms a gate in a vertical transistor. The method of claim 1, wherein the second electrode contacts a bottom surface of the substrate, and wherein the conductive material in the first trench forms a field plate in a vertical transistor, and the field plate is electrically connected to The first electrode. The method of claim 1, wherein the second electrode contacts a bottom surface of the substrate, and wherein the conductive material in the first trench forms a field plate in a vertical transistor, and the field plate floats. The method of claim 1, wherein the second electrode contacts a bottom surface of the substrate, and wherein the conductive material in the first trench forms a field plate in a vertical transistor, and the field plate is electrically connected to A gate. The method of claim 1, wherein the step of implanting nitrogen ions comprises implanting nitrogen ions such that a nitrogen dopant concentration along the sidewalls is from a bottom of the first trench to the first trench One of the tops is raised to produce a tapered nitrogen dopant concentration, and wherein the step of oxidizing the sidewalls includes oxidizing the sidewalls such that the cerium oxide near the bottom of the trench is substantially closer to the trench The top cerium oxide is thicker. The method of claim 1, wherein the second electrode is formed by overlying the at least one first layer, and the component comprises a source region and a drain region of a short channel lateral MOSFET. a crystal (MOSFET), wherein the first trench is formed along a drift region between the source region and the drain region, wherein the step of implanting nitrogen ions comprises implanting nitrogen ions to The concentration of a nitrogen dopant of the sidewalls increases from immediately adjacent the source region to immediately adjacent the drain region to produce the tapered nitrogen dopant concentration, and wherein the step of oxidizing the sidewalls comprises oxidizing the sidewalls to The cerium oxide adjacent to the drain region is substantially thicker than the cerium oxide adjacent to the source region. The method of claim 10 further comprising forming a gate adjacent to a body region to generate a conductive path through the body region when the component is turned on, wherein the conductive material filling the first trench is electrically connected to the gate a pole to accumulate carriers along the drift region to reduce on-resistance when the component is turned "on". The method of claim 1, wherein the first trench has a sloped sidewall. The method of claim 1 wherein the first trench has substantially parallel sidewalls. The method of claim 1 further comprising: etching a second trench into the at least one first layer; implanting nitrogen ions into at least sidewalls of the second trench such that the second trench is along the second trench A concentration of a nitrogen dopant of the sidewalls of the trench is raised from a bottom of one of the second trenches to a top of the second trench to produce a tapered nitrogen dopant concentration; The sidewalls are annealed to form a tapered thickness of tantalum nitride along the sidewalls; the sidewalls of the second trench are oxidized to form cerium oxide along the sidewalls, wherein the cerium oxide a thickness gradually thinning along the sidewalls of the second trench such that the cerium oxide near the bottom of the second trench is substantially thicker than the cerium oxide near the top of the second trench; The second trench is at least partially filled with the conductive material; wherein the conductive material in the first trench forms a gate of a vertical transistor, and the conductive material in the second trench forms a field plate. The method of claim 1, wherein the step of at least partially filling the first trench with the conductive material comprises: partially filling the first trench with the conductive material to form a first conductive material portion; Forming cerium oxide on the first conductive material portion; and filling the first trench with the conductive material to form a second conductive material portion isolated from the first conductive portion, wherein the second conductive material portion is formed And a gate of a vertical transistor, and the first conductive material portion forms a field plate. The method of claim 1, wherein the at least one first layer has a first conductivity type, the method further comprising: forming a well region having a second conductivity type in the at least one first layer; Forming a first region having the first conductivity type in the well region, wherein a channel region is formed between an edge of the first region and an edge of the well region, wherein the semiconductor component is a vertical transistor . The method of claim 1, wherein the conductive material at least partially filling the first trench is a gate that is electrically biased to cause a current to flow between the first electrode and the second electrode Reverse an area. The method of claim 1, wherein the substrate is defective. The method of claim 1, wherein the cerium carbide (SiC) is used. A semiconductor device comprising: a germanium-containing substrate having a top end surface; at least one first layer epitaxially grown on a top surface of the substrate; a first trench etched into the at least one first layer Up to a first depth, the first trench has sidewalls, the sidewalls comprising a tapered tantalum nitride layer, the sidewalls being deformed by a tapered tantalum nitride layer that variably inhibits growth of the ceria layer Further comprising a tapered cerium oxide layer; a conductive material at least partially filling the first trench; a first electrode overlying the at least one first layer; and a second electrode, wherein the current is The element is conducted between the first electrode and the second electrode when the element is turned on. The element of claim 20, wherein the electrically conductive material forms a vertical gate of a vertical transistor. The element of claim 20, wherein the electrically conductive material forms a field plate of a vertical transistor. The element of claim 20, wherein a thickness of one of the tantalum nitride layers along the sidewalls is thicker near a top of one of the first trenches, and a bottom portion of the first trench is thinner, and wherein The thickness of one of the ceria layers along the sidewalls is substantially close to the bottom of one of the first trenches due to the thickness of the tapered tantalum nitride layer that variably inhibits the growth of the ceria layer, and is close to the The top of the trench is thinner.