TWI746007B - Power device - Google Patents

Abstract

Provided is a power device including an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; an isolated-field plate in the trench; an insulating filling layer located in the trench, surrounding the sidewalls and bottom of a lower part of the isolation field plate; a first gate electrode and a second gate electrode located in the trench and on the insulating filling layer; and a dielectric layer surrounds sidewalls of the first gate electrode and the second gate electrode, wherein a lower portion of the dielectric layer has a maximum width of the dielectric layer, and the isolation field plate includes a first portion and a second portion, the first portion is adjacent to the lower portion of the dielectric layer, and a doping concentration of the lower portion is greater than that of the second portion.

Description

Power components

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power device and a manufacturing method thereof.

Power MOSFET is a voltage-type control element. Its driving circuit is simple, the driving power is high, the switching speed is fast, and it has a high operating frequency. It is a switching element widely used in various electronic application components.

The trench gate MOSFET is a power MOSFET in which the gate is buried in the substrate or the epitaxial layer to make it have a vertical channel. This kind of power metal oxide half field effect transistor has a small cell size and small on-resistance, and is suitable for medium and low voltage power MOSFETs.

The Split Gate Trench (SGT) MOSFET is a power MOSFET in which a single gate is split into two gates, and the two gates are separated by an isolation field plate. The isolation field plate deep in the epitaxial layer can increase the lateral depletion and increase the N-drift doping concentration. Isolating the field plate can also reduce the overlap of the gate and the drain, so it can reduce the gate-to-drain capacitance. Therefore, the structure has excellent performance in both static and dynamic characteristics.

However, due to the complicated manufacturing process of the SGT MOSFET, leakage current is likely to occur between the gate electrode and the isolation field plate, so that the breakdown voltage of the device is insufficient. On the other hand, if the doping concentration of the epitaxial layer is reduced in order to reduce the leakage current between the gate and the isolation field plate, the on-resistance (Ron) will increase and the gate charge (QG) will increase. And affect the performance of the component.

The present invention proposes a power element that can reduce the leakage current between the gate and the isolation field plate, increase the breakdown voltage of the element, reduce the on-resistance, reduce the gate charge (QG), and improve the figure of merit (FOM), Improve the performance of components.

A power device according to an embodiment of the present invention includes a power device, including: an epitaxial layer having trenches extending from a first surface to a second surface of the epitaxial layer; and a drain doped layer located on the epitaxial layer On the second surface of the crystal layer; a first body region and a second body region located in the epitaxial layer on both sides of the trench; a first source doped region and a second source doped region, Are respectively located in the first base region and the second base region; an isolation field plate is located in the trench; an insulating filling layer is located in the trench and surrounds the sidewall and bottom of the lower part of the isolation field plate; The first gate and the second gate are located in the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the second Two gates are located between the isolation field plate and the second base region; and a dielectric layer surrounds the sidewalls of the first gate and the second gate, wherein the lower part of the dielectric layer has The maximum width of the dielectric layer, and wherein the isolation field plate includes a first portion and a second portion, the first portion is adjacent to the lower portion of the dielectric layer, and the doping concentration of the first portion is greater than that of the second portion .

Based on the above, there is a sufficiently thick oxide layer at the bottom corner of the gate trench, so that the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the device can be increased. Under the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality factor (FOM), and enhance the performance of the device.

1A to 1J are schematic cross-sectional views of a method of manufacturing a power device according to a first embodiment of the present invention. The power element is, for example, SGT MOSFET.

1A, the manufacturing method of the power device includes forming the drain doped layer 12 in the substrate 10. The substrate 10 may be a semiconductor substrate 10, such as a silicon substrate. The drain doped layer 12 may be formed by an in-situ doping process during wafer manufacturing. The drain doped layer 12 has first conductivity type dopants. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. Next, an epitaxial layer 14 is formed on the drain doped layer 12. The method for forming the epitaxial layer 14 is, for example, a selective epitaxial growth process. The epitaxial layer 14 has dopants of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the epitaxial layer 14 is, for example, lower than the doping concentration of the drain doped layer 12. The dopants of the epitaxial layer 14 may be formed in-situ during the selective epitaxial growth process, or may be formed by an ion implantation process after the selective epitaxial growth process is performed.

Thereafter, trenches 16 are formed in the epitaxial layer 14. The trench 16 extends from the first surface 14a to the second surface 14b of the epitaxial layer 14. The trench 16 can be formed by lithography and etching processes. The etching process may be an anisotropic etching process, an isotropic etching process, or a combination thereof. After that, an insulating filling layer 18 and a conductive layer 20 are formed on the epitaxial layer 14 and in the trench 16. The material of the insulating filling layer 18 is, for example, silicon oxide, silicon nitride, or a combination thereof formed by chemical vapor deposition. The conductor layer 20 is formed on the insulating filling layer 18 and fills the remaining space of the trench 16. The conductive layer 20 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by a chemical vapor deposition method.

1B, the conductive layer 20 is etched back to remove the conductive layer 20 other than the trench 16 to leave the conductive layer 20a in the trench 16. In some embodiments, the top surface of the conductive layer 20 a is lower than the top surface of the epitaxial layer 14.

1C, a doped layer (or doped region) 20b is formed on or in the conductive layer 20a. The doped layer/doped region 20b and the conductive layer 20a have dopants of the same conductivity type, for example, dopants of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped layer/doped region 20b is, for example, higher than the doping concentration of the conductive layer 20a. In some embodiments, the doping concentration of the doped layer/doped region 20b ranges from 5E18 1/cm ³ to 5E20 1/cm ³ . The thickness/depth of the doped layer/doped region 20b greater than 1500 angstroms can facilitate the control of the subsequent etching process for forming the gate trench. The thickness/depth range of the doped layer/doped region 20b is, for example, 1600 angstroms to 2500 angstroms.

In one embodiment, the doped region 20b is located in the conductive layer 20a. The method for forming the doped region 20b is, for example, performing an ion implantation process IMP 1 on the conductor layer 20a. The IMP 1 ion implantation process implants dopants into the conductive layer 20a in a manner perpendicular to the surface of the substrate 10. In another embodiment, the doped layer 20b is located on the conductive layer 20a. The formation method of the doped layer 20b is, for example, after the conductive layer 20a is formed, a chemical vapor deposition process is performed in situ to form the doped layer 20b on the conductive layer 20a with a concentration greater than that of the conductive layer 20a.

After that, referring to FIG. 1D, a conductive layer 20c is formed on the doped layer/doped region 20b. The method for forming the conductive layer 20c is, for example, after forming a conductive layer on the insulating filling layer 18 and the doped layer/doped region 20b, and then performing an etch-back process to remove the conductive layer other than the trench 16. The conductive layer 20c may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by a chemical vapor deposition method. The top surface of the conductive layer 20c may be coplanar with the first surface 14a of the epitaxial layer 14 or lower than the first surface 14a of the epitaxial layer 14.

Thereafter, referring to FIG. 1E, an etch-back process is performed on the insulating filling layer 18 to remove the insulating filling layer 18 other than the trench 16, so as to leave the insulating filling layer 18 a in the trench 16. The insulating filling layer 18a surrounds the sidewalls and the bottom surface of the conductor layer 20a, and surrounds part of the sidewalls of the doped layer/doped region 20b, and the top surface of the insulating filling layer 18a is between the top surface and the bottom surface of the doped region 20b. In other words, the insulating filling layer 18 a has a first gate trench 22 and a second gate trench 24. The sidewalls of the first gate trench 22 and the second gate trench 24 expose the epitaxial layer 14, the conductor layer 20c and a part of the doped region 20b, and the first gate trench 22 and the second gate trench The bottom surface of 24 exposes the top surface of the insulating filling layer 18a. The etch-back process is, for example, an anisotropic etching process, an isotropic etching process, or a combination.

1F, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductor layer 20c and in the first gate trench 22 and the second gate trench 24. The dielectric layer 30 may be silicon oxide formed by a thermal oxidation method or a chemical vapor deposition method. In some embodiments where the dielectric layer 30 is a silicon oxide layer formed by a thermal oxidation method, the doping concentration of the doped region 20b is greater than the doping concentration of the epitaxial layer 14. Compared with the epitaxial layer 14, the doped region 20b is easier to oxidize. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20 b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the epitaxial layer 14. In addition, since the doping concentration of the doped region 20b is greater than the doping concentration of the conductive layer 20c, the doped region 20b is easier to oxidize compared to the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the doped region 20b is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20c. Narrated.

1G, a conductive layer 31 is formed on the dielectric layer 30. The conductor layer 31 fills up the remaining space of the first gate trench 22 and the second gate trench 24. The conductive layer 31 may be a semiconductor material, for example, doped polysilicon formed by a chemical vapor deposition method.

1H, the conductive layer 31 is etched back to remove the conductive layer 31 other than the first gate trench 22 and the second gate trench 24, so that the first gate trench 22 and the second gate trench A first gate 32 and a second gate 34 are formed in the trench 24. The top surfaces of the first gate electrode 32 and the second gate electrode 34 may be coplanar with the first surface 14 a of the epitaxial layer 14 or lower than the first surface 14 a of the epitaxial layer 14.

Please continue to refer to FIG. 1H, a first base region 36 and a second base region 38 are formed in the epitaxial layer 14 on both sides of the trench 16. The first body region 36 and the second body region 38 extend from the first surface 14a to the second surface 14b of the epitaxial layer 14. The first body region 36 and the second body region 38 have second conductivity type dopants, such as P-type dopants. The P-type dopant is, for example, boron or boron trifluoride. The formation method of the first base region 36 and the second base region 38 is, for example, an ion implantation method. In another embodiment, the first body region 36 and the second body region 38 may be formed before the trench 16 is formed. For example, the first body region 36 and the second body region 38 can be formed in-situ during the selective epitaxial growth process of forming the epitaxial layer 14, or after the selective epitaxial growth process is performed Then it is formed by ion implantation process.

Next, a first source doped region 42 and a second source doped region 44 are formed in the first body region 36 and the second body region 38, respectively. The first source doped region 42 and the second source doped region 44. It has a first conductivity type dopant, for example, an N-type dopant. N-type dopants, such as phosphorus or arsenic. The formation method of the first source doped region 42 and the second source doped region 44 is, for example, an ion implantation method.

1I, a dielectric layer 46 is formed on the epitaxial layer 14 to cover the first source doped region 42, the second source doped region 44, the first gate 32, the second gate 34, and the dielectric Electric layer 30. The dielectric layer 46 is, for example, borophosphosilicate glass (BPSG) formed by chemical vapor deposition, silicon oxide, silicon nitride, or a combination thereof. Next, a lithography and etching process is performed to form a first contact window opening 52 and a second contact window opening 54 in the dielectric layer 46 to expose the first source doped region 42 and the second source doped region, respectively 44. Thereafter, a first doped region 62 and a second doped region 64 are formed in the first body region 36 and the second body region 38, respectively. The first doped region 62 and the second doped region 64 have second conductivity type dopants. The second conductivity type dopant may be a P type dopant, such as boron or boron trifluoride. The formation method of the first doped region 62 and the second doped region 64 is, for example, an ion implantation method.

1J, after that, a first contact 72 contacting the first doped region 62 and a second contact 72 contacting the second doped region 64 are formed in the first contact opening 52 and the second contact opening 54 respectively. The contact window 74, and the first contact window 72 and the second contact window 74 are electrically connected to each other. After that, the subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate electrode 32 and the second gate electrode 34.

1J, in this embodiment, the conductive layer 20a, the doped layer/doped region 20b, and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolation field plate PL can uniform the electric field distribution of the epitaxial layer 14 under the first p-body region 36 and the second p-body region 38, so that the peak electric field intensity is reduced, and therefore the breakdown voltage can be increased. On the other hand, under the same breakdown voltage, the doping concentration of the epitaxial layer 14 can be increased to reduce the on-resistance (Ron).

In addition, in this embodiment, the isolation field plate PL includes a first part P1 and a second part P2. The doped layer/doped region 20b is the first part P1 of the isolation field plate PL; the conductor layer 20a and the conductor layer 20c can be collectively referred to as the second part P2 of the isolation field plate PL. The first part P1 is sandwiched in the second part P2, and the doping concentration of the first part P1 is greater than the doping concentration of the second part P2.

Since the first portion P1 of the isolation field plate PL having a higher concentration in this embodiment is exposed by the first gate trench 22 and the second gate trench 24, and the first gate trench 22 and the second gate trench The bottom of the groove 24 is higher than the bottom of the first part P1 (as shown in FIG. 1E). Therefore, during the subsequent thermal oxidation process for forming the dielectric layer 30, the first portion P1 having a higher concentration contributes to the formation of a thicker silicon oxide layer, and therefore, more of the first portion P1 is oxidized. Therefore, after the dielectric layer 30 is formed, in the isolation field plate PL with the horizontal height between the top and bottom surfaces of the first gate trench 22 and the second gate trench 24, the first portion P1 has the narrowest width , As shown in Figure 1F and Figure 2.

Fig. 2 shows an enlarged schematic diagram of the area R in Fig. 1J. Please refer to FIG. 2, the dielectric layer 30 between the epitaxial layer 14 and the first gate electrode 32 is referred to as the first gate dielectric layer 30 a. The dielectric layer 30 between the epitaxial layer 14 and the second gate electrode 34 is referred to as the second gate dielectric layer 30b. The dielectric layer 30 between the isolation field plate PL and the first gate electrode 32 is referred to as a first insulating layer 30c. The dielectric layer 30 between the isolation field plate PL and the second gate electrode 34 is referred to as a second insulating layer 30d.

The first portion P1 (doped layer/doped region 20b) of the isolation field plate PL is adjacent to and in contact with the first insulating layer 30c and the lower portion 30L of the second insulating layer 30d. In the isolation field plate PL, the second portion P2 (conductor layer 20c) above the first portion P1 is adjacent to and in contact with the first insulating layer 30c and the upper portion 30U of the second insulating layer 30d.

Since the first portion P1 having a higher concentration helps to form a thicker silicon oxide layer, the lower portion 30L of the first insulating layer 30c and the second insulating layer 30d is formed by the first insulating layer 30c and the second insulating layer 30d. _{Where the} maximum thicknesses are T _{max1 and} T _max2 . In addition, although the first insulating layer 30c and the second insulating layer 30d between the bottom surface of the first gate 32 and the first portion P1 (doped layer/doped region 20b) of the isolation field plate PL have the minimum thickness T _min1 , T _min2 , however, _{the ratio of the minimum thickness T min1} to the average thickness of the first insulating layer 30c, and the ratio of the minimum thickness T _min2 to the average thickness of the second insulating layer 30d are still greater than 0.8. In one embodiment, the average thickness of the first insulating layer 30c and the second insulating layer 30d is about 900 angstroms, the maximum thickness T _{max1 and} T _max2 of the lower part 30L is about 1600 angstroms, and the minimum thickness T _min1 , T min1 and T of the lower part 30L _min2 is about 800 angstroms.

Since the lower portion 30L of the dielectric layer 30 (the first insulating layer 30c and the second insulating layer 30d) in contact with the first gate electrode 32 and the second gate electrode 34 has a relatively thick and sufficiently thick thickness, the first The leakage current between the gate 32 and the isolation field plate PL and between the second gate 34 and the isolation field plate PL increases the breakdown voltage of the device.

3A to 3E are schematic cross-sectional views of a method of manufacturing a power device according to a second embodiment of the present invention.

3A, according to the method described in the first embodiment, after the conductive layer 20a is formed in the trench 16, two doped regions 20b' are formed in the conductive layer 20a. The doped region 20b' is formed in the edge region of the conductive layer 20a, and the central region of the conductive layer 20a is not formed with the doped region 20b'. The doped region 20b' and the conductive layer 20a have dopants of the same conductivity type, for example, dopants of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the doped region 20b' is higher than the doping concentration of the conductive layer 20a. In some embodiments, the doping concentration of the doped region 20b' ranges from 5E18 1/cm ³ to 5E20 1/cm ³ . The formation method of the doped region 20b' is, for example, performing the inclined ion implantation process IMP 2 on the conductor layer 20a. The angle θ between the inclined ion implantation process IMP 2 and the normal direction of the surface of the substrate 10 ranges from 30 degrees to 60 degrees, for example.

Thereafter, referring to FIG. 3B, a conductive layer 20c is formed on the conductive layer 20a and the doped region 20b' according to the method described in the first embodiment above. In this embodiment, the conductive layer 20a, the doped region 20b', and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolation field plate PL. The isolation field plate PL may include a first part P1 and a second part P2. The first part P1 includes two separate doped regions 20b' that are not connected. The second part P2 includes a conductive layer 20a and a conductive layer 20c connected to each other, and separates the two doped regions 20b' from each other. The doping concentration of the first part P1 is greater than the doping concentration of the second part P2.

3C, according to the method described in the first embodiment, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16 and forming a second insulating filling layer 18a on the insulating filling layer 18a. A gate trench 22 and a second gate trench 24. The height of the bottom surface of the first gate trench 22 and the second gate trench 24 is between the top surface and the bottom surface of the two doped regions 20b'.

Thereafter, referring to FIG. 3D, according to the method described in the first embodiment above, a dielectric is formed on the epitaxial layer 14 and the conductor layer 20c, and in the first gate trench 22 and the second gate trench 24. Layer 30. Similarly, since the doping concentration of the doped region 20b' is greater than the doping concentration of the conductive layer 20c and greater than the doping concentration of the epitaxial layer 14, compared to the conductive layer 20c and the epitaxial layer 14, the doped region 20b' is higher. Easy to oxidize. Therefore, the thickness of the dielectric layer 30 formed on the surface of the doped region 20b' is greater than the thickness of the dielectric layer 30 formed on the surface of the conductive layer 20c, and the dielectric layer 30 formed on the surface of the conductive layer 20c The thickness of is greater than the thickness of the dielectric layer 30 formed on the surface of the epitaxial layer 14.

After that, referring to FIG. 3E, the subsequent manufacturing process is performed according to the method described in the above first embodiment until the first contact window 72 and the second contact window 74 are formed. After that, the subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate electrode 32 and the second gate electrode 34.

4A to 4E are schematic cross-sectional views of a method of manufacturing a power device according to a third embodiment of the present invention.

4A, according to the method of forming the conductive layer 20a described in the first embodiment, the conductive layer 20a' is formed in the trench 16. However, in this embodiment, the conductive layer 20a' is doped polysilicon with a higher concentration. In an embodiment, the doping concentration of the conductive layer 20a' ranges from 1E19 1/cm ³ to 5E20 1/cm ³ .

After that, a mask layer 19 is formed on the surface of the edge region of the conductor layer 20a'. The mask layer 19 exposes the surface of the central area of the conductor layer 20a'. The mask layer 19 may be a patterned photoresist layer, which covers the surface and sidewalls of the insulating filling layer 19 and the surface of the edge region of the conductor layer 20a'. The mask layer 19 has an opening, which exposes the surface of the central area of the conductor layer 20a'. The mask layer 19 may also be a spacer, which only covers the sidewall of the insulating filling layer 19 and the surface of the edge area of the conductor layer 20a'. The material of the spacer can be silicon oxide, silicon nitride or a combination thereof. The method for forming the spacer can be to form the spacer material layer first, and then perform an anisotropic etching process.

The conductive layer 20a' is subjected to the ion implantation process IMP 3 to form a doped region 20d in the conductive layer 20a'. The doped region 20d and the conductive layer 20a' may have dopants of the same or different conductivity types.

In an embodiment where the doped region 20d and the conductive layer 20a' have dopants of the same conductivity type, the doping concentration of the doped region 20d is lower than the doping concentration of the conductive layer 20a'. The doped region 20d can be implanted into the conductive layer 20a' by the ion implantation process IMP 3 in a manner perpendicular to the surface of the substrate 10. The ion implantation process IMP 3 is, for example, implanting a second conductivity type dopant different from the first conductivity type dopant of the conductive layer 20a' into the conductive layer 20a', and the dopants compensate each other to make the formed The doping concentration of the doped region 20d is lower than the doping concentration of the conductor layer 20a'. The second conductivity type dopant is a P type dopant, such as boron or boron trifluoride. The doping concentration of the doping region 20d ranges from 5E18 1/cm ³ to 1E20 1/cm ³ .

In an embodiment where the doped region 20d and the conductor layer 20a' have dopants of different conductivity types, the ion implantation process IMP 3 can be used to implant the dopants into the conductor layer 20a' in a manner perpendicular to the surface of the substrate 10 Among them, a doped region 20d is formed. The ion implantation process IMP 3 is, for example, implanting a second conductivity type dopant that is different from the first conductivity type dopant of the conductive layer 20a' and has a higher doping concentration than the conductive layer 20a' into the conductive layer 20a', by The dopants compensate each other so that the conductivity type of the dopants of the formed doped region 20d is different from the conductivity type of the dopants of the conductor layer 20a'. The second conductivity type dopant is a P type dopant, such as boron or boron trifluoride. The doping region 20d has conductivity type dopants, and the doping concentration range is, for example, 5E19 1/cm ³ to 8E20 1/cm ³ .

Please refer to FIG. 4B to remove the mask layer 19. The mask layer 19 can be removed by an ashing method or an etching method. After that, according to the method described in the first embodiment, a conductive layer 20c is formed on the doped region 20d and the conductive layer 20a'. In this embodiment, the conductive layer 20a', the doped region 20d, and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolation field plate PL.

The isolation field plate PL may include a first part P1, a second part P2, and a third part P3. The doping concentration of the first part P1 is greater than the doping concentration of the second part P2, and is greater than the doping concentration of the third part P3. The first part P1 includes the conductor layer 20a'; the second part P2 includes the doped region 20d; and the third part includes the conductor layer 20c. The sidewalls and bottom of the second part P2 are surrounded by the first part P1, and the third part P3 covers the top surfaces of the first part P1 and the second part P2.

4C, according to the method described in the first embodiment above, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16 and forming a second insulating filling layer 18a on the insulating filling layer 18a. A gate trench 22 and a second gate trench 24. The height of the bottom surface of the first gate trench 22 and the second gate trench 24 is lower than the top surface of the conductor layer 20a', so that the sidewalls of the first gate trench 22 and the second gate trench 24 are exposed The conductor layer 20c and part of the conductor layer 20a'.

Thereafter, referring to FIG. 4D, according to the method described in the first embodiment above, a dielectric is formed on the epitaxial layer 14 and the conductor layer 20c, and in the first gate trench 22 and the second gate trench 24. Layer 30. Since the doping concentration of the conductive layer 20a' is greater than the doping concentration of the conductive layer 20c, the conductive layer 20a' is easier to oxidize compared to the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductive layer 20a' is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductive layer 20c. The doping of the doped region 20d is less likely to be oxidized than the conductive layer 20a'. Therefore, the isolation field plate PL can maintain a sufficient width to prevent the conductive layer 20a' from being over-oxidized and becoming too thin, resulting in too high resistance. The characteristics of power components. In addition, it can also be ensured that the dielectric layers on the left and right sides are not connected to each other due to excessive oxidation of the conductor layer 20a'. If the dielectric layers (oxide layers) 30 on the left and right sides are connected, the isolation field plate PL will be disconnected.

After that, referring to FIG. 4E, the subsequent manufacturing process is performed according to the method described in the first embodiment above until the first contact window 72 and the second contact window 74 are formed. After that, the subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate electrode 32 and the second gate electrode 34.

5A to 5D are schematic cross-sectional views of a method of manufacturing a power device according to a fourth embodiment of the present invention.

Referring to FIG. 5A, according to the method for forming the conductive layer 20a described in the first embodiment, a conductive layer 20a' is formed in the trench 16. However, in this embodiment, the conductive layer 20a' is doped with a higher concentration. Of polysilicon. In one embodiment, the doping concentration of the conductive layer 20a' ranges from 5E19 1/cm ³ to 8E20 1/cm ³ .

After that, the conductor layer 20c is formed on the conductor layer 20a' according to the method described in the above-mentioned first embodiment. The conductive layer 20c and the conductive layer 20a' have dopants of the same conductivity type, for example, dopants of the first conductivity type. The doping concentration of the conductor layer 20c is lower than the doping concentration of the conductor layer 20a'. The method for forming the conductive layer 20c is, for example, after the conductive layer 20a' is formed, a chemical vapor deposition process is performed in situ, but the concentration of the doped gas is reduced to form a lower concentration on the conductive layer 20a' than the conductive layer 20a'的 Conductor layer 20c. The doping concentration of the conductive layer 20c is, for example, 2/3 to 1/2 of the doping concentration of the conductive layer 20a'.

In this embodiment, the conductive layer 20a' and the conductive layer 20c can be collectively referred to as a source polysilicon layer or an isolation field plate PL. The conductor layer 20a' is the first part P1 of the isolation field plate PL; the conductor layer 20c is the second part P2 of the isolation field plate PL. The doping concentration of the first part P1 is greater than the doping concentration of the second part P2. The second part P2 covers the top surface of the first part P1.

5B, according to the method described in the first embodiment, the insulating filling layer 18 is etched back to leave the insulating filling layer 18a in the trench 16 and forming a first gate on the insulating filling layer 18a The pole trench 22 and the second gate trench 24. The height of the bottom surface of the first gate trench 22 and the second gate trench 24 is lower than the top surface of the conductor layer 20a', so that the sidewalls of the first gate trench 22 and the second gate trench 24 are exposed The conductor layer 20c and part of the conductor layer 20a'.

5C, according to the method described in the first embodiment, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20c and in the first gate trench 22 and the second gate trench 24. Since the doping concentration of the conductive layer 20a' is greater than the doping concentration of the conductive layer 20c, the conductive layer 20a' is easier to oxidize compared to the conductive layer 20c. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductive layer 20a' is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductive layer 20c.

After that, referring to FIG. 5D, the subsequent manufacturing process is performed according to the method described in the above first embodiment until the first contact window 72 and the second contact window 74 are formed. After that, the subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate electrode 32 and the second gate electrode 34.

The above Figures 1J, 3E, 4E, and 5D respectively depict a unit of the SGT MOSFET. However, the present invention is not limited to this. In some embodiments, the SGT MOSFET may have two cells C1 and C1', as shown in FIG. 6. In FIG. 6, the unit of FIG. 1J is taken as an example for illustration, but the present invention is not limited to this. The component symbols of the similar or identical components in the units C1' and C1 are represented by the same numbers, and "'" and "'" are added after the numbers. For example, the second doped region 64' is similar to the second doped region 64, and both have dopants of the second conductivity type.

The cells C1 and C1' are adjacent to each other, and the first base region 36 and the first doped region 62 are shared by the cells C1 and C1'. In addition, the first doped region 62, the second doped region 64, and the second doped region 64' are electrically connected to each other through the first contact window 72 and the second contact windows 74, 74'. The first gate 32 and the second gate 34 of the cell C1 and the first gate 32' and the second gate 34' of the cell C1' may be electrically connected to each other.

In other embodiments, the SGT MOSFET may have more cells, and these cells may be arranged in an array. In other words, the SGT MOSFET may have multiple gates, multiple source doped regions, and multiple drain doped regions. These multiple gates, multiple sources, and multiple drains can be respectively arranged in an array, and these multiple gates, multiple source doped regions, and multiple drain doped regions can be respectively arranged by Interconnected and connected together to form a gate terminal point, a source terminal point and a drain terminal point

In summary, the present invention exposes an isolation field plate with a high doping concentration on the bottom sidewall of the gate trench. Therefore, a thick oxide layer can be formed at the bottom corners of the gate trench, so that the gate and the gate can be reduced. The leakage current between the sources increases the breakdown voltage of the device. Under the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the figure of merit (FOM), and improve The performance of the component.

10: substrate 12: drain doped layer 14: epitaxial layer 14a: first surface 14b: second surface 16: trench 18, 18a: insulating filling layer 20, 20a, 20a', 20c, 31: conductor layer 20b: Doped layer, doped regions 20b', 20d: doped region 22: first gate trench 24: second gate trench 30, 46: dielectric layer 30a: first gate dielectric layer 30b: second Gate dielectric layer 30c: first insulating layer 30d: second insulating layer 30L: lower part 30U: upper part 32, 32': first gate 34, 34': second gate 36: first base region 38: second Body region 42: first source doping region 44: second source doping region 52: first contact window opening 54: second contact window opening 62: first doping region 64, 64': second doping Zone 72: first contact window 74, 74': second contact window C1, C1': unit PL: isolation field plate P1: first part P2: second part P3: third part IMP 1, IMP 2, IMP3: ion Implantation process T _min1 , T _min2 : minimum thickness T _{max1 ,} T _max2 : maximum thickness α1, α2, β1, β2: bottom angle θ: included angle

1A to 1J are schematic cross-sectional views of a method of manufacturing a power device according to a first embodiment of the present invention. Fig. 2 is an enlarged schematic diagram of area R in Fig. 1J. 3A to 3E are schematic cross-sectional views of a method of manufacturing a power device according to a second embodiment of the present invention. 4A to 4E are schematic cross-sectional views of a method of manufacturing a power device according to a third embodiment of the present invention. 5A to 5D are schematic cross-sectional views of a method of manufacturing a power device according to a fourth embodiment of the present invention. FIG. 6 is a schematic cross-sectional view showing two units of the power device.

10: Base

12: Drain doped layer

14: epitaxial layer

14a: first surface

14b: second surface

16: trench

18a: Insulating filling layer

20a, 20c: conductor layer

20b: doped layer, doped area

22: The first gate trench

24: The second gate trench

30: Dielectric layer

PL: Isolated field board

P1: Part One

P2: Part Two

Claims (10)

A semiconductor component, including: An epitaxial layer having trenches extending from the first surface to the second surface of the epitaxial layer; A drain doped layer located on the second surface of the epitaxial layer; The first body region and the second body region are located in the epitaxial layer on both sides of the trench; The first source doped region and the second source doped region are respectively located in the first body region and the second body region; Isolation field board, located in the ditch; An insulating filling layer, located in the trench, surrounding the sidewall and bottom of the lower part of the isolation field plate; The first gate and the second gate are located in the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the second Two gates are located between the isolation field plate and the second base region; and A dielectric layer surrounds the sidewalls of the first gate and the second gate, wherein the lower part of the dielectric layer has the maximum width of the dielectric layer, and The isolation field plate includes a first part and a second part, the first part is adjacent to the lower part of the dielectric layer, and the doping concentration of the first part is greater than that of the second part. The semiconductor element according to claim 1, wherein the first part is a doped layer and is sandwiched in the second part. The semiconductor element according to claim 1, wherein the first part includes two unconnected doped regions separated by the second part. The semiconductor device according to claim 1, wherein the isolation field plate further includes a third part whose doping concentration is lower than that of the first part and covers the top surfaces of the first part and the second part, and The side walls and the bottom of the second part are surrounded by the first part. The semiconductor element according to claim 1, wherein the second part is located on the first part and covers the top surface of the first part. The semiconductor element according to claim 1, wherein the bottom surface of the first portion is higher than the bottom surface of the dielectric layer. The semiconductor device according to claim 1, wherein the top surface of the first portion is higher than the bottom surface of the dielectric layer. The semiconductor device according to claim 1, wherein the maximum width of the dielectric layer is greater than the average width of the dielectric layer. The semiconductor element according to claim 1, wherein the isolation field plate has a minimum width of the dielectric layer at a position corresponding to the lower portion of the dielectric layer. The semiconductor element according to claim 9, wherein the ratio of the minimum width of the dielectric layer to the average width of the dielectric layer is 0.8 or more.

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