TWI731714B - Power device and method of fabricating the same - Google Patents

Abstract

Provided is a power device including an epitaxial layer having a trench extending from a first surface to a second surface of the epitaxial layer; a drain doped layer on the second surface of the epitaxial layer; a first body region and a second body region in the epitaxial layers besides of the trench; a first source doped region and a second source doped region in the first body region and the second body region; an isolated-field plate in the trench; an insulating filling layer in the trench and surrounding a lower sidewall and a bottom of the isolated-field plate; a first gate and a second gate in the trench and on the insulating filling layer; and a dielectric layer surrounding sidewalls of the first gate and the second gate, wherein bottom angles of the first gate and the second gate are obtuse angles.

Description

Power element and its manufacturing method

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a power device and a manufacturing method thereof.

Power MOSFET is a voltage-type control element. Its driving circuit is simple, the driving power is high, the switching speed is fast, and it has a high operating frequency. It is a switching element widely used in various electronic application components.

The trench gate MOSFET is a power MOSFET in which the gate is buried in the substrate or the epitaxial layer to make it have a vertical channel. This kind of power metal oxide half field effect transistor has a small cell size and small on-resistance, and is suitable for medium and low voltage power MOSFETs.

The Split Gate Trench (SGT) MOSFET is a power MOSFET in which a single gate is split into two gates, and the two gates are separated by an isolation field plate. The isolation field plate deep in the epitaxial layer can increase the lateral depletion and increase the N-drift doping concentration. Isolating the field plate can also reduce the overlap of the gate and the drain, so it can reduce the gate-to-drain capacitance. Therefore, the structure has excellent performance in both static and dynamic characteristics.

However, due to the complicated manufacturing process of the SGT MOSFET, leakage current is likely to occur between the gate electrode and the isolation field plate, so that the breakdown voltage of the device is insufficient. On the other hand, if the doping concentration of the epitaxial layer is reduced in order to reduce the leakage current between the gate and the isolation field plate, the on-resistance (Ron) will increase and the gate charge (QG) will increase. And affect the performance of the component.

The present invention proposes a power element that can reduce the leakage current between the gate and the isolation field plate, increase the breakdown voltage of the element, reduce the on-resistance, reduce the gate charge (QG), and improve the figure of merit (FOM), Improve the performance of components.

A power device according to an embodiment of the present invention includes: an epitaxial layer having trenches extending from a first surface to a second surface of the epitaxial layer; a drain doped layer located on the epitaxial layer On the second surface; the first body region and the second body region are located in the epitaxial layer on both sides of the trench; the first source doped region and the second source doped region are respectively located in the first A base region and the second base region; an isolation field plate, located in the trench; an insulating filling layer, located in the trench, surrounding the sidewall and bottom of the lower part of the isolation field plate; the first gate and The second gate is located in the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the second gate is located at all Between the isolation field plate and the second base region; and a dielectric layer surrounding the sidewalls of the first gate and the second gate, wherein the first gate and the second gate The bottom angle is obtuse.

A method of manufacturing a power device according to an embodiment of the present invention includes: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming an insulating filling layer and a conductor layer in the trench, and the insulating filling The layer surrounds the sidewall and bottom surface of the conductive layer, and the top of the insulating filling layer is lower than the top surface of the conductive layer, and a first gate trench and a second gate trench are formed on the insulating filling layer Groove; forming a gap wall mask on the sidewalls of the first gate groove and the second gate groove; using the gap wall mask as a mask, remove part of the insulating filling layer to Deepen the depth of the first gate trench and the second gate trench and have an arc-shaped bottom corner; remove the spacer mask; in the first gate trench and the A dielectric layer is formed in the second gate trench; and a first gate and a second gate are formed in the first gate trench and the second gate trench.

Based on the above, there is a sufficiently thick oxide layer at the bottom corner of the gate trench, so that the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the device can be increased. Under the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality factor (FOM), and enhance the performance of the device.

1A to 1L are schematic cross-sectional views of a method of manufacturing a power device according to an embodiment of the present invention. The power element is, for example, SGT MOSFET.

1A, the manufacturing method of the power device includes forming the drain doped layer 12 in the substrate 10. The substrate 10 may be a semiconductor substrate 10, such as a silicon substrate. The drain doped layer 12 may be formed in-situ during the wafer manufacturing process. The drain doped layer 12 has first conductivity type dopants. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. Next, an epitaxial layer 14 is formed on the drain doped layer 12. The method for forming the epitaxial layer 14 is, for example, a selective epitaxial growth process. The epitaxial layer 14 has dopants of the first conductivity type. The first conductivity type dopant is an N-type dopant, such as phosphorus or arsenic. The doping concentration of the epitaxial layer 14 is, for example, lower than the doping concentration of the drain doped layer 12. The dopants of the epitaxial layer 14 may be formed in-situ during the selective epitaxial growth process, or may be formed by an ion implantation process after the selective epitaxial growth process is performed.

Thereafter, trenches 16 are formed in the epitaxial layer 14. The trench 16 extends from the first surface 14a to the second surface 14b of the epitaxial layer 14. The trench 16 can be formed by lithography and etching processes. The etching process may be an anisotropic etching process, an isotropic etching process, or a combination thereof. After that, an insulating filling layer 18 and a conductive layer 20 are formed on the epitaxial layer 14 and in the trench 16. The material of the insulating filling layer 18 is, for example, silicon oxide, silicon nitride, or a combination thereof formed by chemical vapor deposition. The conductor layer 20 is formed on the insulating filling layer 18 and fills the remaining space of the trench 16. The conductive layer 20 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by a chemical vapor deposition method. In some embodiments, the conductive layer 20 is doped polysilicon with a doping concentration ranging from 3E18 1/cm ³ to 3E20 1/cm ³ .

1B, the conductive layer 20 is etched back to remove the conductive layer 20 other than the trench 16 to leave the conductive layer 20a in the trench 16. In some embodiments, the top surface of the conductive layer 20 a is lower than the top surface of the epitaxial layer 14. In other embodiments, the top surface of the conductive layer 20a and the top surface of the epitaxial layer 14 are substantially coplanar (not shown). The conductor layer 20a may be referred to as a source polysilicon layer. In addition, the conductor layer 20a can be used as an isolation field plate, so it can be called an isolation field plate 20a. The conductor layer 20a, which can be used as an isolation field plate, can evenly distribute the electric field of the epitaxial layer 14 under the first p-body region 36 and the second body region 38 (please refer to FIG. 1L) that are subsequently formed, so that they are opposite to each other. The critical electric field strength is reduced, so the breakdown voltage can be increased. On the other hand, under the same breakdown voltage, the doping concentration of the epitaxial layer 14 can be increased to reduce the on-resistance (Ron).

1C, the insulating filling layer 18 is etched back to remove the insulating filling layer 18 other than the trench 16 to leave the insulating filling layer 18a in the trench 16. In some embodiments, the insulating filling layer 18a surrounds the sidewall and the bottom surface of the conductive layer 20a, and the top of the insulating filling layer 18a is lower than the top surface of the conductive layer 20a. In other words, the insulating filling layer 18 a has a first gate trench 22 and a second gate trench 24. The sidewalls of the first gate trench 22 and the second gate trench 24 expose the epitaxial layer 14 and the conductor layer 20a, and the bottom surfaces of the first gate trench 22 and the second gate trench 24 expose the insulating filling The top of layer 18a. The etch-back process is, for example, an anisotropic etching process, an isotropic etching process, or a combination.

1D, a spacer layer 26 is formed on the epitaxial layer 14 and the conductor layer 20a and in the first gate trench 22 and the second gate trench 24. The spacer layer 26 is, for example, a conformal layer. The spacer layer 26 and the insulating filling layer 18a are made of different materials, and have a different etching rate from the insulating filling layer 18a. In the embodiment where the insulating filling layer 18a is an oxide, the spacer layer 26 is, for example, nitride. The spacer layer 26 is, for example, silicon nitride, silicon oxide, or a combination thereof formed by a chemical vapor deposition method or an atomic layer deposition method. The thickness of the spacer layer 26 is, for example, 1/10 to 1/3 of the width of the first gate trench 22 or the second gate trench 24. The spacer layer 26 may be a single layer or multiple layers.

1E, an anisotropic etching process is performed on the spacer layer 26 to form a spacer mask 28 on the sidewalls of the first gate trench 22 and the second gate trench 24. The spacer mask 28 covers the surrounding portion of the insulating filling layer 18a at the top of the first gate trench 22 and the second gate trench 24, and makes the insulating filling layer 18a in the first gate trench 22 and the second gate trench 24 The central part of the top in the second gate trench 24 is exposed.

1F, using the spacer mask 28 as a mask, an etching process is performed to remove part of the insulating filling layer 18a, so that the depth of the first gate trench 22 and the second gate trench 24 is deepened, forming a first gate trench 22 and a second gate trench 24. A gate trench 22' and a second gate trench 24'. The etching process may be an isotropic etching process, such as a dry etching process, a wet etching process, or a combination thereof.

Since the central part of the top of the insulating filling layer 18a located in the first gate trench 22 and the second gate trench 24 is not covered by the spacer mask 28, the amount of etching is relatively large; located at the first gate Since the surrounding portions of the top of the insulating filling layer 18a in the trench 22 and the second gate trench 24 are shielded by the spacer mask 28, they are less likely to be etched, so the amount of etching is less. Therefore, the insulating filling layer 18b is left after the etching process. The insulating filling layer 18b surrounds the sidewalls and the bottom of the lower portion of the conductor layer 20a, and the central part of the top in the first gate trench 22' and the second gate trench 24' is relatively concave, and the surrounding part of the top is relatively concave. Raised. In other words, the insulating filling layer 18b includes the main body MB and the protrusions P1, P2, P3, and P4. The main body MB surrounds the sidewall and the bottom of the lower portion of the conductor layer 20a. The protrusions P1, P2, P3, and P4 are on the main body MB and adjacent to the sidewalls of the first gate trench 22' and the second gate trench 24', that is, the sidewalls of the epitaxial layer 14 and the conductor layer 20a. The protrusions P1, P2, P3, and P4 have sidewalls substantially perpendicular to the surface of the substrate 10, which are adjacent to the sidewalls of the epitaxial layer 14 or the conductor layer 20a. The protrusions P1, P2, P3, and P4 also have arc-shaped sidewalls, the width of which is tapered from the second surface 14b of the epitaxial layer 14 to the first surface 14a of the epitaxial layer 14. Therefore, the formed first gate trench 22' and second gate trench 24' have a bottom angle greater than 90 degrees, and the bottom angle may be, for example, a circular arc shape.

1G and 1H, the spacer mask 28 is removed, and the first gate trench 22' and the second gate trench 24' are exposed. Next, a dielectric layer 30 is formed on the epitaxial layer 14 and the conductive layer 20a and in the first gate trench 22' and the second gate trench 24'. The dielectric layer 30 may be silicon oxide formed by a thermal oxidation method or a chemical vapor deposition method. In some embodiments where the dielectric layer 30 may be a silicon oxide layer formed by a thermal oxidation method, since the doping concentration of the conductive layer 20a is greater than the doping concentration of the epitaxial layer 14, compared to the epitaxial layer 14, the conductive layer 20a is easier to oxidize. Therefore, the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the conductor layer 20 a is greater than the thickness of the dielectric layer (silicon oxide layer) 30 formed on the surface of the epitaxial layer 14. In addition, since the protrusions P1, P2, P3, and P4 at the bottom corners of the first gate trench 22' and the second gate trench 24' are quite thin, the oxidized gas (for example, oxygen) can still be used. Pass through the protrusions P1, P2, P3, and P4 to react with the sidewalls of the epitaxial layer 14 and the conductor layer 20a to form a silicon oxide layer. In some embodiments, after the dielectric layer 30 is formed, the remaining spaces of the first gate trench 22' and the second gate trench 24' still have a circular bottom angle, or a bottom angle greater than 90 degrees .

1I, a conductive layer 31 is formed on the dielectric layer 30. The conductor layer 31 fills the remaining space of the first gate trench 22' and the second gate trench 24'. The conductive layer 31 may be a semiconductor material, such as undoped polysilicon or doped polysilicon formed by a chemical vapor deposition method.

1J, the conductive layer 31 is etched back to remove the conductive layer 31 other than the first gate trench 22' and the second gate trench 24', so that the first gate trench 22' and the second gate trench A first gate 32 and a second gate 34 are formed in the two gate trenches 24 ′. Since the first gate 32 and the second gate 34 occupy the remaining space of the first gate trench 22' and the second gate trench 24', the first gate 32 and the second gate 34 have a degree greater than 90 degrees Bottom corner. The bottom corner may be in the shape of a circular arc, for example.

There is an arc-shaped interface between the dielectric layer 30 and the protrusion P1 between the first gate electrode 32 and the epitaxial layer 14, and the two are collectively referred to as the first gate dielectric layer 30 a. There is an arc-shaped interface between the dielectric layer 30 and the protrusion P2 between the second gate electrode 34 and the epitaxial layer 14, and the two are collectively referred to as the second gate dielectric layer 30b. There is an arc-shaped interface between the dielectric layer 30 and the protrusion P3 between the first gate electrode 32 and the conductive layer 20a, and the two are collectively referred to as the first insulating layer 30c. There is an arc-shaped interface between the dielectric layer 30 and the protrusion P4 between the second gate electrode 34 and the conductor layer 20a, and the two are collectively referred to as the second insulating layer 30d.

1J, a first body region 36 and a second body region 38 are formed in the epitaxial layer 14 on both sides of the trench 16. The first body region 36 and the second body region 38 extend from the first surface 14a to the second surface 14b of the epitaxial layer 14. The first body region 36 and the second body region 38 have second conductivity type dopants, such as P-type dopants. The P-type dopant is, for example, boron or boron trifluoride. The formation method of the first base region 36 and the second base region 38 is, for example, an ion implantation method. In another embodiment, the first body region 36 and the second body region 38 may be formed before the trench 16 is formed. For example, the first body region 36 and the second body region 38 can be formed in-situ during the selective epitaxial growth process of forming the epitaxial layer 14, or after the selective epitaxial growth process is performed Then it is formed by ion implantation process.

Next, a first source doped region 42 and a second source doped region 44 are formed in the first body region 36 and the second body region 38, respectively. The first source doped region 42 and the second source doped region 44. It has a first conductivity type dopant, for example, an N-type dopant. N-type dopants, such as phosphorus or arsenic. The formation method of the first source doped region 42 and the second source doped region 44 is, for example, an ion implantation method.

1K, a dielectric layer 46 is formed on the epitaxial layer 14 to cover the first source doped region 42, the second source doped region 44, the first gate 32, the second gate 34, and the conductor层20a. The dielectric layer 46 is, for example, silicon oxide, silicon nitride, borophosphosilicate glass (BPSG) or a combination thereof formed by chemical vapor deposition. Next, a lithography and etching process is performed to form a first contact window opening 52 and a second contact window opening 54 in the dielectric layer 46, wherein the sides of the first contact window 52 and the second contact window 54 are respectively exposed to the first contact window opening 52 and the second contact window opening 54 The source doped region 42 and the second source doped region 44. Thereafter, a first doped region 62 and a second doped region 64 are formed in the first body region 36 and the second body region 38, respectively. The first doped region 62 and the second doped region 64 have second conductivity type dopants. The second conductivity type dopant may be a P type dopant, such as boron or boron trifluoride. The method for forming the first doped region 62 and the second doped region 64 is, for example, an ion implantation method.

1L, after that, a first contact 72 contacting the first doped region 62 and a second contact 72 contacting the second doped region 64 are formed in the first contact opening 52 and the second contact opening 54 respectively. The contact window 74, and the first contact window 72 and the second contact window 74 are electrically connected to each other.

After that, the subsequent metallization process is performed. The subsequent metallization process may include processes such as electrically connecting the first gate electrode 32 and the second gate electrode 34.

Fig. 2 shows an enlarged schematic diagram of the area R in Fig. 1L. FIG. 3A shows an enlarged schematic diagram of area A in FIG. 2. FIG. 3B shows an enlarged schematic diagram of area B in FIG. 2. FIG. 3C shows an enlarged schematic diagram of area C in FIG. 2. FIG. 3D shows an enlarged schematic diagram of area D in FIG. 2.

1L and FIG. 2, the bottom angles α1, β1, α2, and β2 of the first gate 32 and the second gate 34 are obtuse angles greater than 90 degrees. The bottom corner may be in the shape of a circular arc, for example. In addition, since the doping concentration in the conductive layer 20a is greater than the doping concentration of the epitaxial layer 14, the dielectric layer 30 formed on the sidewall of the conductive layer 20a is thicker than that of the dielectric layer 30 formed on the sidewall of the epitaxial layer 14. thickness. Therefore, the average thickness T3 of the first insulating layer 30c between the conductor layer 20a and the first gate 32 and composed of the dielectric layer 30 and the protrusion P3 is greater than that between the epitaxial layer 14 and the first gate 32 The average thickness T1 of the first gate dielectric layer 30a between the dielectric layer 30 and the protrusion P1 is as shown in FIG. 2, FIG. 3A and FIG. 3B. The average thickness T4 of the second insulating layer 30d between the conductor layer 20a and the second gate 34 and composed of the dielectric layer 30 and the protrusion P4 is greater than that between the epitaxial layer 14 and the second gate 34 and The average thickness T2 of the second gate dielectric layer 30b combined by the dielectric layer 30 and the protrusion P2 is as shown in FIG. 2, FIG. 3C, and FIG. 3D.

Referring to FIGS. 2, 3A and 3B, the minimum thicknesses T _min1 and T _min2 of the first gate dielectric layer 30a and the second gate dielectric layer 30b are at the level of the first gate 32 and the second gate 34 between the top and bottom surfaces. The ratio of the minimum thickness T _min1 to the average thickness T1 and the ratio of the minimum thickness T _min2 to the average thickness T2 are greater than 0.8, for example, 0.85 to 0.95. In one embodiment, the average thicknesses T1 and T2 of the first gate dielectric layer 30a and the second gate dielectric layer 30b are, for example, about 800 angstroms to 820 angstroms; the first gate dielectric layer 30a and the second gate dielectric layer The minimum thicknesses T _min1 and T _{min2 of} 30b are, for example, about 720 angstroms to 740 angstroms. _{The absolute value of the difference between the minimum thickness T min1} and T _{min2 of the} first gate dielectric layer 30 a and the second gate dielectric layer 30 b and the average thickness is less than 100 angstroms, for example, 60 to 80 angstroms.

Referring to Figures 2, 3C and 3D, the minimum thicknesses T _min3 and T _min4 of the first insulating layer 30c and the second insulating layer 30d are at the level of the top surface of the first gate 32 and the second gate 34 Between and the bottom surface. The positions of the minimum thicknesses T _min3 and T _min4 are far away from the top surfaces of the first gate 32 and the second gate 34 and closer to the bottom surfaces of the first gate 32 and the second gate 34. The ratio of the minimum thickness T _min3 to the average thickness T3 and the ratio of the minimum thickness T _min4 to the average thickness T4 are greater than 0.8, for example, 0.85 to 0.9. In one embodiment, the average thicknesses T3 and T4 of the first insulating layer 30c and the second insulating layer 30d are, for example, about 900 angstroms to 920 angstroms; the minimum thicknesses T _min3 and T of the first insulating layer 30c and the second insulating layer 30d _{The min4 is,} for example, about 800 angstroms to 820 angstroms. _{The absolute value of the difference between the minimum thickness T min3} and T _{min4 of the} first insulating layer 30c and the second insulating layer 30d and the average thickness is less than 100 angstroms, for example, 60 to 80 angstroms.

Please refer to FIG. 2. On the other hand, the position of the maximum width of the first gate electrode 32 and the second gate electrode 34 is not on the top surface or the bottom surface, but between the top surface and the bottom surface. The positions of the maximum widths of the first gate 32 and the second gate 34 are far away from the top surfaces of the first gate 32 and the second gate 34 and closer to the bottom surfaces of the first gate 32 and the second gate 34.

Figure 1L above shows a cell of the SGT MOSFET. However, the present invention is not limited to this. In some embodiments, the SGT MOSFET may have two cells C1 and C1', as shown in FIG. 4. The cells C1 and C1' are adjacent to each other, and the first base region 36 and the first doped region 62 are shared by the cells C1 and C1'. In addition, the first doped region 62, the second doped region 64, and the second doped region 64' are electrically connected to each other through the first contact window 72 and the second contact windows 74, 74'. The first gate 32 and the second gate 34 of the cell C1 and the first gate 32' and the second gate 34' of the cell C1' may be electrically connected to each other.

In other embodiments, the SGT MOSFET may have more cells, and these cells may be arranged in an array. In other words, the SGT MOSFET may have multiple gates, multiple source doped regions, and multiple drain doped regions. These multiple gates, multiple sources, and multiple drains can be respectively arranged in an array, and these multiple gates, multiple source doped regions, and multiple drain doped regions can be respectively arranged by Inner wires are connected together to form a gate terminal point, a source terminal point and a drain terminal point.

In summary, in the present invention, a gap wall mask is formed on the sidewall of the gate trench, and then an isotropic etching process is performed to deepen the depth of the gate trench and make it have an arc-shaped bottom corner, so that the subsequent use The oxygen used in the oxidation process to form the gate dielectric layer can pass through the protrusions at the bottom corners of the gate trench, so that the conductor layer around the bottom corner of the gate trench as the isolation field plate and the epitaxial layer can be Oxidation, and an oxide layer is formed at the bottom corner of the gate trench. Since there is a sufficiently thick oxide layer at the bottom corner of the gate trench, the leakage current between the gate and the isolation field plate can be reduced, and the breakdown voltage of the device can be increased. Simulation experiments show that the breakdown voltage can be increased by about 2 to 3 times. Under the premise of maintaining the same breakdown voltage, the concentration of the epitaxial layer can be increased to reduce the on-resistance (Ron), reduce the gate charge (QG), improve the quality factor (FOM), and enhance the performance of the device.

10: substrate 12: drain doped layer 14: epitaxial layer 14a: first surface 14b: second surface 16: trench 18, 18a, 18b: insulating filling layer 30c: first insulating layer 30d: second insulating layer 20 31: Conductor layer 20a: Conductor layer, isolation field plates 22, 22': First gate trench 24, 24': Second gate trench 26: Spacer layer 28: Spacer cover 30, 46: Dielectric layer 30a: first gate dielectric layer 30b: second gate dielectric layer 32, 32': first gate 34, 34': second gate 36: first base region 38: second base region 42 : First source doped region 44: second source doped region 52: first contact window opening 54: second contact window opening 62: first doped region 64, 64': second doped region 72: First contact window 74, 74': second contact window A, B, C, D, R: area C1, C1': unit MB: main body P1, P2, P3, P4: protrusions T1, T2, T3 , T4: average thickness T _min1 , T _min2 , T _min3 , T _min4 : minimum thickness α1, α2, β1, β2: bottom angle

1A to 1L are schematic cross-sectional views of a method of manufacturing a power device according to an embodiment of the present invention. Fig. 2 is an enlarged schematic diagram of area R in Fig. 1L. FIG. 3A is an enlarged schematic diagram of area A in FIG. 2. FIG. 3B is an enlarged schematic diagram of area B in FIG. 2. FIG. 3C is an enlarged schematic diagram of area C in FIG. 2. FIG. 3D is an enlarged schematic diagram of area D in FIG. 2. FIG. 4 is a schematic cross-sectional view showing two units of the power device.

10: Base

12: Drain doped layer

14: epitaxial layer

14a: first surface

14b: second surface

16: trench

18b: Insulating filling layer

20a: Conductor layer, isolation field plate

22’: The first gate trench

24’: The second gate trench

28: Clearance wall screen

MB: main body

P1, P2, P3, P4: protrusions

Claims (13)

A power device includes: an epitaxial layer with trenches extending from a first surface to a second surface of the epitaxial layer; a drain doped layer located on the second surface of the epitaxial layer; A body region and a second body region are located in the epitaxial layer on both sides of the trench; a first source doped region and a second source doped region are respectively located in the first body region and the In the second base region; the isolation field plate is located in the trench; the insulating filling layer is located in the trench and surrounds the sidewall and bottom of the lower part of the isolation field plate; the first gate and the second gate are located In the trench and on the insulating filling layer, wherein the first gate is located between the isolation field plate and the first base region, and the second gate is located between the isolation field plate and the Between the second base region; and a dielectric layer surrounding the sidewalls of the first gate and the second gate, wherein the bottom angle of the first gate and the second gate is an obtuse angle, The thickness of the dielectric layer on the surface of the isolation field plate is greater than the thickness of the dielectric layer on the surface of the epitaxial layer. The power device according to claim 1, wherein the bottom corners of the first gate and the second gate are arc-shaped. The power element according to claim 1, wherein the position of the maximum width of the first gate electrode and the second gate electrode is between the top surface and the bottom surface thereof. The power device according to claim 1, wherein the insulating filling layer has protrusions located on the sidewalls of the isolation field plate and the epitaxial layer. The power device according to claim 4, wherein: the dielectric layer and the protrusion located between the epitaxial layer and the first gate form a first gate dielectric layer; The dielectric layer and the protrusion between the epitaxial layer and the second gate electrode form a second gate dielectric layer; the second gate dielectric layer is located between the first gate electrode and the isolation field plate The dielectric layer and the protrusions form a first insulating layer; and the dielectric layer and the protrusions between the second gate electrode and the isolation field plate form a second insulating layer. The power device according to claim 5, wherein the ratio of the minimum thickness to the average thickness of the first insulating layer and the ratio of the minimum thickness to the average thickness of the second insulating layer are respectively greater than 0.8. The power device according to claim 5, wherein the ratio of the minimum thickness to the average thickness of the first gate dielectric layer and the ratio of the minimum thickness to the average thickness of the second gate dielectric layer are respectively greater than 0.8. The power device according to claim 5, wherein the horizontal heights of the minimum width positions of the first gate dielectric layer and the second gate dielectric layer are between the first gate electrode and the second gate electrode Between the top and bottom of the The power device according to claim 5, wherein the average thickness of the first insulating layer is greater than the average thickness of the first gate dielectric layer, and the average thickness of the second insulating layer is greater than the average thickness of the second gate dielectric The average thickness of the electrical layer. The power device according to claim 1, further comprising: a first doped region located in the first body region, and adjacent to the first source doped region and within the first doped region The top surface level is lower than the first source doped region; the second doped region is located in the second body region and is adjacent to the second source doped region and the second doped region The top surface level of the impurity region is lower than the second source doped region, wherein the first doped region and the second doped region have a conductivity type different from that of the drain doped layer; A contact window located on the first doped region and in contact with the first doped region; and a second contact window located on the second doped region and in contact with the second doped region, And it is electrically connected with the first contact window. A method for manufacturing a power device includes: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming an insulating filling layer and a conductor layer in the trench, the insulating filling layer surrounding the conductor layer The sidewall and bottom surface of the insulating filling layer are lower than the top surface of the conductor layer, and a first gate trench and a second gate trench are formed on the insulating filling layer; A gap wall mask is formed on the sidewalls of the first gate trench and the second gate trench; using the gap wall mask as a mask, a part of the insulating filling layer is removed to make the The depths of the first gate groove and the second gate groove are deepened and have arc-shaped bottom corners; the gap wall mask is removed; the first gate groove and the second gate groove A dielectric layer is formed in the two gate trenches; and a first gate and a second gate are formed in the first gate trench and the second gate trench. The method for manufacturing a power device according to claim 11, further comprising: forming a drain doped layer in the substrate before forming the epitaxial layer on the substrate; A first body region and a second body region are formed in the epitaxial layer; and a first source doped region and a second source doped region are formed in the first body region and the second body region, respectively. The method for manufacturing a power device according to claim 12, further comprising: forming a first doped region adjacent to the first source doped region in the first base region; A second doped region adjacent to the first source doped region is formed in the second body region; a first contact window is formed on the first doped region to interact with the first doped region. Miscellaneous region contact; and forming a second contact window on the second doped region to contact the second doped region and electrically connect with the first contact window.

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