TWI775695B - Trench transistor and manufacturing method thereof - Google Patents

Abstract

Provided are a trench transistor and a manufacturing method thereof. The manufacturing method of a trench transistor includes the following steps. A trench is formed in a substrate. A first insulating layer is formed on the sidewall and bottom surface of the trench. A first conductive layer is formed on the first insulating layer in the trench, wherein voids or seams are formed in a part of the first conductive layer. A part of the first conductive layer is removed to remove voids or seams. A protective layer is formed on the first conductive layer in the trench and on the first insulating layer on the sidewall of the trench. At least a part of the first insulating layer between the protective layer and the sidewall of the trench is removed. A second insulating layer is formed on the exposed sidewall of the trench. The protective layer is removed. A second conductive layer is formed on the first conductive layer. The second insulating layer above the second conductive layer is removed. A third insulating layer is formed on the second conductive layer and on the sidewall of the trench. A third conductive layer is formed on the third insulating layer. A first doped region is formed in the substrate around the third conductive layer.

Description

Trench transistor and method of making the same

The present invention relates to a transistor and a manufacturing method thereof, and more particularly, to a trench transistor and a manufacturing method thereof.

In the current technology, trench metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely used in power switch components, such as power supplies, rectifiers or Low voltage motor controller. For a general shield gate trench (SGT) MOSFET, the quality of the gate electrode and the shield electrode (also called the source electrode) disposed in the trench is very important to the device. have a significant effect on the electrical properties. In particular, in the process of forming a shaded gate trench MOSFET, since the trench has a high aspect ratio, it tends to form when electrode material is filled into the trench. A void or a seam. When voids or pores are generated, the quality of the formed electrode will be seriously affected, thereby seriously affecting the electrical characteristics of the device.

The present invention provides a trench transistor that includes electrodes without holes or pores.

The present invention provides a method for manufacturing a trench transistor, which adopts a multi-stage manner to form a conductive layer serving as a shield electrode or a source electrode.

The manufacturing method of the trench transistor of the present invention includes the following steps. A trench is formed in the substrate. A first insulating layer is formed on the sidewall and bottom surface of the trench. A first conductive layer is formed on the first insulating layer in the trench, wherein holes or pores are formed in a portion of the first conductive layer. Parts of the first conductive layer are removed to remove the holes or pores. A protective layer is formed on the first conductive layer in the trench and on the first insulating layer on the sidewall of the trench. At least a portion of the first insulating layer between the protective layer and the sidewall of the trench is removed. A second insulating layer is formed on the exposed sidewalls of the trench. The protective layer is removed. A second conductive layer is formed on the first conductive layer. The second insulating layer over the second conductive layer is removed. A third insulating layer is formed on the second conductive layer and the sidewall of the trench. A third conductive layer is formed on the third insulating layer. A first doped region is formed in the substrate around the third conductive layer.

In an embodiment of the method for fabricating a trench transistor of the present invention, the protective layer includes a silicon nitride layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the protective layer fills the trench.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the substrate includes a base layer and an epitaxial layer formed on the base layer, and the trench is located in the epitaxial layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, after removing a part of the first insulating layer between the protective layer and the sidewall of the trench, the first insulating layer The top surface of the first conductive layer is not lower than the top surface of the first conductive layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the method for forming the second conductive layer includes the following steps. A conductive material layer is filled in the trenches. An etch-back process is performed to remove part of the conductive material layer, wherein the top surface of the remaining conductive material layer is higher than the top surface of the first insulating layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the method for forming the second conductive layer includes the following steps. A conductive material layer is filled in the trenches. An etch-back process is performed to remove part of the conductive material layer, wherein the top surface of the remaining conductive material layer is not higher than the top surface of the first insulating layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the method for forming the third insulating layer includes performing a thermal oxidation process.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the bottom surface of the first doped region is not higher than the bottom surface of the third conductive layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the following steps are further included after forming the first doped region. A second doped region is formed in the first doped region, wherein the conductivity type of the second doped region is different from that of the first doped region. A fourth insulating layer is formed on the substrate. A contact window connected to the second doped region is formed in the fourth insulating layer. A fourth conductive layer connected to the contact window is formed on the fourth insulating layer.

In an embodiment of the method for manufacturing a trench transistor of the present invention, after the fourth insulating layer is formed and before the contact window is formed, a third doped region is further formed under the contact window , and the conductivity type of the third doped region is the same as that of the first doped region.

In an embodiment of the method for manufacturing a trench transistor of the present invention, the thickness of a portion of the first insulating layer located on the bottom surface of the trench is greater than that of the first insulating layer located in the trench The thickness of the part on the side wall.

The trench transistor of the present invention includes a substrate having a trench, a first electrode, an insulating layer, a second electrode, an inter-gate dielectric layer, a gate dielectric layer, and a body body region. The first electrode is disposed at the lower portion of the trench. The insulating layer is disposed between the first electrode and the sidewall and bottom surface of the trench. The second electrode is disposed on the first electrode. The inter-gate dielectric layer is disposed between the first electrode and the second electrode. The gate dielectric layer is disposed between the second electrode and the substrate. The body region is disposed in the substrate around the second electrode.

In an embodiment of the trench transistor of the present invention, a thickness of a portion of the insulating layer located on a bottom surface of the trench is greater than a thickness of a portion of the insulating layer located on a sidewall of the trench .

In an embodiment of the trench transistor of the present invention, the substrate includes a base layer and an epitaxial layer disposed on the base layer, and the trench is located in the epitaxial layer.

In an embodiment of the trench transistor of the present invention, the first electrode includes a first portion and a second portion located on the first portion, and the width of the second portion is greater than the width of the first portion .

In an embodiment of the trench transistor of the present invention, it further includes a second insulating layer disposed between the second portion and the substrate.

In an embodiment of the trench transistor of the present invention, the bottom surface of the body region is not higher than the bottom surface of the second electrode.

In an embodiment of the trench transistor of the present invention, it further includes a source region, an inter-layer dielectric layer, a contact, and a conductive layer. The source region is disposed in the body region. The interlayer dielectric layer is disposed on the substrate. The contact window is disposed in the interlayer dielectric layer and is electrically connected with the source region. The conductive layer is disposed on the interlayer dielectric layer and is electrically connected with the contact window.

In an embodiment of the trench transistor of the present invention, it further includes a doped region disposed below the contact window and electrically connected to the contact window, wherein the conductivity type of the doped region is the same as The conductivity types of the body regions are the same.

To sum up, in the fabrication process of the trench transistor of the present invention, the protective layer and the multi-stage method are used to form the conductive layer as the shielding electrode or the source electrode, so that the existence of holes or holes in the conductive layer can be effectively avoided. pores, so that the trench transistor of the present invention can have stable electrical performance.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

The following examples will be described in detail with reference to the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to full scale. In order to facilitate understanding, the same elements will be described with the same symbols in the following description.

Terms such as "include", "include", "have", etc. used in the text are all open-ended terms, that is, "including but not limited to".

When describing elements in terms of "first", "second", etc., they are only used to distinguish these elements from each other and do not limit the order or importance of the elements. Therefore, in some cases, the first element may also be referred to as the second element, and the second element may also be referred to as the first element, without departing from the scope of the present invention.

In addition, the directional terms mentioned in the text, such as "up", "down", etc., are only used to refer to the direction of the drawings, and are not used to limit the present invention. Thus, it will be understood that "on" is used interchangeably with "under" and that when an element such as a layer or film is placed "on" another element, the element can be directly on the other element or may be present intermediate element. On the other hand, when an element is referred to as being "directly on" another element, there are no intervening elements between the two elements.

1A to 1G are cross-sectional schematic diagrams illustrating a manufacturing process of a trench transistor according to an embodiment of the present invention. In this embodiment, the trench transistor is a shielded gate trench metal oxide semiconductor field effect transistor, which has a gate disposed in the trench and a shielding electrode (also referred to as a source electrode). The following This will be explained in detail. In addition, in this embodiment, the first conductivity type is one of the P-type and the N-type, and the second conductivity type is the other of the P-type and the N-type.

First, referring to FIG. 1A, a substrate 100 is provided. In this embodiment, the substrate 100 includes a base layer 100a and an epitaxial layer 100b formed on the base layer 100a. The base layer 100a is, for example, a heavily doped silicon base layer with the first conductivity type. The epitaxial layer 100b is, for example, a lightly doped epitaxial layer of the first conductivity type. The method for forming the epitaxial layer 100b is, for example, a selective epitaxy growth (SEG) process. Next, trenches 102 are formed in the epitaxial layer 100b. In this embodiment, the depth of the trench 102 is smaller than the thickness of the epitaxial layer 100b, that is, the bottom of the trench 102 is located in the epitaxial layer 100b, so that the trench 102 does not expose the base layer 100a. Furthermore, in this embodiment, the trenches 102 have substantially vertical sidewalls.

Next, referring to FIG. 1B , a first insulating layer 104 is formed on the sidewall and bottom surface of the trench 102 . In this embodiment, the first insulating layer 104 is a silicon oxide layer. A method for forming the first insulating layer 104 is, for example, a thermal oxidation process to conformally form an insulating material layer on the substrate 100 . In this embodiment, the first insulating layer 104 has a substantially uniform thickness, that is, the thickness of the portion of the first insulating layer 104 located on the bottom surface of the trench 102 is substantially equal to the thickness of the first insulating layer 104 located on the trench 102 The thickness of the part on the side wall. Then, a first conductive layer 106 is formed on the first insulating layer 104 in the trench 102 . In this embodiment, the first conductive layer 106 is a polysilicon layer. A method for forming the first conductive layer 106 is, for example, a chemical vapor deposition (CVD) process, so as to fill the conductive material layer into the trench 102 . Since the trenches 102 generally have a relatively high aspect ratio, after the conductive material layer is filled into the trenches 102 , holes or pores 106 a are inevitably formed in the first conductive layer 106 formed. Generally, holes or pores 106a are mostly formed in the upper portion of the first conductive layer 106 . In FIG. 1B , only one hole or aperture 106a is shown for clarity of the drawing and convenience of description, but the present invention is not limited thereto.

Then, referring to FIG. 1C , a portion of the first conductive layer 106 is removed, leaving the first conductive layer 106 at the lower portion of the trench 102 . In this embodiment, an etching-back process is performed to remove the first conductive layer 106 located outside the trench 102 and a part of the first conductive layer 106 located in the trench 102 . As such, the holes or pores 106a in the first conductive layer 106 can be removed. After that, a protective layer 108 is formed on the first conductive layer 106 in the trench 102 . In this embodiment, the method for forming the protective layer 108 is, for example, to form a protective material layer on the substrate 100 conformally covering the top surface of the first conductive layer 106 and the first insulating layer 104, and then perform an etching process to remove A layer of protective material on the top surface of the first insulating layer 104 except for the trenches 102 . In this embodiment, the protective material layer is a silicon nitride layer, but the present invention is not limited thereto. In other embodiments, as long as the protective material layer has a lower etching rate than the first insulating layer 104 in the subsequent etching process. In addition, in this embodiment, the protective material layer is conformally formed on the substrate 100 , that is, the protective material layer does not fill the trench 102 , but the invention is not limited thereto. In other embodiments, the protective material layer may fill the trenches 102 .

Next, referring to FIG. 1D , a portion of the first insulating layer 104 between the protective layer 108 and the sidewall of the trench 102 is removed. In this embodiment, the method for removing part of the first insulating layer 104 is, for example, performing an etch-back process. Since the protective layer 108 has a lower etching rate than the first insulating layer 104 , the protective layer 108 can still remain on the first conductive layer 106 after a portion of the first insulating layer 104 is removed. In addition, in this embodiment, after removing part of the first insulating layer 104 , the top surface of the remaining first insulating layer 104 is higher than the top surface of the first conductive layer 106 , but the invention is not limited thereto. In other embodiments, the top surface of the remaining first insulating layer 104 may be coplanar with the top surface of the first conductive layer 106 . After that, a second insulating layer 110 is formed on the exposed sidewalls of the trench 102 and the top surface of the epitaxial layer 100b. In this embodiment, the second insulating layer 110 is a silicon oxide layer. The formation method of the second insulating layer 110 is, for example, a thermal oxidation process. Since the protective layer 108 remains on the first conductive layer 106 , the second insulating layer 110 is not formed on the first conductive layer 106 .

Then, referring to FIG. 1E, the protective layer 108 is removed. Next, a second conductive layer 112 is formed on the first conductive layer 106 . In this embodiment, the second conductive layer 112 is a polysilicon layer. The formation method of the second conductive layer 112 is, for example, performing a chemical vapor deposition process to fill the conductive material layer into the trench 102 , and then performing an etch back process to remove the conductive material layer outside the trench 102 and the trench 102 . Part of the conductive material layer in 102 , so that the top surface of the remaining conductive material layer is higher than the top surface of the first insulating layer 104 . In this way, the first conductive layer 106 and the second conductive layer 112 can constitute the first electrode 114 of the trench transistor of this embodiment. The first electrode 114 may serve as a shielding electrode (also referred to as a source electrode). Specifically, in this embodiment, the first electrode 114 is disposed at the lower portion of the trench 102 , and the first electrode 114 includes a first portion 114 a and a second portion 114 b located on the first portion 114 a. The width of the second portion 114b is greater than the width of the first portion 114a, that is, the cross-section of the first electrode 114 presents a “T” shape.

Next, referring to FIG. 1F , the second insulating layer 110 above the second conductive layer 112 is removed to expose part of the sidewalls of the trenches 102 . In this embodiment, an etch-back process may be performed to remove the second insulating layer 110 over the second conductive layer 112 until the top surface of the remaining second insulating layer 110 and the top surface of the second conductive layer 112 are coplanar. Then, a third insulating layer 116 is formed on the second conductive layer 112 and on the exposed sidewalls of the trench 102 . In this embodiment, the third insulating layer 116 is a silicon oxide layer. The formation method of the third insulating layer 116 is, for example, a thermal oxidation process. Next, a third conductive layer 118 is formed on the third insulating layer 116 . In this embodiment, the third conductive layer 118 is a polysilicon layer. The third conductive layer 118 is formed by, for example, performing a chemical vapor deposition process to fill the conductive material layer into the trench 102 , and then performing an etch-back process to remove the conductive material layer outside the trench 102 .

In this embodiment, the third conductive layer 118 can be used as the second electrode 120 (gate) of the trench transistor of this embodiment. The third insulating layer 116 between the first electrode 114 and the second electrode 120 may serve as an inter-gate dielectric layer, and the third insulating layer 116 between the second electrode 120 and the substrate 100 (the epitaxial layer 100b ) may serve as an inter-gate dielectric layer. as a gate dielectric.

Next, a first doped region 122 is formed in the substrate 100 (the epitaxial layer 100 b ) around the third conductive layer 118 . The first doped region 122 is, for example, a heavily doped doped region with the second conductivity type. A method for forming the first doped region 122 is, for example, an ion implantation process. The bottom surface of the first doped region 122 is not higher than the bottom surface of the third conductive layer 118 . In this embodiment, the bottom surface of the first doped region 122 and the bottom surface of the third conductive layer 118 are coplanar. The first doped region 122 may serve as the body region of the trench transistor of this embodiment.

Afterwards, referring to FIG. 1G , the structure in FIG. 1F may be subjected to subsequent required processes to form the trench transistor 10 of the present embodiment. For example, after the first doped region 122 is formed, the second doped region 124 is formed in the first doped region 122 . The second doped region 124 is, for example, a doped region with heavy doping of the first conductivity type. The formation method of the second doped region 124 is, for example, performing an ion implantation process. The depth of the second doped region 124 is smaller than that of the first doped region 122 . The second doped region 124 can be used as the source region of the trench transistor of this embodiment. That is, in the trench transistor 10, the second electrode 120 serves as a gate electrode, the first electrode 114 serves as a shield electrode or a source electrode, the second doped region 124 serves as a source electrode, and the substrate 100 serves as a drain electrode.

Next, a fourth insulating layer 126 may be formed on the substrate 100 . In this embodiment, the fourth insulating layer 126 is a silicon oxide layer. The formation method of the fourth insulating layer 126 is, for example, a chemical vapor deposition process. The fourth insulating layer 126 covers the third insulating layer 116 and the second electrode 120 to serve as an interlayer dielectric layer. Then, a contact window 128 electrically connected to the second doped region 124 may be formed in the fourth insulating layer 126 . In this embodiment, the bottom surface of the contact window 128 is located in the second doping region 124, but the invention is not limited thereto. In addition, in order to reduce the electrical resistance, before forming the contact window 128 , a doped region 130 electrically connected to the contact window 128 may be formed under the contact window 128 . The doped region 130 is, for example, a doped region with heavy doping of the second conductivity type. In addition, a conductive layer 132 electrically connected to the contact window 128 can be formed on the fourth insulating layer 126 . The conductive layer 132 is, for example, a metal layer. The conductive layer 132 may serve as a source line. The formation methods of the contact window 128 , the doped region 130 and the conductive layer 132 are well known to those skilled in the art, and will not be repeated here.

In this embodiment, the cross section of the first electrode 114 serving as the shielding electrode or the source electrode presents a "T" shape, but the present invention is not limited thereto. 2 is a schematic cross-sectional view of a trench transistor according to another embodiment of the present invention. During the steps shown in FIG. 1E , the conductive material layer located in the trench 102 is removed by an etch-back process until the top surface of the remaining conductive material layer is not higher than the top surface of the first insulating layer 104 . In this way, as shown in FIG. 2 , in the trench transistor 20 , the top surface of the formed second conductive layer 200 can be coplanar with the top surface of the first insulating layer 104 . In other embodiments, the top surface of the formed second conductive layer 200 may be lower than the top surface of the first insulating layer 104 . The first conductive layer 106 and the second conductive layer 200 constitute the first electrode 202 of the trench transistor of the present embodiment, so that the cross section of the first electrode 202 serving as a shielding electrode or a source electrode presents an "1" type, that is, the upper portion The width is substantially equal to the width of the lower part. In addition, since there is the first insulating layer 104 between the entire first electrode 202 and the substrate 100 , the step of forming the second insulating layer 110 in FIG. 1D can also be omitted.

In the above-mentioned embodiment, in the steps described in FIG. 1B , the formed first insulating layer 104 has a substantially uniform thickness, but the present invention is not limited thereto. In other embodiments, the first insulating layer 104 may not be formed with a substantially uniform thickness.

3A to 3C are schematic cross-sectional views illustrating a manufacturing process of a trench transistor according to another embodiment of the present invention. In this embodiment, the same components as those in FIGS. 1A to 1G will be denoted by the same reference numerals, and will not be described again.

First, referring to FIG. 3A , after the trench 102 is formed as described in FIG. 1A , a first insulating layer 104 a is formed at the bottom of the trench 102 . In this embodiment, the first insulating layer 104a is a silicon oxide layer. In addition, the thickness of the portion of the first insulating layer 104a on the bottom surface of the trench 102 is greater than the thickness of the portion of the first insulating layer 104a on the sidewall of the trench 102 . That is to say, in this embodiment, the first insulating layer 104a does not have a substantially uniform thickness, and it can be formed by adjusting the process parameters, and this method is well known to those skilled in the art, and will not be repeated here. Repeat.

Next, referring to FIG. 3B , the steps described in FIGS. 1B and 1C are performed to form a first conductive layer 106 on the first insulating layer 104 in the trench 102 . At this time, the first insulating layer 104 with a relatively large thickness exists under the first conductive layer 106 . Since the first insulating layer 104a has a relatively large thickness at the bottom of the trench 102, the aspect ratio of the trench 102 is reduced, which in turn can improve the voids or voids 106a when the first conductive layer 106 is formed (as shown in FIG. 1B ). shown) formation.

After that, referring to FIG. 3C , the steps described in FIGS. 1C to 1G are performed to form the trench transistor 30 of the present embodiment. In the trench transistor 30 , since the first insulating layer 104 with a relatively large thickness exists under the first electrode 114 , the problem of leakage current from the bottom of the trench transistor 30 during operation can be further avoided.

In addition, in other embodiments, the “1” type first electrode serving as the shield electrode or the source electrode can also be formed as shown in FIG. 2 .

To sum up, in the trench transistor of the present invention, the protective layer is used and the conductive layer as the shielding electrode or the source electrode is formed in a multi-stage manner, thus effectively avoiding holes or pores in the conductive layer. In this way, the trench transistor of the present invention can have stable electrical performance without being affected by holes or porosity.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10, 20, 30: Trench transistors 100: base 100a: Grassroots 100b: epitaxial layer 102: Groove 104, 104a: the first insulating layer 106: The first conductive layer 106a: Holes or pores 108: Protective layer 110: Second insulating layer 112, 200: the second conductive layer 114, 202: The first electrode 114a: Part 1 114b: Part II 116: The third insulating layer 118: the third conductive layer 120: Second electrode 122: the first doped region 124: the second doping region 126: Fourth insulating layer 128: Contact window 130: Doping region 132: Conductive layer

1A to 1G are cross-sectional schematic diagrams illustrating a manufacturing process of a trench transistor according to an embodiment of the present invention. 2 is a schematic cross-sectional view of a trench transistor according to another embodiment of the present invention. 3A to 3C are schematic cross-sectional views illustrating a manufacturing process of a trench transistor according to another embodiment of the present invention.

100: base

100a: Grassroots

100b: epitaxial layer

102: Groove

104: first insulating layer

106: The first conductive layer

108: Protective layer

Claims (19)

A method for manufacturing a trench transistor, comprising: forming a trench in a substrate; forming a first insulating layer on the sidewall and bottom surface of the trench; forming on the first insulating layer in the trench a first conductive layer, wherein holes or pores are formed in part of the first conductive layer; part of the first conductive layer is removed to remove the holes or pores; the first conductive layer in the trench forming a protective layer on the layer and on the first insulating layer on the sidewall of the trench; removing at least part of the first insulating layer between the protective layer and the sidewall of the trench; forming a second insulating layer on the exposed sidewalls of the trench; removing the protective layer; forming a second conductive layer on the first conductive layer; removing the second conductive layer above the second conductive layer a second insulating layer; a third insulating layer formed on the second conductive layer and on the sidewalls of the trench; a third conductive layer formed on the third insulating layer; and around the third conductive layer A first doped region is formed in the substrate. The method for manufacturing a trench transistor according to claim 1, wherein the protective layer comprises a silicon nitride layer. The method for manufacturing a trench transistor according to claim 1, wherein the protective layer fills the trench. The method for manufacturing a trench transistor according to claim 1, wherein the substrate comprises a base layer and an epitaxial layer formed on the base layer, and the trench is located in the epitaxial layer. The method for fabricating a trench transistor according to claim 1, wherein after removing a portion of the first insulating layer between the protective layer and the sidewall of the trench, the first insulating layer is The top surface is not lower than the top surface of the first conductive layer. The method for manufacturing a trench transistor according to claim 1, wherein the method for forming the second conductive layer comprises: filling the trench with a conductive material layer; and performing an etch-back process to remove part of the conductive material. The conductive material layer, wherein the top surface of the remaining conductive material layer is higher than the top surface of the first insulating layer. The method for manufacturing a trench transistor according to claim 1, wherein the method for forming the second conductive layer comprises: filling the trench with a conductive material layer; and performing an etch-back process to remove part of the conductive material. The conductive material layer, wherein the top surface of the remaining conductive material layer is not higher than the top surface of the first insulating layer. The method for manufacturing a trench transistor according to claim 1, wherein the method for forming the third insulating layer includes performing a thermal oxidation process. The method for manufacturing a trench transistor according to claim 1, wherein the bottom surface of the first doped region is not higher than the bottom surface of the third conductive layer. The method for manufacturing a trench transistor according to claim 1, wherein after forming the first doped region, further comprising: forming a second doped region in the first doped region, wherein the The conductivity type of the second doped region is different from that of the first doped region; a fourth insulating layer is formed on the substrate; a connection with the second doped region is formed in the fourth insulating layer a contact window; and a fourth conductive layer connected to the contact window is formed on the fourth insulating layer. The method for manufacturing a trench transistor according to claim 10, wherein after the fourth insulating layer is formed and before the contact window is formed, a third doped region is further formed under the contact window, And the conductivity type of the third doped region is the same as the conductivity type of the first doped region. The method for manufacturing a trench transistor according to claim 1, wherein a thickness of a portion of the first insulating layer located on the bottom surface of the trench is greater than that of the first insulating layer located on the trench The thickness of the part on the side wall. A trench-type transistor, comprising: a substrate with a trench; a first electrode disposed at the lower portion of the trench; an insulating layer disposed between the first electrode and the sidewall and bottom surface of the trench; a second electrode, disposed on the first electrode; an inter-gate dielectric layer disposed between the first electrode and the second electrode; a gate dielectric layer disposed between the second electrode and the substrate; and a main body region disposed between the second electrode In the surrounding substrate, wherein the substrate includes a base layer and an epitaxial layer disposed on the base layer, and the trench is located in the epitaxial layer. The trench transistor of claim 13, wherein a thickness of a portion of the insulating layer on a bottom surface of the trench is greater than a thickness of a portion of the insulating layer on a sidewall of the trench. The trench transistor of claim 13, wherein the first electrode includes a first portion and a second portion located on the first portion, and the width of the second portion is greater than the width of the first portion. The trench transistor of claim 15, further comprising a second insulating layer disposed between the second portion and the substrate. The trench transistor of claim 13, wherein a bottom surface of the body region is no higher than a bottom surface of the second electrode. The trench transistor according to claim 13, further comprising: a source region, disposed in the body region; an interlayer dielectric layer, disposed on the substrate; a contact window, disposed in the interlayer dielectric a conductive layer in the layer and electrically connected with the source region; and a conductive layer disposed on the interlayer dielectric layer and electrically connected with the contact window. The trench transistor according to claim 13, further comprising a doping region disposed below the contact window and electrically connected to the contact window, wherein the conductivity type of the doping region is the same as that of the body The conductivity types of the regions are the same.

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