JPH02206172A - Horizontal type conductivity modulating mosfet and method of controlling same - Google Patents

Abstract

PURPOSE:To enhance conductivity modulation in the ON state and to extinguish the conductivity modulation quickly in transistion from the ON to OFF state by providing a lead-out electrode in contact with an N<+>type buffer layer. CONSTITUTION:On the surface of an N<->type substrate 1 of the first conductivity type, there are provided a first region (P-type well) 2 of the second conductivity type and a second region (N<+>type buffer layer) 9 of the first conductivity type which are spaced from each other by a predetermined distance. On the surface of the P-type well 2, there are provided a third highly doped region (P<++>type contact layer) 3 of the second conductivity type and a fourth region (N<+>type source layer) 4 of the first conductivity type. On the surface of the buffer layer 9, there is provided a fifth highly doped region (P<+>type drain layer) 8 of the second conductivity type which is in contact with a drain electrode 10. A lead- out electrode 11 is provided in contact with the buffer layer 9. ln the ON state, a forward voltage is applied to the PN junction between the second and fifth regions. In the transition from the ON to OFF state, a reverse voltage is applied. In this manner, conductivity modulation can be enhanced in the ON state, and the conductivity modulation can be extinguished quickly in the OFF state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lateral conductivity modulated MOSFET in which the base current of a lateral bipolar transistor is supplied by a channel current of a MOSFET, and a control method thereof.

[Conventional technology]

A conductivity modulated MOS FET is an insulated gate bipolar transistor (Insulated Gate B
Since it is also called (ipolartransistor), it will be abbreviated as IGBT hereinafter. IGBTs are known as voltage-driven bipolar devices, and were initially developed as vertical devices, but recently horizontal IGBTs have been developed. This is because a vertical IGBT allows current to flow between the front and back surfaces of the semiconductor substrate, whereas a horizontal IGBT is formed using only one side of the semiconductor substrate. This is because it is simple and easy to connect with integrated circuits on the same board.

Figure 2 shows a conventional horizontal N-channel I GET, with N
- The surface of the P well 2 provided on one side of the substrate 1 has P
A +4 layer 3 and an N'' source layer 4 in contact with it are provided, and a source electrode 5 connected to a source terminal S is provided on both layers.
are in contact. A polycrystalline silicon gate electrode 7 is provided between the source layer 4 and the N-substrate region 1 via a gate oxide film 6, and is connected to the gate terminal G. N+ surrounding the P well layer 2 and the P'' drain layer 8 with a space therebetween.
A buffer layer 9 is arranged, and a drain electrode 10 connected to the drain terminal is in contact with the P'' layer 8.

In this IGBT, a voltage is applied to the gate electrode 7, and the surfaces of the two layers 2 immediately below it are inverted to form an N channel.
Electrons are introduced into the N- layer 1 from the N+ source layer 4. In response, holes are introduced from the P'' layer 8 on the drain side into the N- layer 1 through the N'' buffer layer 9 so as to satisfy the neutrality condition. In this way, carriers accumulate in the N- layer 8, resulting in conductivity modulation.

FIG. 3 is a potential barrier diagram showing a path through which holes 31 are introduced from the drain P3 layer 8 to the N− layer 1 through the 'N buffer layer 9. Previously, N゛buff 21
By changing the resistivity of the layer 9, that is, changing the Fermi level, the hole P″ is transferred from the drain layer 8 to N″
The potential barrier to the buffer layer 9 was controlled. Specifically, increasing the specific resistance of the N'buff 1 layer lowers the potential barrier, and lowering the specific resistance increases the potential barrier.

[Problem to be solved by the invention]

IGBTs are actually often used as switching elements, and in this case, it is desirable to cause conductivity modulation as much as possible in the on state, that is, to make the on-resistance as small as possible. And on the other hand,
When transitioning from the on state to the off state, it is desired to transition to the off state as quickly as possible, that is, a fast switching time is required.

In view of these requirements, the specific resistance and thickness of the N1 buffer layer 9 are taken into consideration, and a lifetime killer is introduced to obtain the characteristics. That is, the reality is that the optimum value is determined by adjusting both the degree of conductivity modulation and the manner in which carriers are annihilated by the lifetime killer.

In this way, the N+ buffer layer 9 merely functions as a stopper for the depletion layer to maintain the withstand voltage (IGET
We are pursuing a major role in switching. However, the impurity concentration and thickness of the N''' buffer layer 9 are uniquely determined, and under these conditions, if a large number of lifetime killers are added, the switching time becomes faster, but the on-resistance increases, and the lifetime killer is If less is added, the switching time will be slower, but the on-resistance will be smaller, and there is a trade-off relationship between the switching time and the voltage drop in the on-state.

The present invention eliminates this trade-off and provides a lateral IGBT and its lateral IGBT that modulates the conductivity as much as possible in the on state and eliminates the conductivity modulation as quickly as possible when switching to the off state. The purpose is to provide a control method.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a method in which a first region of a second conductivity type and a second region of a first conductivity type are selectively provided on the surface of a substrate of a first conductivity type with a low impurity concentration. A third region of the second conductivity type and a fourth region of the first conductivity type, both of which have a high impurity concentration, are selectively formed on the surface of the first region. The four regions are short-circuited by a source electrode, a gate electrode is provided on the surface of the first region between the fourth region and the substrate region via an oxide film, and a drain electrode is in contact with the surface of the second region. Horizontal IGBT in which a fifth region of the second conductivity type with high impurity concentration is selectively formed
In this case, it is assumed that the extraction electrode contacts the second region. In the on state, a forward voltage is applied to the PN junction between the second region and the fifth wi region via the drain electrode and the extraction electrode. In the switching state from on to off, a voltage in the opposite direction is applied to the PN junction between the second region and the fifth region via the drain electrode and the extraction electrode.

[Effect]

Since a dedicated extraction electrode is provided in the second region, it is possible to apply a DC voltage with appropriate polarity between the fifth region, which is the drain layer, and the second region, which is the buffer layer. The potential barrier can now be controlled,
Corresponding to the on state, it is easy to inject one carrier to increase the conductivity modulation, and corresponding to the switching state from on to off, the injection of one carrier and the ejection of the other carrier are controlled, thereby increasing the conductivity. It becomes possible to quickly eliminate the modulation.

〔Example〕

FIG. 1 shows a horizontal N-channel IGBT according to an embodiment of the present invention.
shows. The layer structure formed within the substrate 1 is the same as the conventional example shown in FIG. That is, a P well (with a width of 40 to 50 Ω and a surface impurity concentration of 5
first region) 2 and surface impurity concentration of approximately 10”/cd N
Four buffer layers (second regions) 9 are formed at intervals d of 50 to 100 −. In P-well 2, impurity is further diffused from the surface to a depth of 4 to 5μ1 and the surface impurity concentration is 10.
19/cd or more P++ contact layer (third region) 3 and depth 1/IWl or less 1 surface impurity concentration approximately 10”/-〇N
Four source layers (fourth regions) 4 are provided. on the other hand,
The N+ buffer layer 9 also has a width of 20~ due to impurity diffusion from the surface.
A P drain layer (fifth region) 8 with a depth of 4 to 5-1 and a surface impurity concentration of about 10''/- is provided.

The layer between the N''' source layer 4 and the N-substrate 1 exposed at the surface has a thickness of too.

A gate electrode 7 with a thickness of 1n is formed of polycrystalline silicon with an impurity concentration of 10"/cd through a human gate oxide film 6. Furthermore, it contacts the P+4 layer 3 and the N+ source layer 4 to short-circuit both layers. source electrode 5.P drain 1147
The layer 8 drain electrode 10 is N'buffed 2 according to the present invention.
A single-layer contacting extraction electrode 11 is provided. Each electrode is made of M or Mo, and the source electrode 4 is connected to the source terminal S, the gate electrode 7 is connected to the gate terminal G, and the drain electrode 10 is connected to the drain terminal. A DC power supply 21 or 22 is connected between them.

Next, a method of controlling this IGBT will be described.

For example, in an IGET to which a voltage of 600 V is applied between the drain and the source, a potential barrier as shown in ta+ in FIG. 4 is realized from the viewpoint of causing as much conductivity modulation as possible in the on state. This is realized by applying a voltage of several to several tens of volts in the forward direction to the PN junction between the N'''' buffer layer and the P'' drain using the power source 21. This facilitates the injection of holes 31 from the P''' drain layer 8 to the N-layer J and the ejection of electrons 32 from the N-layer 1 to the P3 drain layer 8, making it possible to increase the conductivity modulation. Therefore, the on-voltage decreases.On the other hand, in the off-switching state, a potential barrier as shown in Figure 4 is realized.This is because the power supply 22 connects the N9 buffer layer and the P
4. This is achieved by applying a voltage of several to several tens of volts to the PN junction of the drain in the opposite direction. As a result, not only the injection of holes 31 from the Pl drain layer 8 to the N layer 1 is significantly restricted, but also the injection of holes 31 from the N− layer 1 to the P3
The electrons 32 discharged to the drain and in layers 8 are also significantly restricted, and as a result, the switching time can also be extremely shortened.

For example, if both the DC power supplies 21 and 22 are connected, the switching loss will be halved in IQBTs with the same on-voltage. However, it is also possible to connect only one of the DC power supplies 21 and 22 and utilize only the effect of one.

Although the above embodiments have been described with respect to a lateral N-channel IGBT, they can also be implemented in a similar manner to a P-channel IGBT in which the conductivity types of each layer are reversed. In this case, the polarity of the DC voltage applied between the drain electrode and the extraction electrode in the on-state and off-switching state is opposite to that of the above embodiment.

〔Effect of the invention〕

According to the present invention, in a vertical IGET, an extraction electrode is provided in the buffer layer from which the electrode cannot be extracted, and a forward or reverse voltage is applied to the PN junction between the drain layer and the buffer layer between the drain electrodes. By controlling the potential barrier, facilitating carrier injection in the on state, and restricting carrier injection or other carrier ejection in the off switching state, it is possible to reduce the on voltage or shorten the switching time. . Moreover, such effects can be controlled to any desired degree only by the magnitude of the applied voltage, and it is much easier to obtain an I GET with desired characteristics than by adjusting the resistivity of the buffer layer or the amount of lifetime killer conductivity. The effect is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a lateral rGBT according to an embodiment of the present invention, FIG. 2 is a sectional view of a main part of a conventional lateral IGET, and FIG. 3 is a sectional view of a conventional lateral rGBT. 4 (a) and (bl) are diagrams showing how the potential barrier shown in FIG. 3 changes due to voltage application according to an embodiment of the present invention.

Claims (3)

[Claims] (1) A first region of a second conductivity type and a second region of the first conductivity type are selectively located at a predetermined interval on a surface portion of a substrate of a first conductivity type with a low impurity concentration, A third region of the second conductivity type and a fourth region of the first conductivity type, both of which have a high impurity concentration, are selectively formed on the surface of the region, and the third region and the fourth region are short-circuited by the source electrode, and A gate electrode is provided on the surface of the first region between the fourth region and the substrate region via an oxide film, and a fifth region of the second conductivity type with a high impurity concentration and in contact with the drain electrode is provided on the second region. A lateral conductivity modulation type MOSFET that is selectively formed and characterized in that an extraction electrode contacts the second region. (2) The lateral conductivity according to claim 1, characterized in that a forward voltage is applied to the PN junction between the second region and the fifth region through the drain electrode and the extraction electrode in the on state. Control method of modulation type MOSFET. (3) P between the second region and the fifth region via the drain electrode and the extraction electrode in the switching state from on to off.
2. The method of controlling a lateral conductivity modulation type MOSFET according to claim 1, further comprising applying a voltage in a reverse direction to the N junction.