GB2295052A - Integrated circuits - Google Patents
Integrated circuits Download PDFInfo
- Publication number
- GB2295052A GB2295052A GB9523207A GB9523207A GB2295052A GB 2295052 A GB2295052 A GB 2295052A GB 9523207 A GB9523207 A GB 9523207A GB 9523207 A GB9523207 A GB 9523207A GB 2295052 A GB2295052 A GB 2295052A
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- ligbt
- ldmos
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- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The integrated circuit comprises a lateral insulated-gate bipolar transistor (LIGBT) having a cathode (35, 36, 37), an anode (34) and a gate (39, 40); and, a lateral double-diffusion metal-oxide-semiconductor (LDMOS) having a source (29, 30, 31), a drain (28) and a gate (33, 41). The LIGBT and the LDMOS are formed laterally on the same substrate (21) with the cathode (35, 36, 37) of the LIGBT being electrically connected to the source (29, 30, 31) of the LDMOS, and the anode (34) of the LIGBT being electrically connected to the drain (28) of the LDMOS. <IMAGE>
Description
SEMICONDUCTOR DEVICE
The present invention relates to a semiconductor device.
High voltage/high power semiconductor devices are well known. For integrated circuits, lateral versions are preferred. One known form is the lateral double-diffusion
MOS (LDMOS). The structure of a conventional LDMOS is shown in Figure 1. The device has a p- substrate 1 on which is formed an n- epitaxial layer 2. An n+ region 3 is formed on the surface of the n- epitaxial layer 2, this n+ region 3 forming the drain of the transistor. An electrode 4 is fixed to the n+ drain 3. A p well 5 is formed on the surface of the n- epitaxial layer 2 laterally displaced from the n+ drain 3. In the surface of the p well 5 are formed adjacent regions of p+ type 6 and n+ type 7. The n+ region 7 formed in the p well 5 acts as the source whilst the p well 5 itself acts as the body in which the MOS transistor gate controls surface channel conduction.An electrode 8 is fixed to the surface of the n+ source 7 and the adjacent p+ region 6. A further electrode 9 is fixed via an oxide layer 10 to the surface of the device so that it extends from the n+ source 7, over the portion of the p well 5 which extends to the surface of the device, and over the surface of the n- epitaxial layer 2, thereby forming the gate electrode 9.
The properties of the LDMOS are well known. The device is desirable since it is a lateral device with all of its electrodes on the surface, allowing easy interconnection with other circuit elements. However, the on-resistance of the device is relatively high because of the light doping of the n- epitaxial layer 2 which forms the drift region.
As an improvement over the LDMOS, another known lateral device is the lateral insulated gate bipolar transistor (LIGBT). The structure of a conventional LIGBT is shown in Figure 2. The device has a p- substrate 11 on which is formed an n- epitaxial layer 12. A p+ region 13 is formed on the surface of the n- epitaxial layer 12, this p+ region 13 forming the anode of the transistor. An electrode 14 is fixed to the p+ anode 13. A p well 15 is formed on the surface of the n- epitaxial layer 12 laterally displaced from the p+ anode 13 to form a gate and a gate electrode 16 is fixed via an oxide layer 17 to the p well 15. In the surface of the p well 15 are formed adjacent regions of p+ type 18 and n+ type 19 which provide the cathode. An electrode 20 is fixed to these p+ and n+ cathode regions 18,19.It should be noted that the gate electrode 16 extends from the n+ cathode region 19, over the portion of the p well 15 which extends to the surface of the device, to the surface of the n- epitaxial layer 12.
In addition, an n-type buffer region is formed under the p+ anode 13 to prevent punchthrough.
In the on-state of the LIGBT, minority carriers (holes in this case) are injected from the p+ anode 13 into the drift region formed in the n- epitaxial layer 12 between the anode and the cathode, thus modulating the conductivity of the drift region. Thus, the LIGBT is a bipolar device utilising conductivity modulation of the drift region.
This lowers the resistance of the drift region relative to a comparable LDMOS, making the LIGBT an attractive device for power IC applications since it provides high input impedance, high breakdown and low on-state resistance.
However, a serious disadvantage is that the injected minority carriers slow the switching speed of the LIGBT relative to the LDMOS because the switch-off time is determined by the recombination process of the injected minority carriers.
An object of the present invention is to provide a semiconductor device which has a low on-state resistance and which also allows fast switch-off.
According to the present invention, there is provided a semiconductor device, the device comprising:
a lateral insulated-gate bipolar transistor (LIGBT) having a cathode, an anode and a gate; and,
a lateral double-diffusion metal-oxide-semiconductor (LDMOS) having a source, a drain and a gate;
the LIGBT and the LDMOS being formed laterally on the same substrate with the cathode of the LIGBT being electrically connected to the source of the LDMOS, and the anode of the LIGBT being electrically connected to the drain of the LDMOS.
It will be understood that where mention is made of the respective drain/anode or source/cathode being electrically connected, this also embraces the situation where the respective drain/anode or source/cathode are held at the same potential or the same potential is applied to the respective drain/anode or source/cathode.
Preferably, the LIGBT and LDMOS are formed on the same substrate.
The anode of the LIGBT may be separated from the drain of the LDMOS by a trench well.
The cathode of the LIGBT may be separated from the source of the LDMOS by a trench well.
Where a trench well is used, the trench well may be filled with an oxide of the substrate. The connection between the respective drain and anode may be by a conductor positioned over the trench well.
The present invention also includes a method of operating a device as described above, comprising the steps of turning on the voltage to each of the gates, and subsequently turning off the LIGBT gate voltage followed by turning off the LDMOS gate voltage a finite period after turn-off of the LIGBT gate voltage.
An example of the present invention will be described with reference to the accompanying drawings, in which:
Fig. 1 is a schematic cross-sectional view of a conventional LDMOS;
Fig. 2 is a schematic cross-sectional view of a conventional LIGBT;
Fig. 3 is a schematic cross-sectional view of a first example of a device according to the present invention;
Fig. 4 is a diagram of an equivalent circuit to the device of Figure 3;
Fig. 5 is a diagram of a graph of simulated cathode current against anode voltage for the device of Figure 3;
Figs. 6 and 7 are diagrams of graphs of simulated anode voltage against time showing the turn-off characteristics of the device of Figure 3;
Fig. 8 is a diagram of a graph of simulated anode current against time showing the turn-off characteristics of the device of Figure 3;;
Fig. 9 is a schematic cross-sectional view of a second example of a device according to the present invention; and,
Fig. 10 is a schematic cross-sectional view of a third example of a device according to the present invention.
The device of Figure 3 consists generally of a lateral insulated-gate bipolar transistor (LIGBT) in parallel with a lateral double-diffusion metal-oxide-semiconductor (LDMOS) formed in parallel on a common substrate and divided by a trench well.
In particular, a p- substrate 21 has formed thereon an n- epitaxial layer 22. The n- epitaxial layer 22 is divided by a trench well 23 into two regions 22a, 22b. As can be seen from Figure 3, the trench well 23 extends fully through the n- epitaxial layer 22 to the p- substrate 21 in order to separate the respective n- layer regions 22a, 22b completely.
The trench well 23 may be formed by etching out the silicon of the n- epitaxial layer 22. An electrically insulating layer 24 is formed on the interior of the trench well 23 on the opposing faces 25, 26 of the respective nlayer regions 22a, 22b. The insulating layer 24 may be an oxide or some other compound of the substrate, e.g. Si02 or
Si3N4 where the substrate is silicon. The insulating layer 24 may completely fill the trench well 23. Alternatively, if the trench well 23 is relatively wide, it can be filled with some other material 27 such as silicon in order to fill the trench well 23 completely and to produce a plane surface to the device.
The portion of the device generally to the left of the trench well 23 in Figure 3 forms the LIGBT, whilst the portion generally to the right of the trench well 23 forms the LDMOS.
Thus, to the right side of the trench well 23 in
Figure 3, an n+ drain 28 is formed. Laterally outwards of the LDMOS drain 28 is formed a p well 29 in the surface of which are formed adjacent n+ and p+ regions 30, 31, the n+ and p+ regions 30, 31 forming the source of the LDMOS. An electrode 32 is fixed over the n+ and p+ regions 30, 31, this LDMOS source electrode 32 being connected to earth.
An oxide layer 33 is formed on the surface of the LDMOS nlayer 22b to extend from the n+ drain 28 over the p well 29 to the n+ region 30 of the LDMOS source.
Similarly, on the left side of the device, a p+ anode 34 of the LIGBT is formed in the surface of the LIGBT nlayer 22a. Laterally outwards of the p+ anode 34 of the
LIGBT is formed a p well 35 in the surface of which are formed adjacent n+ and p+ regions 36, 37 which together form the cathode of the LIGBT. As can be seen, the n+ region 36 of the LIGBT cathode is positioned on the trench well side of the p+ region 37 of the LIGBT cathode. An electrode 38 is fixed to the surface of the n+ and p+ regions 36, 37 of the LIGBT cathode, the LIGBT cathode electrode 38 being connected to earth. An oxide layer 39 is formed on the surface of the n- layer 22a of the LIGBT and extends from the p+ anode 34 over the p well 35 to the n+ region 36 of the LIGBT cathode.
Respective gate electrodes 40, 41 are fixed to the respective oxide layers 39, 33 of the LIGBT and the LDMOS.
Similarly, electrodes 42, 43 are fixed to the p+ anode 34 of the LIGBT and n+ drain 28 of the LDMOS, the anode electrodes 42, 43 themselves being electrically connected to each other as shown.
The operating characteristics of the device have been studied by using a simulation. For the simulation, the total width of the device (i.e. from left to right of
Figure 3) was 143cm. The width of the trench well 23 was 3mum. The doping of each of the n- drift layers 22a, 22b was 1015cm 3 and the doping of the p- substrate 21 was 7xlO13cm 3. The thickness of each of the gate oxide layers 39, 33 was 40nm.
In Figure 5 there is shown a graph of cathode current against anode voltage for the case where the voltage applied to each of the gate electrodes 40, 41 is 5V. The device shows typical LDMOS conduction up to an anode voltage of 0.7V. For anode voltages greater than 0.7V,
LIGBT conduction is dominant, though the transition between the two conduction mechanisms is quite smooth. Thus, the advantage of the low on-state resistance of a LIGBT is easily obtained by applying an anode voltage greater than 0.7V.
The structure under simulation had a breakdown voltage of 550V, which is probably limited by punchthrough breakdown. This could probably be improved by using an n buffer layer under the p+ anode 34 of the LIGBT.
The turn-off characteristics of the device were then investigated. In Figure 6, a graph of anode voltage against time is shown for the condition where the voltage applied to the LDMOS gate 41 is maintained at 5v, with an on-state current of 4x10 A/pm, and the voltage to the
LIGBT gate 40 is reduced from 5v to 0v in 40ns. As can be seen, the anode voltage rises to about 20v within 300ns.
During this period, the partitioning of device current between the LIGBT and the LDMOS changes from
I(LDMOS)/I(LIGBT) = 0.75/3.25 to I(LDMOS)/I(LIGBT) = 3.9/0.1 at t=300ns. Thus, substantially pure LDMOS operation is obtained approximately 300ns after the voltage applied to the LIGBT gate electrode 41 is reduced to zero.
After 300ns, the voltage applied to the LDMOS gate electrode 41 is reduced to zero. As shown in Figure 7, which is a diagram of a graph of anode voltage against time similar to Figure 6 but with the anode voltage shown on a much smaller scale, the anode voltage rises extremely rapidly when the voltage applied to the LDMOS gate electrode 41 is reduced to zero, the anode voltage rising to about 500v within 20ns. As shown in Figure 8, the anode current falls to a very small value within about 20 ns (i.e. in the period from 20ns to 40ns after the LDMOS gate electrode 41 is switched off) and the anode current falls practically to zero within a further 30 ns or so.
Accordingly, the device of the present invention, in which a LIGBT and LDMOS are in parallel, provides a very fast switching power device with a high breakdown voltage and low on-state resistance. The device is simply controlled by switching on and off the respective gate electrodes 40, 41.
A second example of a device according to the present invention is shown schematically in Figure 9. Indeed, in
Figure 9, several lateral devices of the invention are shown formed on the substrate in parallel. It will be appreciated that the device shown in Figure 3 can also be repeated across the same substrate to form multiple parallel devices on the same substrate.
In the following discussion of the device shown in
Figure 9 (and also of the device shown in Figure 10 and subsequently described), as much of the structure is similar to that of the device shown in Figure 3, the following description will be less detailed. Reference can be made to the drawings to determine the type and relative degree of doping for any particular region.
In Figure 9, an n- epitaxial layer 22 is formed on a p- substrate 21 as in the first example. The primary difference between the example of Figure 9 and the example of Figure 3 is that the cathodes/sources of the respective
LIGBT and LDMOS are separated by a trench well in the example of Figure 9, as opposed to the drain/anode of the respective transistors being separated by a trench well in the example of Figure 3. In Figure 9, there is shown a central trench well 50.
A cathode C1 for a LIGBT is formed on the left hand side of the central trench 50 in Figure 9. A source S2 for the LDMOS is formed on the right hand side of the trench well in Figure 9. The LIGBT cathode C1 and LDMOS source S2 are in themselves conventional and have been described above.
An anode Al for the LIGBT is provided to the left of the LIGBT source S1 in Figure 9. A drain D2 for the LDMOS is provided to the right of the LDMOS source S2 in Figure 9. Respective gate electrodes G1,G2 are fixed over the appropriate regions for the LIGBT and LDMOS as described above with reference to the example of Figure 3.
In Figure 9, an indication of the repeatability of the structure is given. In particular, further to the left of the LIGBT anode Al, there is provided a further LIGBT cathode structure C3 and corresponding gate G3. The anode for the second LIGBT is the aforementioned anode Al for the first LIGBT, which is therefore a shared anode. Further to the left of the second LIGBT cathode C3, a second trench well 51 is provided through the epitaxial layer 22 to separate the second LIGBT structure C3,G3,A1 from the rest of the device. For example, a gate and source structure for a LDMOS may be provided to the left of the second trench 51.
Similarly, a source S4 and gate G4 are provided for a second LDMOS to the right of the drain D2 of the first
LDMOS structure S2,G2,D2. The drain D2 is shared between the first and second LDMOS structures shown in Figure 9.
To the right of the source S4 of the second LDMOS is formed a third trench well 52 through the epitaxial layer 22 to separate the second LDMOS structure S4,G4,D2 from the rest of the device. To the right of the third trench well 52 may be provided a cathode and gate structure for a further
LIGBT, for example.
A third example of a device according to the present invention is shown in Figure 10. There is shown a LIGBT structure C5,G5,A5 adjacent to a LDMOS structure S6,G6,D6.
The cathode C5 and source S6 of the adjacent LIGBT and
LDMOS are common and connected to the p- substrate 21 by a deep p+ diffusion 60.
The LIGBT anode A5 is shared with a further LIGBT cathode C7 and gate G7 positioned to the left of the first
LIGBT structure C5,G5,A5 in Figure 10. Similarly, the
LDMOS drain D6 is shared with a gate G8 and source S8 of a further LDMOS, which is positioned to the right of the first LDMOS structure S6,G6,D6 in Figure 10.
Where multiple cell structures are used (i.e. where there are more than one LIGBT and LDMOS on a particular substrate), the device can be isolated by having deep p+ diffusions through the n- epitaxial layer 22 to the substrate 21 at the edges of the device adjacent a cathode/source of a LIGBT or LDMOS as the case may be.
The device can also be made with the doping types of all of the regions reversed compared to the device described above in order to obtain a device which can be operated with reverse cathode, anode and gate voltage polarities.
Claims (10)
1. A semiconductor device, the device comprising:
a lateral insulated-gate bipolar transistor (LIGBT) having a cathode, an anode and a gate; and,
a lateral double-diffusion metal-oxide-semiconductor (LDMOS) having a source, a drain and a gate;
the LIGBT and the LDMOS being formed laterally on the same substrate with the cathode of the LIGBT being electrically connected to the source of the LDMOS, and the anode of the LIGBT being electrically connected to the drain of the LDMOS.
2. A device according to claim 1, wherein the anode of the LIGBT is separated from the drain of the LDMOS by a trench well.
3. A device according to claim 2, wherein the connection between the respective drain and anode is by a conductor positioned over the trench well.
4. A device according to claim 1, wherein the cathode of the LIGBT is separated from the source of the LDMOS by a trench well.
5. A device according to claim 4, wherein the connection between the respective cathode and source is by a conductor positioned over the trench well.
6. A device according to any of claims 2 to 5, wherein the trench well is filled with an oxide of the substrate.
7. A device according to any of claims 2 to 5, wherein the trench well is filled with an oxide of the substrate, the oxide itself being filled with further material.
8. A device according to claim 1, wherein the cathode of the LIGBT is connected to the source of the LDMOS by a diffusion layer.
9. A method of operating a device according to any of claims 1 to 8, comprising the steps of turning on the voltage to each of the gates, and subsequently turning off the LIGBT gate voltage followed by turning off the LDMOS gate voltage a finite period after turn-off of the LIGBT gate voltage.
10. A semi-conductor device substantially as described with reference to any of Figures 3, 9 and 10 of the accompanying drawings.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9423423A GB9423423D0 (en) | 1994-11-14 | 1994-11-14 | Semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9523207D0 GB9523207D0 (en) | 1996-01-17 |
| GB2295052A true GB2295052A (en) | 1996-05-15 |
| GB2295052B GB2295052B (en) | 1998-07-15 |
Family
ID=10764708
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9423423A Pending GB9423423D0 (en) | 1994-11-14 | 1994-11-14 | Semiconductor device |
| GB9523207A Expired - Fee Related GB2295052B (en) | 1994-11-14 | 1995-11-13 | Integrated bipolar and field effect transistors |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9423423A Pending GB9423423D0 (en) | 1994-11-14 | 1994-11-14 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH08213617A (en) |
| GB (2) | GB9423423D0 (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2307343A (en) * | 1995-11-17 | 1997-05-21 | Int Rectifier Corp | IGBT with integrated control |
| US6133591A (en) * | 1998-07-24 | 2000-10-17 | Philips Electronics North America Corporation | Silicon-on-insulator (SOI) hybrid transistor device structure |
| US6307246B1 (en) | 1998-07-23 | 2001-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor resurf devices formed by oblique trench implantation |
| US6429077B1 (en) * | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| US7605446B2 (en) | 2006-07-14 | 2009-10-20 | Cambridge Semiconductor Limited | Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation |
| WO2010057340A1 (en) * | 2008-11-19 | 2010-05-27 | 深圳市联德合微电子有限公司 | Integrated circuit utilizing ligbt output stage |
| CZ302020B6 (en) * | 2000-05-16 | 2010-09-08 | Robert Bosch Gmbh | Semiconductor power component |
| CN102593127A (en) * | 2012-02-27 | 2012-07-18 | 电子科技大学 | Composite power semiconductor device |
| DE102011002857A1 (en) * | 2011-01-19 | 2012-07-19 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Semiconductor device with a BiLDMOS or SOI-BiLDMOS transistor, and cascode circuit |
| US8698238B2 (en) | 2011-12-12 | 2014-04-15 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of forming the same |
| CN107564814A (en) * | 2016-06-30 | 2018-01-09 | 株洲中车时代电气股份有限公司 | A kind of method for making power semiconductor |
| CN107564952A (en) * | 2016-06-30 | 2018-01-09 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007318062A (en) * | 2006-04-27 | 2007-12-06 | Matsushita Electric Ind Co Ltd | High withstand voltage semiconductor switching device |
| JP5284077B2 (en) * | 2008-12-26 | 2013-09-11 | 株式会社日立製作所 | Semiconductor device and power conversion device using the same |
| CN104916674B (en) * | 2015-04-17 | 2017-10-31 | 东南大学 | A kind of intensifying current type landscape insulation bar double-pole-type transistor |
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1994
- 1994-11-14 GB GB9423423A patent/GB9423423D0/en active Pending
-
1995
- 1995-11-01 JP JP7284856A patent/JPH08213617A/en active Pending
- 1995-11-13 GB GB9523207A patent/GB2295052B/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2307343A (en) * | 1995-11-17 | 1997-05-21 | Int Rectifier Corp | IGBT with integrated control |
| US5798538A (en) * | 1995-11-17 | 1998-08-25 | International Rectifier Corporation | IGBT with integrated control |
| GB2307343B (en) * | 1995-11-17 | 2000-11-15 | Int Rectifier Corp | IGBT with integrated control |
| US6307246B1 (en) | 1998-07-23 | 2001-10-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor resurf devices formed by oblique trench implantation |
| US6133591A (en) * | 1998-07-24 | 2000-10-17 | Philips Electronics North America Corporation | Silicon-on-insulator (SOI) hybrid transistor device structure |
| US6429077B1 (en) * | 1999-12-02 | 2002-08-06 | United Microelectronics Corp. | Method of forming a lateral diffused metal-oxide semiconductor transistor |
| CZ302020B6 (en) * | 2000-05-16 | 2010-09-08 | Robert Bosch Gmbh | Semiconductor power component |
| US7605446B2 (en) | 2006-07-14 | 2009-10-20 | Cambridge Semiconductor Limited | Bipolar high voltage/power semiconductor device having first and second insulated gated and method of operation |
| WO2010057340A1 (en) * | 2008-11-19 | 2010-05-27 | 深圳市联德合微电子有限公司 | Integrated circuit utilizing ligbt output stage |
| DE102011002857A1 (en) * | 2011-01-19 | 2012-07-19 | Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik | Semiconductor device with a BiLDMOS or SOI-BiLDMOS transistor, and cascode circuit |
| US8698238B2 (en) | 2011-12-12 | 2014-04-15 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of forming the same |
| CN102593127A (en) * | 2012-02-27 | 2012-07-18 | 电子科技大学 | Composite power semiconductor device |
| CN102593127B (en) * | 2012-02-27 | 2014-04-09 | 电子科技大学 | Composite power semiconductor device |
| CN107564814A (en) * | 2016-06-30 | 2018-01-09 | 株洲中车时代电气股份有限公司 | A kind of method for making power semiconductor |
| CN107564952A (en) * | 2016-06-30 | 2018-01-09 | 株洲中车时代电气股份有限公司 | A kind of power semiconductor |
| CN107564814B (en) * | 2016-06-30 | 2020-11-10 | 株洲中车时代半导体有限公司 | Method for manufacturing power semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9523207D0 (en) | 1996-01-17 |
| JPH08213617A (en) | 1996-08-20 |
| GB2295052B (en) | 1998-07-15 |
| GB9423423D0 (en) | 1995-01-11 |
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