CN107564814A - A kind of method for making power semiconductor - Google Patents
A kind of method for making power semiconductor Download PDFInfo
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- CN107564814A CN107564814A CN201610503033.7A CN201610503033A CN107564814A CN 107564814 A CN107564814 A CN 107564814A CN 201610503033 A CN201610503033 A CN 201610503033A CN 107564814 A CN107564814 A CN 107564814A
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Abstract
A kind of method for making power semiconductor, including：Step 1: the semiconductor layer of the first preset thickness is formed on substrate；Step 2: being performed etching to the semiconductor layer of the first preset thickness, first object table top is obtained；Step 3: the second polysilicon layer is formed on first object table top；Step 4: semiconductor layer is continuously formed on the second polysilicon layer, and the semiconductor layer to ultimately forming performs etching, and obtains the second target mesa, so as to form gate oxide；Step 5: the first polysilicon layer is formed in the second target mesa.The gate oxide for the power semiconductor for making to obtain using this method has been internally formed floating polysilicon layer, therefore field plate structure has been internally formed it in gate oxide, improve the pressure-resistant performance of device, so that the distance between the doping concentration of enhanced carrier layer and cellular can further increase, reduce the base resistance and JFET areas resistance of device, so as to reduce on-state voltage drop, and realize on-state voltage drop and pressure-resistant good compromise.
Description
Technical field
The present invention relates to electric and electronic technical field, specifically, is related to a kind of power semiconductor.
Background technology
Power semiconductor is the basis of Power Electronic Technique and its application apparatus, is to promote converters to develop
Main source.Power semiconductor is in the heart status of modern power electronic converter, its reliability, cost and property to device
It can play a very important role.Wherein, triode thyristor, gate turn off thyristor and insulated gate bipolar transistor (IGBT)
Successively it is referred to as the development platform of power semiconductor.
Current planar gate IGBT, generally use enhanced carrier layer realize stronger conductance modulation, so as to reduce
The on-state voltage drop of device.The doping concentration of enhanced carrier layer is higher, and conductance modulation effect is stronger, and on-state voltage drop is lower.So
And the increase of enhanced carrier layer doping concentration, the pressure-resistant performance of device can be sacrificed.In order to take into account the pressure-resistant performance of device,
Doping concentration with regard to needing carefully to optimize enhanced carrier layer, being allowed to can not be too high.Simultaneously, it is also necessary to optimize first intercellular
Distance, being allowed to can not be excessive.This is obviously unfavorable for the production of power semiconductor, greatly limit the production effect of power semiconductor
Rate.
The content of the invention
To solve the above problems, the invention provides a kind of method for making power semiconductor, methods described includes：
Step 1: the semiconductor layer of the first preset thickness is formed on substrate；
Step 2: being performed etching to the semiconductor layer of first preset thickness, first object table top is obtained；
Step 3: form the second polysilicon layer on the first object table top；
Step 4: semiconductor layer is continuously formed on second polysilicon layer, and the semiconductor layer to ultimately forming enters
Row etching, obtains the second target mesa, so as to form gate oxide；
Step 5: form the first polysilicon layer in second target mesa.
According to one embodiment of present invention, the gate oxide has a multi-thickness, and with semiconductor source electrode
The trend gradually increased is presented in the increase of distance between area, the thickness of the gate oxide.
According to one embodiment of present invention, the thickness of the most thick opening position of the gate oxide after etching is its most thin opening position
More than 8 times of thickness.
According to one embodiment of present invention, the thickness of the first object table top is along first end to the second linear increasing
Greatly.
According to one embodiment of present invention, second target mesa includes the multiple intervals being sequentially connected,
Each odd number interval is flat bed section in the multiple interval, and each even number interval is oblique interval；Or,
Each odd number interval is oblique interval in the multiple interval, and each even number interval is flat bed section；
Wherein, the flat bed section keeps constant interval for the thickness of each opening position, and the tiltedly interval is that thickness is linear
The interval of increase.
According to one embodiment of present invention, second target mesa includes the multiple intervals being sequentially connected, described more
Individual interval forms step structure, wherein, the thickness of the interval more remote apart from the first end is bigger.
According to one embodiment of present invention, the length of the farthest interval of first end described in distance is small in the multiple interval
In the half of half cellular width of power semiconductor.
According to one embodiment of present invention, the thickness of first polysilicon layer and/or the second polysilicon layer position
Spend equal.
According to one embodiment of present invention, before the first object table top is formed, methods described is also in the substrate
Upper formation first window, and the enhanced current-carrying with the first conduction type is formed in the substrate using the first window
Sublayer, P- bases are formed in the enhanced carrier layer.
According to one embodiment of present invention, after first polysilicon layer is formed, methods described is also in the polycrystalline
The second window is formed in silicon layer and gate oxide, and utilize second window to be formed in the substrate there is the first conductive-type
The enhanced carrier layer of type, P- bases are formed in the enhanced carrier layer.
According to one embodiment of present invention, after the P- bases are formed, methods described is formed in also described P- bases
Source area with the first conduction type and the ohmic contact regions with the second conduction type, wherein, the Ohmic contact position
In the centre position of the P- bases.
According to one embodiment of present invention, the thickness of the ohmic contact regions is more than the thickness of the source area.
According to one embodiment of present invention, methods described also includes：
Cushion is formed on another surface of the substrate；
Collector area is formed on the cushion.
According to one embodiment of present invention, methods described also includes：
Short dot is formed on the collector area.
The gate oxide of power semiconductor provided by the present invention has been internally formed floating polysilicon layer, therefore in grid
Oxide layer has been internally formed field plate structure, improves the pressure-resistant performance of device, so that the doping of enhanced carrier layer is dense
The distance between degree and cellular can further increase, and the base resistance and JFET areas resistance of device be reduced, so as to reduce
On-state voltage drop, and realize on-state voltage drop and pressure-resistant good compromise.
Meanwhile gate oxide linearly changes in power semiconductor provided by the present invention, therefore it can effectively be avoided
The high convex and discontinuous defect of device surface present in existing power semiconductor.Compared to existing power semiconductor, this hair
Bright the power semiconductor that passes through is more smooth, and its technique (mark alignment, photoetching and etching etc.) difficulty is effectively reduced, this
Sample also helps to improve the performance of power semiconductor and the reliability of chip package function.
The gate oxide of power semiconductor provided by the present invention can be carried out using the photoetching of standard with etching technics
Make, without additionally developing specific photoetching and etching technics for step gates structure, therefore process exploitation cost can be saved.
Meanwhile gate oxide is the shallower structure of the ratio formed using multiple substep photoetching and etching, therefore progress can be avoided single
Secondary deep etching, this also just reduces technology difficulty.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
Obtain it is clear that or being understood by implementing the present invention.The purpose of the present invention and other advantages can be by specification, rights
Specifically noted structure is realized and obtained in claim and accompanying drawing.
Brief description of the drawings
Accompanying drawing shows the various embodiments of each aspect of the present invention, and they are used to explain this hair together with specification
Bright principle.Those skilled in the art will appreciate that specific embodiment shown in the drawings is only exemplary, and they
It is not intended to limit the scope of the present invention.It should be appreciated that in some examples, an element being illustrated can also be designed to more
Individual element, or multiple element can also be designed to an element.In some examples, it is shown as the inside of another element
The element of part can also be implemented as the external component of another element, and vice versa.For clearer, this hair in detail
Bright exemplary embodiment is so that those skilled in the art can understand more to the advantages of each aspect of the present invention and its feature
Add thoroughly, now accompanying drawing is introduced, in the accompanying drawings：
Fig. 1 is the structural representation of existing power semiconductor；
Fig. 2 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 3 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 4 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 5 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 6 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 7 is the structural representation of the cellular of power semiconductor half according to an embodiment of the invention；
Fig. 8, Fig. 9 and Figure 10 are the flows according to an embodiment of the invention for making power semiconductor as shown in Figure 5
Figure.
Embodiment
Embodiments of the present invention are described in detail below with reference to drawings and Examples, and how the present invention is applied whereby
Technological means solves technical problem, and the implementation process for reaching technique effect can fully understand and implement according to this.Need to illustrate
As long as not forming conflict, each embodiment in the present invention and each feature in each embodiment can be combined with each other,
The technical scheme formed is within protection scope of the present invention.
Meanwhile in the following description, many details are elaborated for illustrative purposes, to provide to of the invention real
Apply the thorough understanding of example.It will be apparent, however, to one skilled in the art, that the present invention can not have to tool here
Body details or described ad hoc fashion are implemented.
In addition, can be in the department of computer science of such as one group computer executable instructions the flow of accompanying drawing illustrates the step of
Performed in system, although also, show logical order in flow charts, in some cases, can be with different from herein
Order perform shown or described step.
Fig. 1 shows the structural representation of existing plane grid-controlled type power semiconductor.As shown in figure 1, existing work(
Rate semiconductor devices includes：Substrate 101, enhanced carrier layer 102, P- bases 103, N+ source areas 104, ohmic contact regions
105th, gate oxide 106 and polysilicon layer 107.Wherein, substrate 101 is the first conduction type, Qi Wei N- areas.Enhanced current-carrying
Sublayer 102 is formed in substrate 101, and it is the first conduction type, and is N areas；P- bases 103 are formed in enhanced carrier
In layer 102, it is the second conduction type；N+ source areas 104 are formed in P- bases 103, and it is the first conduction type；P+ ohms
Ohmic contact regions 105 are formed in P- bases, and it is the second conduction type；Polysilicon layer 107 is formed on gate oxide 106.
For plane grid-type power semiconductor as shown in Figure 1, if between the adjacent cellular of any two
Distance L it is too small, then can then cause the resistance in JFET areas to increase, so as to influence the on-state voltage drop of device.And if two phases
The distance between adjacent cellular L is excessive, then can influence the pressure-resistant performance of device.
In addition, in order to reduce the on-state voltage drop of device, existing most efficient method is as shown in Figure 1 in P- bases 103
One enhanced carrier layer 102 of outer setting.However, the doping concentration of enhanced carrier layer 102 must rationally design, otherwise will
Have a strong impact on the voltage endurance of device.
In order to solve above-mentioned two problems, existing production firm has to carefully adjust the spacing of cellular and enhanced load
Flow the doping concentration of sublayer, with cause the spacing of cellular will not excessive while enhanced carrier layer doping concentration will not be too high
(such as the doping concentration of enhanced carrier layer is arranged to 1e15/cm3 magnitudes).However, this method is to optimizing semiconductor
The tradeoff of the on-state voltage drop of device and pressure-resistant performance is than relatively limited.
In addition, the voltage endurance of non-parallel planes knot can be improved using field plate structure, therefore this method can also be used
In structure cell.The relatively large cellular of the enhanced carrier layer with higher-doped concentration and two neighboring interval it
Between use field plate structure, can improve because enhanced carrier layer doping concentration uprises and cellular spacing becomes big and brought resistance to
The adverse effect for pressing characteristic to decline.But field plate structure is set on the gate oxide of routine, due to the thickness of gate oxide
Limit and become infeasible.
Meanwhile for existing plane grid-controlled type power semiconductor, its gate oxide employ one it is trapezoidal
Design, pass through close to raceway groove opening position set one layer of thin gate oxide, away from raceway groove opening position set one
Thickness gate oxide, gate capacitance, the effect of optimization power semiconductor switching device characteristic are reduced to realize, while can also adjusted
Threshold voltage characteristic.However, how design of thin, the ratio of thick grating oxide layer (packet length, the ratio of thickness), grid can be directly affected
The size of electric capacity, and then influence the optimal compromise of switching characteristic and threshold voltage characteristic.It is also, most importantly, existing
The design of gate oxide, the pattern of device surface is influenceed very big, it is easy to cause the high convex of device surface and do not connect
It is continuous, so as to influence the planarization of device surface.This not only causes the technique of device to realize that difficulty increases, and can also influence device performance
And the reliability of chip package.
For the above-mentioned problems in the prior art, the invention provides a kind of new power semiconductor, the work(
Formed with floating polysilicon layer in the gate oxide of rate semiconductor devices, so that field plate structure has been internally formed in gate oxide,
The pressure-resistant performance of device is improved, so that the distance between the doping concentration of enhanced carrier layer and cellular can enter one
Step increase, reduces the base resistance and JFET areas resistance of device, so as to reduce on-state voltage drop, and realize on-state voltage drop with
Pressure-resistant good compromise.
In order to more clearly illustrate the structure of power semiconductor provided by the present invention and advantage, below in conjunction with
Power semiconductor provided by the present invention is further detailed different embodiments, simultaneously as the present invention is carried
The structure of the power semiconductor of confession is symmetrical, therefore is described for convenience, is carried out in following examples with half structure cell
Explanation.
Embodiment one：
Fig. 2 shows the structural representation of half cellular of the power semiconductor that the present embodiment is provided.
As shown in Fig. 2 the power semiconductor that the present embodiment is provided preferably includes：Substrate 201, the first conductive region,
Gate oxide 202, the first polysilicon layer 203a and the second polysilicon layer 203b.Wherein, in the present embodiment, the first conductive region shape
Into in substrate 201, it includes：Enhanced carrier layer 204 with the first conduction type, the P- with the second conduction type
Basic unit 205, the source area 206 with the first conduction type and the ohmic contact regions 207 with the second conduction type.This implementation
In example, the conduction type of substrate 201 is the first conduction type.
In the present embodiment, enhanced carrier layer 204 is formed in substrate 201.Making enhanced carrier layer 204
During, deposit layer of oxide layer on the substrate 201 first, the thickness of the oxide layer is preferably no more than 0.5 μm, then to institute
The oxide layer of formation performs etching, so as to produce the injection of enhanced carrier layer 204/doping window.Obtain it is enhanced
After the injection of carrier layer 204/doping window, enhanced carrier layer is carried out into substrate 201 using the injection/doping window
Injection/doping, high temperature propulsion/diffusion is then carried out, so as to form a doping concentration enhanced current-carrying higher than substrate 201
Sublayer 204.In the present embodiment, the doping concentration of enhanced carrier layer 204 is preferably more than 1e15/cm3。
P- basic units are further formed after enhanced carrier layer 204 is obtained, it is necessary in enhanced carrier layer 204
205.In the present embodiment, because the injection using enhanced carrier layer 204/doping window forms enhanced carrier layer 204
During, high temperature promotes technique that the thickness of oxide layer is added, therefore now needs first to the increased oxidation of thickness
Layer performs etching, to form the injection of P- bases/doping window.
After injection/doping window of P- bases is formed, you can carry out P- to enhanced carrier layer 204 using the window
Injection/doping of base, high temperature propulsion/DIFFUSION TREATMENT is then carried out, so as to form P- bases in enhanced carrier layer 204
205.In the present embodiment, the doping concentration of P- bases 205 is preferably e17/cm3Magnitude.
It is pointed out that in other embodiments of the invention, according to being actually needed, enhanced carrier layer 204 and/
Or the doping concentration of P- bases 205 can also be other reasonable values, the invention is not restricted to this.
Similarly, source area 206 and ohmic contact regions can be formed respectively in P- bases 205 using same method
207, its specific forming process will not be repeated here.In the present embodiment, the thickness of ohmic contact regions 207 is preferably more than source area
206 thickness.
As shown in Fig. 2 in the present embodiment, gate oxide 202 is formed on the substrate 201, and gate oxide 202 is close to source
One end of polar region 206 contacts with source area 206.First polysilicon layer 203a is formed on the surface of gate oxide 202.Second polysilicon
Layer 203b is formed to be located above the first conductive region (preferably in the inside of gate oxide 202, the second polysilicon layer 203b one end
Ground is positioned at the enhanced top of carrier layer 204), the other end aligns with the cellular right hand edge of power semiconductor.In the present embodiment, the
One polysilicon layer 203a and/or the thickness of the second polysilicon layer 203b positions preferably keep constant.
In order to avoid existing power semiconductor because thin, thickness portion the thickness difference of gate oxide is excessive and caused by technique
The problem of difficulty is big, process uniformity control is poor, and thus caused power semiconductor surface is high convex and discontinuous
Problem, the gate oxide for the power semiconductor that the present embodiment is provided employ new table top grid structure.Specifically, such as Fig. 2
Shown, gate oxide 202 has multi-thickness, and with the increase with the distance between the first conductive region center line, grid oxygen
The thickness for changing layer linearly increases.
In the structure cell of power semiconductor half as shown in Figure 2, the starting point (left end point i.e. in figure) of gate oxide 202
Above source area 206, terminal (right endpoint i.e. in figure) aligns with cellular edge.In the present embodiment, gate oxide 202
Thickness is, gate oxide thickness D start position at linearly increasing by origin-to-destination1Preferably general thickness (example
Such as 0.1 μm), thickness D of the gate oxide at final position2Preferably more than 10 times (such as 1 μm) of starting point thickness.
It is pointed out that in other embodiments of the invention, according to being actually needed, gate oxide 202 is in starting point position
The thickness for putting place can also be other Rational Thickness, while the thickness at final position can also be that other are more than start position
The value (such as 8 times that thickness of the gate oxide at final position is thickness at start position are with first-class) of the thickness at place, this hair
Bright not limited to this.
, can be to carry out gate oxide after the making of source area 206 and ohmic contact regions 207 is completed in the present embodiment
202nd, the first polysilicon layer 203a and the second polysilicon layer 203b making.Specifically, in the present embodiment, first in substrate
201 and first to form a thickness on conductive region be D3SiO2Layer, then using multiple photoetching and the method for etching, so that
The first object table top that one thickness linearly changes.In the present embodiment, thickness D3Value be preferably configured to thickness D2Value
90%.
After the first object table top of the thickness linear change is obtained, the more of a specific thicknesses are formed in the target mesa
Crystal silicon layer (i.e. the second polysilicon layer 203b).Then continuing to make SiO on the polysilicon layer2Layer so that the SiO2The thickness of layer
Spend for D2.By to the SiO2Layer carries out multiple photoetching and etching, so as to form the second target mesa that thickness linearly changes.
The polysilicon layer (i.e. the first polysilicon layer 203a) of a specific thicknesses is finally formed in the second target mesa, and it is more to carry out N-type
Doped polycrystal silicon.In the present embodiment, the thickness of polysilicon layer is preferably less than 0.5 μm, and its doping concentration is preferably in 1e19/cm3
More than.Certainly, in other embodiments of the invention, according to being actually needed, the thickness and doping concentration of polysilicon layer may be used also
Think other reasonable values, the invention is not restricted to this.
After completing said process, in the present embodiment, the portion also to being covered on ohmic contact regions 207 and source area 206
Divide SiO2Layer and polysilicon layer carry out photoetching or etching, so as to ultimately form power semiconductor structure as shown in Figure 2.
It is pointed out that in the present embodiment, the table of the second polysilicon layer 203b shape preferably with gate oxide 202
Face shape is similar.Certainly, in the other embodiment of invention, the second polysilicon layer 203b shape can also be other reasonable shapes
Shape, the invention is not restricted to this.
It is also desirable to, it is noted that in other embodiments of the invention, the material of gate oxide can also select it
His reasonable material, the invention is not restricted to this.In addition, in other embodiments of the invention, source area 206 and ohmic contact regions
207 can also be made after gate oxide 202 and polysilicon layer 203 complete, due to its specific manufacturing process sheet
Art personnel are by foregoing description it is known that therefore will not be repeated here.
In the present embodiment, power semiconductor is also including the cushion 208 with the first conduction type and conductive with second
The collector area 209 of type.Wherein, for cushion shape 208 on another surface of substrate 201, it preferably includes the first buffering
Layer 208a and second buffer layer 208b.It is to be noted that in other embodiments of the invention, cushion 208 both can be wrapped only
Containing a Rotating fields, more than three layers structures can also be included, the invention is not restricted to this.
Collector area 209 is formed on cushion 208, as shown in Fig. 2 in the present embodiment, in collector area 209 formed with
Some short dots 210 with the first conduction type.
In the present embodiment, during cushion 208, collector area 209 and short dot 210 is made, first with
High temperature (being greater than 1000 DEG C) spreads or the mode of ion implanting+low temperature (such as less than 500 DEG C) annealing is come in the table of substrate 201
Face forms one or more N buffer layer structures, so as to obtain cushion 208.Followed by High temperature diffusion or ion implanting+laser
The mode of annealing to form P+ collector areas 209 on the surface of cushion 208.Finally, also with High temperature diffusion or ion implanting+
The mode of laser annealing forms some N+ short dots 210 in P+ collector areas 209.
It is pointed out that in different embodiments of the invention, for the thicker power semiconductor of thickness, its positive work
The order of skill and back process (technical process for making cushion, collector area and short dot) can be adjusted, i.e., both
Back process can first be carried out and carry out positive technique again, can also first carried out positive technique and carry out back process again.And for needing
Thinned power semiconductor is carried out, it is necessary to first carry out positive technique carries out back process again, and overleaf can not in technique
There is pyroprocess.
As can be seen that gate oxide linearly becomes in the power semiconductor that the present embodiment is provided from foregoing description
Change, therefore it can effectively avoid the high convex and discontinuous defect of the device surface present in existing power semiconductor.Compared to
Existing power semiconductor, the power semiconductor that the present embodiment passed through is more smooth, its technique (mark alignment, photoetching and quarter
Erosion etc.) difficulty effectively reduced, so also help to improve the performance and chip package function of power semiconductor
Reliability.
Meanwhile the gate oxide of power semiconductor that the present embodiment is provided has been internally formed floating polysilicon layer,
Therefore field plate structure has been internally formed in gate oxide, the pressure-resistant performance of device has been improved, so that enhanced carrier layer
Doping concentration and the distance between cellular can further increase, reduce the base resistance and JFET areas resistance of device, from
And on-state voltage drop is reduced, and realize on-state voltage drop and pressure-resistant good compromise.
The gate oxide for the power semiconductor that the present embodiment is provided can be entered using the photoetching of standard with etching technics
Row make, without additionally developing specific photoetching and etching technics for step gates structure, thus can save process exploitation into
This.Meanwhile gate oxide is the shallower structure of the ratio formed using multiple substep photoetching and etching, therefore can avoid carrying out
Single deep etching, this also just reduces technology difficulty.
Embodiment two：
Fig. 3 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 3 can be seen that the power that the power semiconductor that the present embodiment is provided is provided with embodiment one
Only difference be present in the structure of gate oxide and polysilicon layer (including the first polysilicon layer and second polysilicon layer) in semiconductor,
Therefore, for convenience of description, while above-mentioned difference is protruded, below only to the gate oxide of power semiconductor in the present embodiment
It is described further with polysilicon layer.
As shown in figure 3, in the present embodiment, gate oxide includes two intervals, i.e. the 1st interval and the 2nd interval.Wherein, the 1st
The projected length of interval and the 2nd interval on substrate is respectively L1And L2.For the 1st interval, with ohmic contact regions
The increase of linear distance, its thickness keep constant, i.e., thickness is D always1；And for the 2nd interval, with ohmic contact regions
The increase of center line distance, its thickness is by D1Linearly increase to D2。
Correspondingly, in the present embodiment, the first polysilicon layer 203a and the second polysilicon layer 203b similarly include two
Individual interval, its shape is similar with the surface configuration of gate oxide, therefore will not be repeated here.In the present embodiment, the second polysilicon layer
203b is formed to be located above the first conductive region (preferably in the inside of gate oxide 202, the second polysilicon layer 203b one end
Above enhanced carrier layer 204), the other end aligns with the cellular right hand edge of power semiconductor.
Certainly, in other embodiments of the invention, with the increase with ohmic contact regions center line distance, power semiconductor
The thickness of middle gate oxide first can also linearly increase keeps constant again, that is, forms structure as shown in Figure 4.
It is pointed out that for the power semiconductor shown in Fig. 4, in order to avoid the grid oxic horizon institute accounting of big thickness
Excessive, the length L of its 2nd interval of example2The preferably less than half of the cellular length of power semiconductor half, by power semiconductor
Threshold voltage controls in the reasonable scope.
Embodiment three：
Fig. 5 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 5 can be seen that the power that the power semiconductor that the present embodiment is provided is provided with embodiment one
Only difference be present in gate oxide and polysilicon layer in semiconductor, therefore, for convenience of description, while prominent above-mentioned difference
Point, only the gate oxide and polysilicon layer of power semiconductor in the present embodiment are described further below.
As shown in figure 5, in the present embodiment, gate oxide includes three intervals, i.e. the 1st interval, the 2nd interval and the 3rd interval.
Wherein, projected length of these three intervals on substrate is respectively L1、L2And L3.For the 1st interval, connect with ohm
The increase of area's center line distance is touched, its thickness keeps constant, i.e., thickness is maintained at D1；For the 2nd interval, connect with ohm
The increase of area's center line distance is touched, its thickness is by D1Linearly increase to D2；For the 3rd interval, with ohmic contact regions center line
The increase of distance, its thickness keep constant, i.e., thickness is maintained at D2。
It is pointed out that in other embodiments of the invention, the interval number n that gate oxide is included can also be it
His reasonable value, the invention is not restricted to this.For example, when gate oxide includes 7 intervals, the structure of power semiconductor will be such as Fig. 6
It is shown.
Simultaneously, it is necessary to explanation, its last layer excessive in order to avoid the grid oxic horizon proportion of big thickness
The length L of section (i.e. n-th layer section)nThe preferably less than cellular length L of power semiconductor half half, by the threshold of power semiconductor
Threshold voltage controls in the reasonable scope.Exist：
L1+L2+...+Ln-1＜ L/2
It is pointed out that when gate oxide includes multiple intervals, it both can be the odd number in this multiple interval
Interval is flat bed section (i.e. as the increase with ohmic contact regions center line distance, thickness keep constant interval), and even number interval is
Oblique interval (i.e. with the increase with ohmic contact regions center line distance, the interval that thickness linearly increases) or this multiple layer
Odd number interval in section is oblique interval and even number interval is basic unit's section, and the invention is not restricted to this.
In addition, for each interval in multiple intervals, its projected length on substrate is advantageously equal, that is, is deposited
In L1=L2=...=Ln, and the slope of each tiltedly interval is also preferably equal.
Correspondingly, in the present embodiment, the first polysilicon layer 203a and the second polysilicon layer 203b similarly include two
Individual or multiple intervals, its shape are similar with the surface configuration of gate oxide.Wherein, the second polysilicon layer 203b one end is positioned at the
(the enhanced top of carrier layer 204 is preferably located in above one conductive region), on the right of the cellular of the other end and power semiconductor
Edge aligns.
Example IV：
Fig. 7 shows the structural representation for the cellular of power semiconductor half that the present embodiment is provided.
Comparison diagram 2 and Fig. 7 can be seen that the power that the power semiconductor that the present embodiment is provided is provided with embodiment one
Only difference be present in gate oxide and polysilicon layer in semiconductor, therefore, for convenience of description, while prominent above-mentioned difference
Point, only the gate oxide and polysilicon layer of power semiconductor in the present embodiment are described further below.
As shown in fig. 7, in the present embodiment, gate oxide includes four intervals, i.e. the 1st interval, the 2nd interval, the 3rd interval and
4th interval.Wherein, this four intervals are flat bed section, and the projected length on its each comfortable substrate is respectively L1、L2、L3And L4,
So just form stair-stepping gate oxide structure.
In the present embodiment, the length for multiple intervals that gate oxide is included preferably is equal to each other, that is, L be present1=L2=
L3=L4。
It is pointed out that in other embodiments of the invention, the quantity of the interval that gate oxide is included can be with
For other fair amounts, meanwhile, the length of different intervals can also be unequal, and the invention is not restricted to this.Meanwhile in order to avoid big
The grid oxic horizon proportion of thickness is excessive, and the length of its last interval is preferably less than the cellular length of power semiconductor half
L half, by the threshold voltage control of power semiconductor in the reasonable scope.
Correspondingly, in the present embodiment, the first polysilicon layer 203a and the second polysilicon layer 203b are similarly comprising more
Individual interval, its shape is similar with the surface configuration of gate oxide, therefore will not be repeated here.In the present embodiment, the second polysilicon layer
203b is formed to be located above the first conductive region (preferably in the inside of gate oxide 202, the second polysilicon layer 203b one end
Above enhanced carrier layer 204), the other end aligns with the cellular right hand edge of power semiconductor.
In order to more easily understand the characteristic of power semiconductor that the present embodiment provided, the present embodiment is carried below
The manufacturing process of the power semiconductor of confession is described further.
Fig. 8, Fig. 9 and Figure 10 show the flow chart that power semiconductor as shown in Figure 5 is manufactured in the present embodiment.
As shown in figure 8, in the present embodiment, layer of oxide layer is deposited on the substrate 201 first, the thickness of the oxide layer is preferred
Ground be no more than 0.5 μm, then the oxide layer formed is performed etching, so as to produce the injection of enhanced carrier layer 204/
Adulterate window.After injection/doping window of enhanced carrier layer 204 is obtained, using the injection/doping window to substrate
Injection/doping of enhanced carrier layer is carried out in 201, high temperature propulsion/diffusion is then carried out, so as to form a doping concentration
The enhanced carrier layer 204 higher than substrate 201.In the present embodiment, the doping concentration of enhanced carrier layer 204 is preferably big
In 1e15/cm3。
P- basic units are further formed after enhanced carrier layer 204 is obtained, it is necessary in enhanced carrier layer 204
205.As shown in figure 8, in the present embodiment, because the injection using enhanced carrier layer 204/doping window forms enhanced load
During flowing sublayer 204, high temperature promotes technique that the thickness of oxide layer 211 is added, and is so to form enhanced current-carrying
Sublayer 204 and injection/doping window for making is covered oxidized layer, therefore now need first to the increased oxidation of thickness
Layer performs etching, to form the injection of P- bases/doping window.
After injection/doping window of P- bases is formed, you can carry out P- to enhanced carrier layer 204 using the window
Injection/doping of base, high temperature propulsion/DIFFUSION TREATMENT is then carried out, so as to form P- bases in enhanced carrier layer 204
205.In the present embodiment, the doping concentration of P- bases 205 is preferably e17/cm3Magnitude.
It is pointed out that in other embodiments of the invention, according to being actually needed, enhanced carrier layer 204 and/
Or the doping concentration of P- bases 205 can also be other reasonable values, the invention is not restricted to this.
After P- bases 205 are formed, it is D to form a thickness on the substrate 2013SiO2Layer 211, and pass through multiple photoetching
And the method for etching, produce SiO as shown in Figure 82Table top (i.e. first object table top).
As shown in figure 9, obtaining the SiO2After table top, in the SiO2The polysilicon layer of a specific thicknesses is formed on table top (i.e.
Second polysilicon layer 203b), and carry out N-type polycrystalline silicon doping.In the present embodiment, the thickness of polysilicon layer is preferably less than 0.5 μ
M, its doping concentration is preferably in 1e19/cm3More than.Certainly, in other embodiments of the invention, it is more according to being actually needed
The thickness and doping concentration of crystal silicon layer can also be other reasonable values, and the invention is not restricted to this.
After completing said process, in the present embodiment, also to being covered on enhanced carrier layer 204 and P- bases 205
Part SiO2Layer and polysilicon layer carry out photoetching or etching, continue thereafter with one layer of SiO of covering2Layer, wherein, the SiO2Layer
Thickness is D2.By to the SiO2Layer carries out multiple etching, forms mesa structure as shown in Figure 9 (i.e. the second target mesa).
As shown in Figure 10, after the second target mesa is obtained, this method forms a specific thicknesses in the second target mesa
Polysilicon layer, and N-type polycrystalline silicon doping is carried out, so as to obtain the first polysilicon layer 203a.Then, successively in P- bases 205
Middle formation source area 206 and ohmic contact regions 207, due to source area 206 and the specific forming process of ohmic contact regions 207
It is similar with the forming process of P- bases, therefore will not be repeated here.In the present embodiment, the thickness of ohmic contact regions 207 is preferably big
In the thickness of source area 206.
So far the positive technique of power semiconductor is just completed.After positive technique is completed, side that the present embodiment is provided
Method will carry out the making of the back process of power semiconductor.Specifically, as shown in Figure 10, (it is greater than first with high temperature
1000 DEG C) diffusion or ion implanting+low temperature (such as less than 500 DEG C) annealing mode formed come another surface in substrate 201
One or more N buffer layer structures, so as to obtain cushion 208.In the present embodiment, cushion 208 includes first buffer layer
208a and second buffer layer 208b.Come followed by the mode of High temperature diffusion or ion implanting+laser annealing in the table of cushion 208
Face forms P+ collector areas 209.Finally, come also with the mode of High temperature diffusion or ion implanting+laser annealing in P+ current collections
Some N+ short dots 210 are formed in polar region 209.
It is pointed out that in different embodiments of the invention, for the thicker power semiconductor of thickness, its positive work
The order of skill and back process (technical process for making cushion, collector area and short dot) can be adjusted, i.e., both
Back process can first be carried out and carry out positive technique again, can also first carried out positive technique and carry out back process again.And for needing
Thinned power semiconductor is carried out, it is necessary to first carry out positive technique carries out back process again, and overleaf can not in technique
There is pyroprocess.
In addition it is also necessary to, it is noted that in other embodiments of the invention, according to being actually needed, source area 206 and
The manufacturing process of ohmic contact regions 207 can also be advanced to before manufacturing gate oxide layers, and the invention is not restricted to this.
It should be understood that disclosed embodiment of this invention is not limited to specific structure disclosed herein, processing step
Or material, and the equivalent substitute for these features that those of ordinary skill in the related art are understood should be extended to.It should also manage
Solution, term as used herein are only used for describing the purpose of specific embodiment, and are not intended to limit.
" one embodiment " or " embodiment " mentioned in specification means special characteristic, the structure described in conjunction with the embodiments
Or during characteristic is included at least one embodiment of the present invention.Therefore, the phrase " reality that specification various places throughout occurs
Apply example " or " embodiment " same embodiment might not be referred both to.
Although above-mentioned example is used to illustrate principle of the present invention in one or more apply, for the technology of this area
For personnel, in the case of without departing substantially from the principle and thought of the present invention, hence it is evident that can in form, the details of usage and implementation
It is upper that various modifications may be made and does not have to pay creative work.Therefore, the present invention is defined by the appended claims.
Claims (14)
- A kind of 1. method for making power semiconductor, it is characterised in that methods described includes：Step 1: the semiconductor layer of the first preset thickness is formed on substrate；Step 2: being performed etching to the semiconductor layer of first preset thickness, first object table top is obtained；Step 3: form the second polysilicon layer on the first object table top；Step 4: semiconductor layer is continuously formed on second polysilicon layer, and the semiconductor layer to ultimately forming is carved Erosion, obtains the second target mesa, so as to form gate oxide；Step 5: form the first polysilicon layer in second target mesa.
- 2. the method as described in claim 1, it is characterised in that the gate oxide has a multi-thickness, and with half The trend gradually increased is presented in the increase of distance between conductor source area, the thickness of the gate oxide.
- 3. method as claimed in claim 1 or 2, it is characterised in that the thickness of the most thick opening position of gate oxide after etching is More than 8 times of the thickness of its most thin opening position.
- 4. such as method according to any one of claims 1 to 3, it is characterised in that the first object table top and/or second The thickness in face is along first end to the second linear increase.
- 5. such as method according to any one of claims 1 to 3, it is characterised in that second target mesa includes connecting successively The multiple intervals connect,Each odd number interval is flat bed section in the multiple interval, and each even number interval is oblique interval；Or,Each odd number interval is oblique interval in the multiple interval, and each even number interval is flat bed section；Wherein, the flat bed section keeps constant interval for the thickness of each opening position, and the tiltedly interval is that thickness linearly increases Interval.
- 6. such as method according to any one of claims 1 to 3, it is characterised in that second target mesa includes connecting successively The multiple intervals connect, the multiple interval form step structure, wherein, the thickness of the interval more remote apart from the first end is more Greatly.
- 7. the method as described in claim 5 or 6, it is characterised in that first end described in distance is farthest in the multiple interval The length of interval is less than the half of half cellular width of power semiconductor.
- 8. such as method according to any one of claims 1 to 7, it is characterised in that first polysilicon layer and/or more than second The thickness of crystal silicon layer position is equal.
- 9. such as method according to any one of claims 1 to 8, it is characterised in that before the first object table top is formed, institute State method and also form first window over the substrate, and formed in the substrate using the first window and led with first The enhanced carrier layer of electric type, P- bases are formed in the enhanced carrier layer.
- 10. such as method according to any one of claims 1 to 8, it is characterised in that after first polysilicon layer is formed, Methods described also forms the second window in the polysilicon layer and gate oxide, and using second window in the substrate It is middle to form the enhanced carrier layer with the first conduction type, P- bases are formed in the enhanced carrier layer.
- 11. the method as described in claim 9 or 10, it is characterised in that after the P- bases are formed, methods described is also described The source area with the first conduction type and the ohmic contact regions with the second conduction type are formed in P- bases, wherein, it is described Ohmic contact regions are located at the centre position of the P- bases.
- 12. method as claimed in claim 10, it is characterised in that the thickness of the ohmic contact regions is more than the source area Thickness.
- 13. the method as any one of claim 1~11, methods described also include：Cushion is formed on another surface of the substrate；Collector area is formed on the cushion.
- 14. method as claimed in claim 13, methods described also include：Short dot is formed on the collector area.
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