JPH08321602A - Mis semiconductor device and controlling method thereof - Google Patents

Abstract

PURPOSE: To simultaneously realize both characteristics of rapid switching characteristics and low on-resistance characteristics in an insulating gate type field effect transistor. CONSTITUTION: Two gate electrode layers 27 and 26 of a MOSFET are formed through an insulating film and selectively used, that is, the gate electrode 27 is used for switching in the turn-on and turn-off times while the gate electrode 26 is used for on-state only. In such a constitution, if the gate electrode 27 of a small Miller capacitance between the gate electrode and a silicon substrate is used, the switching rate can be increased while if the gate electrode 26 having a thin gate oxide film is used, the on-resistance in the normal state is lowered. Furthermore, in the turn-on time, after turning on by feeding a gate signal to the gate electrode 27, the gate signal is given to the gate electrode 26. Contrarily, in the turn off time, firstly, after turning off the gate signal fed to the electrode 26, the gate signal fed to the gate electrode 27 is turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device (hereinafter, abbreviated as MIS semiconductor device) having a metal-insulating film-semiconductor structure gate and performing a switching operation.

[0002]

2. Description of the Related Art MOSF which is a kind of MIS semiconductor device
A partial cross-sectional view of ET (a field effect transistor having a gate of a metal-oxide film-semiconductor structure) is shown in FIG. M
In the OSFET, in addition to the active portion for turning on / off the current shown in the figure, there is a portion mainly responsible for breakdown voltage in the peripheral portion,
Since it is not a part related to the essence of the present invention, it is omitted.

In FIG. 1, an n drift layer 2 epitaxially grown on a low resistance n type substrate 1 has a p base region 3 formed in its surface layer by selectively introducing p type impurities. An n source region 4 is formed in a part of the surface layer of the p base region 3, and the surface of the p base region 3 and the n drift layer 2 sandwiched between the n source regions 4 in two adjacent p base regions 3 are exposed. A gate electrode 6 made of polycrystalline silicon is formed on the portion via a gate oxide film 5. Then, a source electrode 8 that is in common contact with the surfaces of the n source region 4 and the p base region 3 is provided,
A drain electrode 9 is provided on the back surface of the n-type substrate 1 by adhesion of an Al alloy. The source electrode 8 can be extended by covering the upper and side portions of the gate electrode 6 with the insulating film 10 as shown in the figure.

The operation of this MOSFET will be described below.
When the source electrode 8 is grounded, the drain electrode 9 is applied with a positive potential, and a potential higher than a certain voltage is applied to the gate electrode 6, an inversion layer (partly partially Storage layer 11 is induced. Then, the drain electrode 9 and the source electrode 8 are electrically connected to each other through the inversion layer 11, and a current flows. When the positive potential of the gate electrode 6 is removed, the inversion layer 11 disappears and the current stops. As described above, conventionally, a single gate electrode controls the on / off operation of the MOSFET.

[0005]

The problem to be solved by the invention is shown in FIG.
The enlarged view of the gate electrode 6 vicinity of (a) is shown. Conventional MO
The switching speed at turn-on and turn-off in the SFET is determined by the size of the mirror capacitance Cmi between the gate electrode and the silicon substrate shown in FIG. FIG. 3 shows the relationship between the switching time and the film thickness of the gate oxide film. The horizontal axis represents the gate oxide film thickness, the vertical axis represents the switching time, and the gate oxide film thickness is 100 n.
It is shown by a relative value with the element of m as a standard. As can be seen from this figure, the thicker the gate oxide film, the shorter the switching time, that is, the faster the switching speed. It is considered that this is because the thicker the gate oxide film, the smaller the mirror capacitance Cmi.

On the other hand, the on-state resistance of the MOSFET in the on-state is mainly determined by the charge amount of the inversion layer 11 shown in FIG. 2B, and the charge amount depends on the thickness of the gate oxide film. FIG. 3 also shows the relationship between the ON resistance and the film thickness of the gate oxide film. The vertical axis represents the on-resistance, which is also shown as a relative value with a device having a gate oxide film thickness of 100 nm as a standard. As can be seen in this figure, the thicker the gate oxide film, the higher the on-resistance.

That is, the switching speed and the on-resistance have a trade-off relationship. Therefore, in the prior art, it was not possible to simultaneously satisfy the two characteristics of high switching speed and low on-resistance. In view of the above problems, an object of the present invention is to provide a MIS semiconductor device that simultaneously satisfies both high-speed switching characteristics and low on-resistance characteristics.

[0008]

In order to solve the above problems, a MIS semiconductor device having a metal-insulating film-semiconductor structure gate of the present invention is a two-layer conductive film in which a gate electrode sandwiches an insulating film. Shall consist of In particular, it is preferable that the insulating film be an oxide film and the conductive film be made of polycrystalline silicon.

As a method of controlling the MIS semiconductor device of the present invention, a signal is applied to the upper layer gate electrode, then a signal is applied to the lower layer gate electrode, and a signal is removed from the lower layer gate electrode and then the upper layer gate electrode is removed. The signal of the gate electrode shall be removed.

[0010]

As described above, the MIS semiconductor device having the gate electrode made of the two-layer conductive film sandwiching the insulating film is as follows.
In each of the turn-on, turn-off, and on-state operating states, the two-layer gate electrodes can be used independently according to each operating mode, and the mirror capacitance Cmi between the gate electrode and the semiconductor substrate can be changed.

In particular, if the insulating film is an oxide film and the conductive film is polycrystalline silicon, it is the most common material in the semiconductor process and is easy to manufacture.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a MOSFET according to an embodiment of the present invention.
FIG. 4 is a partial cross-sectional view of the active portion of FIG. In the figure, n epitaxially grown on a low-resistance n-type substrate 21.
A p base region 23 is formed in the surface layer of the drift layer 22 by selectively introducing a p-type impurity. An n source region 24 is formed in a part of the surface layer of the p base region 23, and the surface of the p base region 23 and the n drift layer 22 sandwiched between the n source regions 24 in two adjacent p base regions 23 are exposed. Gate electrode 2 composed of two layers of polycrystalline silicon sandwiching an oxide film with a gate oxide film 25 interposed therebetween.
6, 27 are formed. Then, the n source region 24
A source electrode 28 that is commonly in contact with the surface of the p-type base region 23 is provided by Al alloy deposition, and a drain electrode 29 is provided on the back surface of the n-type substrate 21 by Al alloy deposition. The source electrode 28 may be extended by covering the upper and side portions of the gate electrode 27 with the insulating film 30 as shown in the figure. The gate electrodes 26 and 27 are controlled independently of each other. A gate electrode 26 formed by sandwiching a gate oxide film 25 on a silicon substrate serving as a semiconductor substrate is for ON state, and a gate electrode 27 formed by sandwiching an oxide film on the gate electrode 26 is for switching. Is.

In this structure, the thickness of each gate oxide film is set as follows. The oxide film thickness under the gate electrode 26 for the on-state is set to 80 nm so as to be thinner than the oxide film thickness of the conventional structure, for example, 100 nm.
The oxide film thickness below the switching gate electrode 27 is the sum of the oxide film thickness below the ON state gate electrode 26 and the oxide film thickness between the gate electrodes 26 and 27,
For example, to increase the oxide film thickness of the conventional structure to 120
nm.

The operation of this MOSFET will be described below.
In the above state, the gate signals 33 and 34 as shown in FIG. 4 are applied to the respective gate electrodes. FIG.
An enlarged view of the vicinity of the gate electrodes 26 and 27 of FIG. 1A is shown in FIG. In the turn-on process, the source electrode 28 is grounded, the drain electrode 29 is given a positive potential, and the voltage signal 33 is applied to the switching gate electrode 27 shown in FIG. At this time, the gate electrode 26 for the on state is in the open state. Then, the inversion layer (a part of the storage layer) 31 is induced in the surface layer of the p base region 23 immediately below the gate electrode 27. Then, the drain electrode 29 and the source electrode 28 are electrically connected to each other through the inversion layer 31, and a current flows. The gate oxide film under the switching gate electrode 27 is
Gate oxide film 25 under the gate electrode 26 for ON state
(Thickness 80 nm) plus the oxide film (thickness 40 nm) between the gate electrode 26 and the gate electrode 27, and since the mirror capacitance Cmi ₂ is small, the switching time is
It is about 0.9 times shorter, that is, the switching speed is
That will be faster. As shown in FIG. 4, the method of applying a large voltage in the initial stage as a voltage signal for switching is a method that is usually performed to speed up switching.

Subsequently, in the ON state, FIG.
The voltage signal 3 is applied to the gate electrode 26 for on-state shown in FIG.
4 is applied. At this time, the gate electrode 2 for switching
7 may be short-circuited with the gate electrode 26 for ON state.
Since the thickness (80 nm) of the gate oxide film 25 under the on-state gate electrode 26 is thin, the number of induced charges in the inversion layer 31 is large, and the inversion layer 31 is strongly inverted. 10% or more lower. At this time, the mirror capacitance Cmi ₁ between the gate electrode 26 and the silicon substrate is large, but this is not a problem because it is in a steady state.

In the turn-off process, as shown in FIG.
The gate signal 34 to the gate electrode 26 for the ON state shown in FIG.
Is turned off first, and then the gate electrode 27 for switching is turned on.
The voltage signal 33 of 1 is set below the threshold value. At this time, similarly to the mirror capacitance Cmi of the oxide film under the gate electrode 27.
_{Since 2} is small, the switching speed is fast. As described above, the gate electrode with the thicker gate oxide film is used during the turn-on and turn-off operations, and the gate electrode with the thinner gate oxide film is used during the on-state. Conventionally, a single gate electrode was used as a gate electrode having a structure in which two electrodes are superposed in a doubled manner, and by selectively using the gate electrode during the switching element operation at the time of turn-on and turn-off and at the time of on-state, A MOSFET that simultaneously satisfies high-speed switching characteristics and low on-resistance characteristics is realized.

Although the MOSFET has been described as an example, the present invention is not limited to the MOSFET, and a bipolar transistor having a MOS gate called an IGBT and an MO having a MOS type gate.
It can also be applied to S-controlled thyristors (MCT). Further, since the insulating film is not limited to the oxide film, it is generally applied to so-called MIS semiconductor devices.

[0018]

As described above, the MIS semiconductor device of the present invention uses a gate electrode having a structure in which two electrodes are doubly overlapped with each other, and the switching element is operated at turn-on and turn-off and in the on-state. By properly using the gate electrode, it becomes a MIS semiconductor device that simultaneously satisfies the high-speed switching characteristic and the low on-resistance characteristic. As a result, the loss of the semiconductor device or the power conversion device using the semiconductor device can be significantly reduced.

[Brief description of drawings]

1A is a partial cross-sectional view of a MOSFET according to an embodiment of the present invention, and FIG. 1B is an enlarged view of the vicinity of a gate electrode thereof.

2A is a partial cross-sectional view of a conventional MOSFET, FIG.
(B) is an enlarged view near the gate electrode

FIG. 3 is a diagram showing gate oxide film thickness dependence of switching time and on-resistance of the inversion layer portion.

FIG. 4 is a timing chart of gate signals for operating the MOSFET according to the embodiment of the present invention.

[Explanation of symbols]

 1, 21 n-type substrate 2, 22 n drift layer 3, 23 p base region 4, 24 n source region 5, 25 gate oxide film 6 gate electrode 26 (for ON state) gate electrode 27 (for switching) gate electrode 8 , 28 Source electrode 9, 29 Drain electrode 10, 30 Insulating film 11, 31 Inversion layer Cmi Mirror capacitance

Claims (4)

[Claims] 1. A MIS semiconductor device having a metal-insulating film-semiconductor structure gate, wherein the gate electrode is composed of two layers of conductive films sandwiching an insulating film. 2. The MI according to claim 1, wherein the insulating film is an oxide film and the conductive film is made of polycrystalline silicon.
S semiconductor device. 3. A method of controlling a MIS semiconductor device having a gate formed of two conductive films sandwiching an insulating film, wherein a signal is applied to a gate electrode of an upper layer and then a signal is applied to a gate electrode of a lower layer. MIS semiconductor device control method. 4. The method of controlling a MIS semiconductor device according to claim 3, wherein the signal of the upper-layer gate electrode is removed after the signal of the lower-layer gate electrode is removed.