JPH08236754A - P-channel type high breakdown strength mosfet - Google Patents

Abstract

PURPOSE: To raise the breakdown strength between a source and drain in the condition that the source electrode potential to a substrate is high, by setting the concentration of impurities on the surface of a p-type drain drift region in specified range. CONSTITUTION: A silicon layer 3 is n-type, and the concentration of impurities is in the range 2*10<14> -1.0*10<16> cm<-3> . A p-type drain drift layer 4 where the concentration of impurities on the surface is in the range of 1.0*10<14> -1.0*10<16> cm<-3> , and the depth of diffusion is in the range of 0.5-4.0μm, and a p-type drain region 8 are made, being connected at a part of the surface layer of this silicon layer 3. Moreover, at a part of the surface layer of the silicon layer 3 is an n-type base region 5 made a little apart from the p-type drain drift region 4, and at a part of the surface layer of the base region 5 is a p-type source region 9 made. This way, the depletion of the p-type drain drift region can be accelerated by lowering the concentration of impurities on the surface of the p-type drain drift region 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a p-channel MOSFET formed on an n-type semiconductor layer joined on a semiconductor substrate via an insulating film.

[0002]

2. Description of the Related Art A semiconductor substrate is shown in FIG.
P-channel MOS formed in integrated n-type semiconductor layer
FET (metal-oxide film-semiconductor structure field effect transistor
(Hereinafter, referred to as a pMOSFET) will be described.
This figure shows bonding to a supporting substrate 1 via a laminated oxide film 2.
Of the silicon layer 3 of the SOI substrate having the silicon layer 3
FIG. 4 is a cross-sectional view of a main part of a pMOSFET formed on a surface layer.
It In recent years, high withstand voltage of devices, insulation from substrate, parasitic capacitance
In order to reduce the amount,
A large number of semiconductor devices were manufactured using
There is. The thickness of the laminated oxide film 2 is 1 to 3 μm,
The n-type layer 3 is n-type and has an impurity concentration of 2.0 × 10 ¹⁴cm^-3,
The thickness is 10 μm. Part of the surface layer of the silicon layer 3
And the surface impurity concentration is 3.0 × 10¹⁶cm^-3, Diffusion depth
Of the p-type drain drift region 4 of 2.0 μm
Pure substance concentration is 3.7 × 10^Fifteencm^-3, The diffusion depth is 6.0μ
The p-type drain region 8 of m is connected and formed. Well
P-type drain drift in a part of the surface layer of the silicon layer 3
A little away from the region 4, the surface impurity concentration is 1.0 × 10
¹⁷cm^-3, N-type base region 5 with a diffusion depth of 4.5 μm
And surface impurities on a part of the surface layer of the n-type base region 5.
Concentration is 2.6 × 10¹⁹cm^-3, The diffusion depth is 0.8 μm
A p-type source region 9 is formed. n-type base region 5
In addition, a high concentration n-type contact region 10 is formed on the surface layer of
Has been formed. On the surface of p-type drain drift region 4
Has a thick LOCOS oxide film 6. p-type source region
N-type base sandwiched between 9 and p-type drain drift region 4
On the surface of the surface 5 and the exposed surface of the silicon layer 3,
A gate electrode 11 is provided via a gate oxide film 7, and p
A drain electrode 13 is formed on the surface of the mold drain region 8 with p
Source electrodes 12 are formed on the surface of the mold source region 9, respectively.
It is provided. This pMOSFET has a gate electrode 1
N-type directly under the gate electrode 11 by applying a negative voltage to
An inversion layer is formed near the surface of the base region 5 and the silicon layer 3.
Occurs, and conduction is established between the source electrode 12 and the drain electrode 13.
To do.

An example of a circuit using this pMOSFET is shown in FIG.
Shown in This circuit is a high withstand voltage drive circuit. PMOSFET 20 between the power supply 101 and the ground 100
1 and n-channel MOSFET (nMOSFET) 20
2 and 2 are connected in series with a common drain, and the output terminal 102 is taken out from the common drain. The load is connected between the output terminal 102 and the ground 100. The voltage of the power supply 101 is 200V, for example. The operation of this circuit will be briefly described. pMOSFET
When the (negative) ON signal is input to the input terminal 103 connected to the gate electrode 11 of 201 and the (negative) OFF signal is input to the input terminal 104 connected to the gate electrode of the nMOSFET 202, the pMOSFET 201 is turned on. In the state, the nMOSFET 202 is turned off, and the output terminal 102 becomes the power supply potential. On the other hand, when a (positive) off signal is input to the input terminal 103 and a (positive) on signal is input to the input terminal 104, the pMOSFET 201 is in the off state and the nMO
The SFET 202 is turned on, and the output terminal 102 becomes the ground potential. Source electrode 12 of pMOSFET 201
Is always at the potential of the power source supplied from the power source terminal 101. Therefore, when the output terminal 102 has the ground potential, the drain electrode 13 of the pMOSFET 201 also has the ground potential, and the power supply voltage is applied between the source electrode 12 and the drain electrode 13 of the pMOSFET 201.

[0004]

Generally, the substrate of a semiconductor device is often placed at ground potential. Considering the pMOSFET of FIG. 8 used in the circuit of FIG. 9 in such a case, when the pMOSFET is in the off state, the supporting substrate 1
And the drain electrode 13 has a ground potential, and the source electrode 12
Is supplied with a (positive) power supply potential.

FIG. 10 shows the source electrode potential dependency of the breakdown voltage of the pMOSFET 201 of FIG. The horizontal axis is substrate 1
The potential of the source electrode 12 based on the potential of the above, and the vertical axis represents the element breakdown voltage, that is, the breakdown voltage between the source electrode 12 and the drain electrode 13. When the source electrode potential is negative, it shows a withstand voltage of 200 V or more, and when the source electrode potential is zero, it shows a withstand voltage of 300 V or more, while it is 1 when the source electrode potential is positive.
It only shows a breakdown voltage of about 00V.

That is, when the pMOSFET 201 of FIG. 8 is used in a state where the substrate is grounded and a positive potential is applied to the source electrode, the device breakdown voltage is about 100 V, and a potential of 200 V is applied to the source electrode 12 as shown in FIG. It cannot be applied to the circuit that is used. In view of the above problems, it is an object of the present invention to provide a p-channel type MOS with a high source-drain breakdown voltage when the source electrode potential with respect to the substrate is high.
It is to provide a FET.

[0007]

[Means for Solving the Problems] The reason why the breakdown voltage of the device is lowered when the potential applied to the source electrode is positive was analyzed. First, FIG. 11 shows a potential distribution when the source electrode 12 has the same ground potential as the substrate 1. A voltage of 300 V is applied between the source electrode 12 and the drain electrode 13. In this case, the potential of the source electrode 12 and the potential of the supporting substrate 1 are the same ground potential, and 300 V is also applied between the substrate 1 and the drain electrode 13. The solid lines in the figure represent equipotential lines for every 30V. The depletion layer spreads widely between the n-type base region 5 and the p-type drain region 8, and the p-type drain drift region 4 is almost entirely depleted. In the depth direction, it also extends into the silicon layer 3 below the p-type drain region 8 and the bonded oxide film 2. It is understood that a high breakdown voltage of 300 V is maintained by being supported by this wide depletion layer.

On the other hand, FIG. 12 shows a potential distribution when the source electrode 12 is kept at a positive potential with respect to the substrate 1. Unlike the case of the ground potential described above, a voltage of 200 V is applied between the source electrode 12 and the substrate 1. Although the depletion layer spreads over the silicon layer 3 and the bonding oxide film 2 below the n base region 5, it is blocked in the lateral direction in the middle of the p-type drain drift region 4 and does not spread sufficiently, so the breakdown voltage does not become so high. . The solid lines in the figure represent equipotential lines every 10 V, and the breakdown voltage between the source electrode 12 and the drain electrode 13 is only about 100 V.

Comparing the two, when the positive potential is applied to the source electrode 12, the depletion of the p-type drain drift region 4 does not proceed more than when the ground potential is applied to the source electrode 12, and the gate electrode An electric field is concentrated near the edge of the LOCOS oxide film 6 under 11 to cause breakdown. This is because the charge of the silicon layer 3 is stuck to the oxide film 2.
It is considered that this occurs because the depletion layer extending from the p-type drain drift region 4 is insufficiently compensated for the depletion layer.

Due to the difference in the withstand voltage mechanism described above, when the potential applied to the source electrode 12 is positive, the withstand voltage is lowered. Then, in order to solve the problem of the decrease in breakdown voltage, the amount of charges in the silicon layer 3 and the p-type drain drift region 4 when the positive potential is applied to the source electrode 12 is balanced and the p-type drain drift is obtained. It is important to promote depletion of the area. For that purpose, there are two methods of reducing the impurity concentration of the p-type drain drift region 4 and the p-type drain region 8 and increasing the impurity concentration of the silicon layer 3. However, it is difficult to greatly change the method of (1) because it may affect other elements formed on the same silicon layer 3.

According to the present invention, an n-type semiconductor layer joined on a semiconductor substrate via an insulating film, an n-type base region formed in a surface layer of the n-type semiconductor layer, and the n-type base region thereof. A p-type source region formed in a part of the surface layer of
The p-type drain drift region formed on the surface layer of the n-type semiconductor layer apart from the type base region, and the p-type drain drift on the surface layer of the n-type semiconductor layer on the side of the p-type drain drift region far from the n-type base region. P formed by connecting to the region
A p-type drain region, a n-type base region sandwiched between the p-type source region and the p-type drain drift region, and a gate electrode provided on the surface of the exposed surface of the n-type semiconductor layer via a gate insulating film, p P-channel MOSF having a thick LOCOS oxide film formed on the surface of the drain drain region and source and drain electrodes provided on the surfaces of the p-type source region and the p-type drain region, respectively.
In ET, it is assumed that the surface impurity concentration of the p-type drain drift region is 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁶ cm ⁻³ .

Particularly, the diffusion depth of the p-type drain drift region is 0.5 to 4.0 μm, and the impurity concentration of the n-type semiconductor layer is 2 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^-3. is important. Further, the p-type drain drift region and the p-type
The type drain regions are preferably made of the same p-type diffusion region.

The n-type base region and the p-type drain drift region may be connected.

[0014]

With the above-mentioned means, the surface impurity concentration of the p-type drain drift region is 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁶ c.
If it is m ⁻³ , depletion of the p-type drain drift region is promoted. Furthermore, if the diffusion depth of the p-type drain drift region is 0.5 to 4.0 μm and the impurity concentration of the n-type semiconductor layer is 2 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^−3. , N-type semiconductor layer and p-drain drift region depletion layer charge balance.

In particular, the p-type drain drift region and p
If the type drain regions are composed of the same p-type diffusion region, both regions can be formed simultaneously. If the n-type base region and the p-type drain drift region are connected, the channel length when applying the gate voltage can be shortened.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.
explain about. FIG. 3 shows a MOS according to the first embodiment of the present invention.
It is sectional drawing of FET. The figure shows the substrate 1
SOI having a silicon layer 3 bonded through an oxide film 2
PMOSFET formed on the surface layer of the silicon layer 3 of the substrate
FIG. Figure 3 shows a pMOSFET switch
FIG. 3 shows a part of the active part that performs the ringing action, and pMOSF
In ET, there are other parts that mainly share the withstand voltage, but
Since that part may have a normal structure, it is omitted here.
It FIG. 3 shows a structure similar to the conventional one shown in FIG.
Therefore, each parameter will be explained. Bonded oxide film 2
The film thickness is 1 to 3 μm, the silicon layer 3 is n-type and has an impurity concentration
Is 1.0 x 10^Fifteencm^-3, The thickness is 10 μm. Siri
A part of the surface layer of the con layer 3 has a surface impurity concentration of 1.0 ×
10^Fifteencm^-3, P-type drain with diffusion depth of 2.0 μm
The lift region 4 and the surface impurity concentration are 3.7 × 10.^Fifteencm
^-3Contact with the p-type drain region 8 having a diffusion depth of 6.0 μm.
It is formed continuously. Also, one of the surface layers of the silicon layer 3
A little away from the p-type drain drift region 4 and the surface
Impurity concentration is 1.0 × 10¹⁷cm^-3, Diffusion depth is 4.5
μm n-type base region 5 and a table of the n-type base region 5
The surface impurity concentration is 2.6 × 10 in a part of the surface layer.¹⁹cm^-3,
The p-type source region 9 having a diffusion depth of 0.8 μm is formed
There is. The surface layer of the n-type base region 5 also has a high concentration of n.
A mold contact region 10 is formed. p-type drain
On the surface of the drift region 4 near the n-type base region 5
Has a thick LOCOS oxide film 6. p-type source region
N-type base sandwiched between 9 and p-type drain drift region 4
On the surface of the surface 5 and the exposed surface of the silicon layer 3,
Gate made of polycrystalline silicon through gate oxide film 7
An electrode 11 is provided and on the surface of the p-type drain region 8
The drain electrode 13 made of Al alloy is a p-type source region.
9 and the n-type contact region 10 have a common contact surface.
Source electrodes 12 to be touched are provided respectively. Drain
Surface layer of p-type drain region 8 provided with in electrode 13
Has a surface impurity concentration of 1 × 10²⁰cm^-3, Diffusion depth 1μ
m p-type contact region 15 is formed to reduce the contact resistance.
ing. The support substrate 1 may be p-type or n-type.

The operation of this pMOSFET is the same as that of the conventional one, and by applying a negative voltage to the gate electrode 11, an inversion layer is formed in the vicinity of the surfaces of the n-type base region 5 and the silicon layer 3 immediately below the gate electrode 11. A current flows from the source electrode 12 to the drain electrode 13. When the negative voltage is removed, the current stops from the source electrode 12 to the drain electrode 13.

FIG. 2 shows the dependency of the device breakdown voltage of the pMOSFET of FIG. The horizontal axis represents the potential of the source electrode 12 based on the potential of the substrate 1, and the vertical axis represents the element breakdown voltage, that is, the breakdown voltage between the source electrode 12 and the drain electrode 13. When the source electrode potential is negative, the withstand voltage is 150 V or less, and when the source electrode potential is zero, the withstand voltage is about 150 V, whereas when the source electrode potential is positive, the withstand voltage is improved, and when the source electrode potential is 200 V. It shows a breakdown voltage of 300 V or more. Therefore, it can be applied to a circuit in which a positive potential is applied to the source electrode as shown in FIG.

The pMOSFET of FIG. 3 has the same basic structure as that of the conventional one, but is characterized in that the surface impurity concentration of the p-type drain drift region 4 is lowered. Therefore, the manufacturing method thereof only needs to change the ion implantation amount of the p-type impurity for forming the p-type drain drift region 4, and does not require a large process change. The main manufacturing conditions were examined. FIG. 1 shows the pMOS of FIG.
The dependence of the FET breakdown voltage on the surface impurity concentration of the p-type drain drift region 4 is shown. The parameters are when the impurity concentration of the silicon layer 3 is 1 × 10 ¹⁵ cm ⁻³ and the diffusion depth of the p-type drain drift region 4 is 2.0 μm.
The horizontal axis represents the surface impurity concentration of the p-type drain drift region 4,
The vertical axis represents the element breakdown voltage, that is, the breakdown voltage between the source electrode 12 and the drain electrode 13. p-type drain drift region 4
Surface impurity concentration of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ c
The breakdown voltage is 200 V or more in the range of m ^-3 . You.

FIG. 4 shows the dependence of the breakdown voltage of the pMOSFET of FIG. 3 on the diffusion depth of the p-type drain drift region 4. The horizontal axis represents the diffusion depth of the p-type drain drift region 4, and the vertical axis represents the device breakdown voltage. The parameters are when the impurity concentration of the silicon layer 3 is 1 × 10 ¹⁵ cm ⁻³ and the surface impurity concentration of the p-type drain drift region 4 is 1 × 10 ¹⁵ cm ⁻³ . The diffusion depth of the p-type drain drift region 4 is 0.
The breakdown voltage is 200 V or higher in the range of 5 to 4.0 μm.

FIG. 5 shows the dependence of the breakdown voltage of the pMOSFET of FIG. 3 on the impurity concentration of the silicon layer 3. The horizontal axis represents the impurity concentration of the silicon layer 3, and the vertical axis represents the device breakdown voltage. The parameters are when the surface impurity concentration of the p-type drain drift region 4 is 1 × 10 ¹⁵ cm ⁻³ and the diffusion depth is 2.0 μm. The impurity concentration of the silicon layer 3 is 2 × 10 ¹⁴ cm
^The withstand voltage is 200 V or more in the range of ^-3 to 1 x 10 ¹⁶ cm ^-3 .

In these ranges, the charges of the silicon layer 3 in the depletion layer and the p-type drain drift region 4 are balanced and depletion is promoted, so that the breakdown voltage becomes high. The p-channel type M formed on the SOI substrate in this way
It has been found that in the OSFET, the following conditions are desirable in order to obtain a high breakdown voltage in the state where a positive potential is applied to the source electrode.

(1) The surface impurity concentration of the p-type drain drift region 4 is in the range of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁶ cm ⁻³ . (2) The diffusion depth of the p drain drift region 4 is 0.5 to
It should be in the range of 4.0 μm. (3) The impurity concentration of the silicon layer 3 is 2 × 10 ¹⁴ cm ⁻³
It should be in the range of 1 × 10 ¹⁶ cm ^-3 .

FIG. 6 shows a pMOSF according to the second embodiment of the present invention.
It is a principal part sectional view of ET. The pMOSFET has a structure similar to that of the first embodiment shown in FIG. 3, but is different in the following points. That is, p with a surface impurity concentration of 1.0 × 10 ¹⁵ cm ⁻³ and a diffusion depth of 2.0 μm is formed on the surface layer of the silicon layer 3.
That is, the type diffusion region 14 is formed and serves as both the p-type drain drift region and the p-type drain region.
In this case, the impurity concentration of the silicon layer 3 is 3 × 10.
^This is an experimental example of ¹⁴ cm ⁻³ , which is slightly lower than that of the first embodiment. The operation of this pMOSFET is the same as the conventional one.

FIG. 2 shows the source electrode potential dependency of the device breakdown voltage of the pMOSFET of FIG. The horizontal axis represents the potential of the source electrode 12 based on the potential of the substrate 1, and the vertical axis represents the element breakdown voltage, that is, the breakdown voltage between the source electrode 12 and the drain electrode 13. 150 to 17 when the source electrode potential is negative
It shows a low withstand voltage of 0 V, and is about 18 when the source electrode potential is zero.
While the withstand voltage is 0 V, the withstand voltage is improved when the source electrode potential is positive, and is 300 when the source electrode potential is 150 V.
It shows a breakdown voltage of V or more. When the source electrode potential exceeds 150V, the breakdown voltage decreases, but when the source electrode potential is 200V, a device breakdown voltage of 210V is shown, and it can be seen that the device can be applied to the circuit of FIG. In this case, the impurity concentration of the silicon layer 3 is 3 × 10.
^This is an experimental example of ¹⁴ cm ⁻³ , which is slightly lower than that of the first embodiment, and it is considered that a higher breakdown voltage can be achieved by increasing the impurity concentration of the silicon layer 3 from the dependence of FIG.

In particular, in the pMOSFET of FIG. 6, the formation of the p-type diffusion region 14 requires only one introduction of impurities as compared with the p-drain drift region 4 and the p-type drain region 8 of the first embodiment of FIG. Therefore, there is an advantage that the number of steps is reduced. FIG. 7 is a sectional view of a pMOSFET of the third embodiment of the present invention, which is a modification of the second embodiment of FIG. This p
In the MOSFET, the p-type diffusion region 14 is formed so as to be connected to the n-type base region 5, and the gate electrode 11 has the n-type base region 5 sandwiched between the p-type source region 9 and the p-type diffusion region 14. Is provided on the surface of the gate via the gate oxide film 7. The surface impurity concentration and the diffusion depth of the p-type diffusion region 14 are the same as those in the second embodiment. The depletion layer spreads to the p-type diffusion region 14 in the same manner, and a sufficiently high breakdown voltage can be obtained even when a positive potential is applied to the source electrode 12 as in the second embodiment. This pMOS
In the FET, the length of the channel generated when a voltage is applied to the gate electrode 11 can be shortened, and it is possible to achieve both a high breakdown voltage of the semiconductor element and a voltage drop during ON operation, that is, a decrease in ON voltage.

[0027]

As described above, the pMOS of the present invention is used.
In the FET, when the surface impurity concentration of the p-type drain drift region is set to 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁶ cm ⁻³ , depletion of the p-type drain drift region is promoted, and the source electrode for the substrate is formed. A p-channel MOSFET having a high withstand voltage between the source and the drain at a high potential is realized.

Furthermore, the diffusion depth of the p-type drain drift region is 0.5 to 4.0 μm, and the impurity concentration of the n-type semiconductor layer is 2 × 10 ¹⁴ to 1 × 10 ¹⁶ cm ^−3. Then, the charges of the depletion layers of the n-type semiconductor layer and the p-type drain drift region are balanced, the depletion of these regions is further promoted, and a p-channel MOSFET having a high source-drain breakdown voltage can be realized.

In particular, the p-type drain drift region and p
If the type drain regions are composed of the same p-type diffusion region, both regions can be formed at the same time, which leads to simplification of the manufacturing process and further cost reduction of the product.

[Brief description of drawings]

FIG. 1 is a p-channel MO according to the first embodiment of the present invention shown in FIG.
The figure which shows the surface impurity concentration dependence of the p-type drain drift region of the element breakdown voltage in SFET.

FIG. 2 is a diagram showing the source electrode potential dependence of the device breakdown voltage in the p-channel MOSFET of the present invention.

FIG. 3 is a p-channel MOSF according to the first embodiment of the present invention.
Sectional view of ET

4 is a p-channel MO according to the first embodiment of the present invention shown in FIG.
The figure which shows the diffusion depth dependence of the p-type diffusion region of the element breakdown voltage in SFET.

5 is a p-channel MO according to the first embodiment of the present invention shown in FIG.
The figure which shows the impurity concentration dependence of the silicon layer of the element breakdown voltage in SFET.

FIG. 6 is a p-channel type MOSF according to a second embodiment of the present invention.
Sectional view of ET

FIG. 7 is a p-channel MOSF according to the third embodiment of the present invention.
Sectional view of ET

FIG. 8 is a sectional view of a main part of a conventional p-channel MOSFET.

FIG. 9 is an application circuit diagram of a p-channel MOSFET.

FIG. 10 is a diagram showing the source electrode potential dependence of the device breakdown voltage in a conventional p-channel MOSFET.

FIG. 11 is a potential distribution diagram when a ground potential is applied to a source electrode in a conventional p-channel MOSFET.

FIG. 12 is a potential distribution diagram when a positive potential is applied to the source electrode in the conventional p-channel MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Support substrate 2 Laminated oxide film 3 Silicon layer 4 p-type drain drift region 5 n-type base region 6 LOCOS oxide film 7 gate oxide film 8 p-type drain region 9 p-type source region 10 n-type contact region 11 gate electrode 12 source electrode 13 drain electrode 14 p-type diffusion region 15 p-type contact region 100 ground 101 power supply terminal 102 output terminal 103 input terminal 104 input terminal 201 p-channel MOSFET 202 n-channel MOSFET

Claims (5)

[Claims] 1. An n-type semiconductor layer bonded on a semiconductor substrate via an insulating film, an n-type base region formed in a surface layer of the n-type semiconductor layer, and a surface layer of the n-type base region. A p-type source region formed in part, a p-type drain drift region formed in the surface layer of the n-type semiconductor layer apart from the n-type base region, and a side of the p-type drain drift region far from the n-type base region. P-type drain region formed on the surface layer of the n-type semiconductor layer connected to the p-type drain drift region, and an n-type base region and an n-type semiconductor layer sandwiched between the p-type source region and the p-type drain drift region. Of the gate electrode provided on the surface of the exposed surface of the via the gate insulating film, the thick LOCOS oxide film formed on the surface of the p-type drain drift region, and the p-type source region and the p-type drain region. It on the surface A source electrode provided which has a drain electrode, in those used as a positive potential is applied to the source electrode to the semiconductor substrate,
The surface impurity concentration of the p-type drain drift region is 1.0 ×
A p-channel type high withstand voltage MOSFET characterized in that it is 10 ^{14 to} 1.0 × 10 ¹⁶ cm ⁻³ . 2. The p-channel type high breakdown voltage MOSFET according to claim 1, wherein the diffusion depth of the p-type drain drift region is 0.5 to 4.0 μm. Wherein the impurity concentration of the n-type semiconductor layer is 2 × 10 ¹⁴ ~
3. The p-channel type high breakdown voltage MOSFET according to claim 2, wherein the p-channel type high breakdown voltage MOSFET is 1 × 10 ¹⁶ cm ⁻³ . 4. The p-channel type high breakdown voltage MOSFET according to claim 3, wherein the p-type drain drift region and the p-type drain region are formed of the same p-type diffusion region. 5. The n-type base region and the p-type drain drift region are connected to each other.
A p-channel type high breakdown voltage MOSFET according to any one of 1.