JP2008311392A - Field-effect transistor using group iii nitride transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor using a normally-off type group III nitride semiconductor, which is a normally-off operation semiconductor device, allowing a high voltage resistance and large current to be compatible. <P>SOLUTION: A MOSFET 200 includes a semiconductor layer 203 of a p type GaN layer which is formed on a substrate 201, a gate electrode 208 which is formed on a channel area 203a through a gate oxide film 205, a source electrode 206, and a drain electrode 207. contact areas 210, 211 are formed on both side of the channel area 203a, and a resurf area 212 is formed between the gate electrode 208 and a drain electrode 207. The contact areas 210, 211 are an n+ type GaN layer which is formed by implanting an n type impurity into the semiconductor layer 203 through an ion implantation method. The seat carrier concentration of the resurf area 212 is set in a range of 1×10<SP>12</SP>cm<SP>-2</SP>or more and 5×10<SP>13</SP>cm<SP>-2</SP>or less, and its sheet resistance is set in an area of 100 Ω/sq or more and 10 kΩ/sq or less to allow a high voltage resistance and large current to be compatible. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor using a normally-off group III nitride semiconductor.

As a field effect transistor using a group III nitride semiconductor, an AlGaN / GaN HEMT (see, for example, Non-Patent Document 1) or a GaN-based M0SFET (see Non-Patent Document 2) is used. These have higher breakdown voltage and saturation mobility than conventional III-group compound semiconductors such as Si, GaAs, and InP, and are suitable for power devices.
M. Kuraguchi et al., “Normally-off GaN-MISFET with well-controlled threshold voltage,” International Workshop on Nitride Semiconductors 2006 (IWN2006), Oct. 22-27, 2006, Kyoto, Japan, WeED1-4 Huang W, Khan T, Chow TP: Enhancement-Mode n-Channel GaN MOFETs on p and n- GaN / Sapphire substrates.In: 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2006 (Italy), 10-1.

  AlGaN / GaN HEMT has been widely studied as a field effect transistor using Group III nitride, but the threshold voltage was as low as +1 V. As for GaN-based MOSFETs, devices with high mobility and devices with a withstand voltage close to 1000 V have been reported, but devices that have both high mobility and high withstand voltage have not yet been realized.

  The present invention has been made in view of such conventional problems, and its purpose is a normally-off semiconductor device that uses a group III nitride semiconductor that achieves both high breakdown voltage and large current. It is to provide a field effect transistor of the type.

In order to solve the above problem, a field effect transistor using a group III nitride semiconductor according to the first aspect of the present invention is a first conductivity type semiconductor formed on a substrate using a group III nitride semiconductor. A gate electrode formed on the channel region of the semiconductor layer with a gate insulating film interposed therebetween, a source electrode and a drain electrode, and formed on both sides of the channel region of the semiconductor layer. In a field effect transistor having a second conductivity type contact region in ohmic contact with each other, the channel region of the semiconductor layer includes a RESURF region formed adjacent to the contact region on the drain side,
The sheet carrier concentration in the RESURF region is in the range of 1 × 10 ¹² cm ^{−2 to} 5 × 10 ¹³ cm ⁻² .

According to this aspect, the breakdown voltage can be increased by providing the RESURF region. In addition, the sheet carrier concentration in the RESURF region is set within the range of 1 × 10 ¹² cm ^-2 or more and 5 × 10 ¹³ cm ^-2 or less, and the sheet resistance of the RESURF region is set to 100 Ω / sq. Or more and 10 kΩ / sq. By setting it within the following range, it is possible to realize a field effect transistor using a group III nitride semiconductor that achieves both high breakdown voltage and large current.

  Here, the “RESURF field (RESURF field)” is a surface electric field relaxation region formed between the gate electrode and the drain electrode of the group III nitride semiconductor layer in order to increase the breakdown voltage.

In a field effect transistor using a group III nitride semiconductor according to another embodiment of the present invention, the sheet carrier concentration in the RESURF region is set in a range of 5 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² . It is characterized by that.

According to this aspect, by setting the sheet carrier concentration in the RESURF region within the range of 5 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² , the sheet resistance is further reduced, and the high withstand voltage and large current are reduced. Achieving balance.

  In a field effect transistor using a group III nitride semiconductor according to another aspect of the present invention, the first conductivity type semiconductor layer is a p-type GaN layer, and the RESURF region is an n-type in the p-type GaN layer. The n-type GaN layer is formed by implanting impurities by ion implantation.

  According to this aspect, it is possible to achieve both high breakdown voltage and large current in the N-channel GaN-based FET. Further, since the RESURF region is an n-type GaN layer formed by implanting an n-type impurity into the p-type GaN layer by an ion implantation method, the sheet carrier concentration is not much higher than the p-type impurity concentration of the p-type GaN layer. Not affected.

In a field effect transistor using a group III nitride semiconductor according to another embodiment of the present invention, the p-type impurity concentration of the semiconductor layer which is a p-type GaN layer is 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ^−. It is characterized by being set within the range of ³ or less.

According to this aspect, the p-type impurity concentration of the semiconductor layer which is a p-type GaN layer is set in a range of 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, so that a normally-off type field transistor For example, in a MOS field effect transistor, a normally-off operation with a high threshold, for example, a threshold of about 3-5 (V) can be realized.

Further, the first conductive semiconductor layer (p-type GaN layer) has the same film thickness, and the breakdown voltage decreases as the p-type impurity concentration (for example, Mg concentration) increases. This is because when the p-type impurity concentration is high, the depletion layer becomes narrower under the n + layer on the drain side (the second conductivity type contact region that is in ohmic contact with the drain electrode), so that the electric field concentrates and breaks. is there. By setting the p-type impurity concentration (acceptor concentration) of the semiconductor layer, which is a p-type GaN layer, within the range of 1 x 10 ¹⁵ cm ^-3 or more and 5 x 10 ¹⁷ cm ^-3 or less, the threshold for normally-off operation is set. However, as a result of extensive studies by the present inventors, it has been found that the p-type impurity concentration is related not only to the threshold value but also to the breakdown voltage. In other words, it was found that the breakdown voltage drops when the p-type impurity concentration is high for the above reason. By setting the p-type impurity concentration within a range of 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, it is possible to suppress a decrease in breakdown voltage.

  In a field effect transistor using a group III nitride semiconductor according to another aspect of the present invention, the RESURF region is composed of a plurality of regions having different sheet carrier concentrations, and the sheet carrier concentration is higher in the region on the drain electrode side. The region on the gate electrode side is low.

  According to this aspect, the strength of the electric field generated in each part of the semiconductor layer on the drain side below the gate electrode and the semiconductor layer at the drain end can be made smaller than the breakdown electric field. As a result, the electric field concentration is more relaxed and a higher breakdown voltage is obtained than in the case of one RESURF region.

  A field effect transistor using a group III nitride semiconductor according to another aspect of the present invention is characterized in that the group III element used in the semiconductor layer is at least one of B, Al, Ga, and In.

  A field effect transistor using a group III nitride semiconductor according to another aspect of the present invention is a normally-off type MOS field effect transistor.

  According to this aspect, in the normally-off type MOS field transistor, a normally-off operation with a high threshold, for example, a threshold of about 3-5 (V) can be realized.

  According to the present invention, a normally-off field effect transistor having a high breakdown voltage and a large current can be realized. In particular, GaN-based field effect transistors using GaN as a group III nitride semiconductor have the potential to achieve higher withstand voltage and lower on-resistance than conventional Si-based electronic devices. This can greatly contribute to downsizing.

Next, embodiments embodying the present invention will be described with reference to the drawings. In the description of each embodiment, similar parts are denoted by the same reference numerals, and redundant description is omitted.
(First embodiment)
A field effect transistor using a group III nitride semiconductor according to the first embodiment will be described with reference to FIGS. This field effect transistor is a normally-off type MOS field effect transistor (hereinafter referred to as a MOSFET).

  As shown in FIG. 1, the MOSFET 200 includes a substrate 201, a semiconductor layer 203 of a first conductivity type formed on the substrate 201 using a group III nitride semiconductor, and a gate oxide on a channel region 203a of the semiconductor layer 203. A gate electrode 208 formed through a film (gate insulating film) 205, a source electrode 206, and a drain electrode 207 are provided. The MOSFET 200 includes contact regions 210 and 211 of second conductivity type formed on both sides of the channel region 203a of the semiconductor layer 203 and in ohmic contact with the source electrode 206 and the drain electrode 207, respectively. The MOSFET 200 further includes a RESURF region 212 formed between the gate electrode 208 and the drain electrode 207 in the channel region 203 a of the semiconductor layer 203.

  In the MOSFET 200, a sapphire substrate, a Si substrate, or the like is used as the substrate 201.

The first conductivity type semiconductor layer 203 uses p-type conductivity formed by epitaxially growing on the substrate 201 p-type impurities, for example, GaN doped with a predetermined amount of Mg, using GaN as a group III nitride semiconductor. Type GaN layer. The gate oxide film 205 is, for example, a SiO ₂ film.

  The second conductivity type contact region 210 is an n + type GaN layer (n + type source) having an n type conductivity formed by implanting an n type impurity such as Si into the semiconductor layer 203 which is a p type GaN layer by an ion implantation method. Area). Similarly, the second conductivity type contact region 211 is an n + type GaN layer (n + type drain region) having n type conductivity formed by implanting an n type impurity such as Si into the semiconductor layer 203 by ion implantation. It is.

  A RESURF field (RESURF field) 212 is a surface electric field relaxation region formed between the gate electrode 208 and the drain electrode 207 of the semiconductor layer 203 in order to increase the breakdown voltage. The RESURF region 212 is an n-type GaN layer formed by implanting an n-type impurity, such as Si, into the semiconductor layer 203, which is a p-type GaN layer, by ion implantation.

  Thus, MOSFET 200 is an N-channel MOSFET (N-channel MOSFET).

  Like the GaN-based MOSFET 200, in the RESURF type MOSFET having the RESURF region 212, when the carrier concentration of the RESURF region 212 (n-type impurity concentration such as Si) is low, the semiconductor at the drain end (semiconductor which is a p-type GaN layer) Layer 203) causes dielectric breakdown. On the other hand, when the carrier concentration of the RESURF region 212 is high, dielectric breakdown is caused in the semiconductor on the drain side below the gate electrode 208. However, in most cases, since the electric field density between the gate electrode 208 and the RESURF region 212 is increased, the gate oxide film 205 causes dielectric breakdown at a voltage lower than that in the semiconductor layer 203. Therefore, the carrier concentration in the resurf region 212 has an optimum concentration. By the way, when the carrier concentration in the RESURF region 212 is low, the resistance in the RESURF region 212 is increased and the current is reduced. As described above, the carrier concentration in the RESURF region 212 needs to be increased to some extent, but if the carrier concentration is increased too much, the breakdown voltage is lowered.

Therefore, in the first embodiment, in the GaN-based MOSFET 200, the sheet carrier concentration in the resurf region 212 is 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less in order to achieve both high breakdown voltage and large current. The sheet resistance of the RESURF region 212 is set within a range of 100 Ω / sq. To 10 ΩW / sq.
(Relation between the sheet resistance of the RESURF region 212 and the drain current)
FIG. 2 is a schematic diagram showing each resistance of the current path in the GaN-based MOSFET 200 described in FIG. The on-resistance R _NR of an NR (Non-RESURF) MOSFET without a RESURF region is the resistance component R _con existing between the source electrode and the contact region (n + type GaN layer), the channel resistance R _ch, and the drain electrode This is the series resistance with the resistance component R _con existing between the contact regions (n + type GaN layer). On the other hand, the on-resistance of the GaN-based MOSFET 200 which is a RESURF type MOSFET having the RESURF region 212 is a value obtained by adding the resistance component R _RES of the RESURF region 212 to the channel resistance R _ch .

The drain current I _d of the NR (Non-RESURF) MOSFET is expressed by the following equation.

W _ch and L _ch are the channel width and channel length, respectively. _μNR is the mobility in the NR MOSFET. That is, the mobility after the influence of resistance at the source / drain contact portion and channel. C _ox is the oxide film capacitance. V _g , V _th , and V _ds are a gate voltage, a threshold voltage, and a drain voltage, respectively. ε ₀ and ε _ox are the dielectric constant of the vacuum and the relative dielectric constant of the oxide film, respectively. S and _dox are the area and thickness of the gate oxide film, respectively.

The drain current I _{d, RES} of the GaN-based MOSFET 200 that is a RESURF type MOSFET is expressed by the following equation.

但し，L_RESはリサーフ長（リサーフ領域２１２の長さ）である。R_RES,sheetはリサーフ領域２１２のシート抵抗である。

However, L _RES is the RESURF length (the length of the RESURF region 212). R _{RES, sheet} is the sheet resistance of the RESURF region 212.

FIG. 3 shows the relationship between the sheet resistance Rs (Ω / sq.) Of the RESURF region 212 and the drain current Id (A). In FIG. 3, the horizontal axis represents the sheet resistance Rs (Ω / sq.), The right vertical axis represents the drain current Id (A), and the left vertical axis represents the sheet carrier concentration Ns (cm ^{− in the} RESURF region 212). ² ) and breakdown voltage BV (V) are shown respectively.

  Further, in FIG. 3, the straight line (1) shows the change in the sheet carrier concentration Ns, the straight line (2) shows the change in the withstand voltage BV, the straight line (3) shows the drain current Id without the RESURF region, and the curve (4). , (5), (6), and (7) respectively show changes in the drain current Id when the RESURF length (the length of the RESURF region 212) is 5 um, 10 um, 20 um, and 30 um. The calculation results shown in FIG. 3 are for a gate width of 200 mm.

From the calculation results shown in FIG. 3, when the sheet resistance is 10 kΩ / sq. Or less, the drain current is 10 A or more. In other words, it was found that the sheet resistance should be 10 KΩ / sq. (1 × 10 ⁴ Ω / sq.) Or less in order to make the drain current at a practical level of 10 A or more.

If the sheet resistance is greater than 1 × 10 ⁴ Ω / sq., The drain current will be too small, which is not good. On the other hand, as for the lower limit of sheet resistance (1 × 10 ² Ω / sq. Or more), even if the sheet resistance is smaller than 1 × 10 ² Ω / sq. The lower limit of resistance is (1 × 10 ² Ω / sq. Or more).

  Thus, as a result of intensive studies by the present inventors, in order to obtain a drain current of a practical level of 10 A or more, the sheet resistance of the RESURF region 212 is in a range of 100 Ω / sq. To 10 kΩ / sq. It was found that it is preferable to set (control) within the range indicated by the symbol A in FIG.

From FIG. 3, when the sheet resistance of the RESURF region 212 is set within the range of 100 Ω / sq. To 10 kΩ / sq., The withstand voltage BV is approximately 1 × 10 ^{4 to} 5 × 10 ⁵ (V). It can be seen that the sheet carrier concentration Ns (cm ⁻² ) is in the range of approximately 1 × 10 ¹³ (cm ⁻² ) to 1 × 10 ¹⁵ (cm ⁻² ).

FIG. 4 shows the relationship between the sheet carrier concentration in the RESURF region 212 and the sheet resistance. From FIG. 4 as well, in order for the sheet resistance to be 10 kΩ / sq. (1 × 10 ⁴ Ω / sq.) Or less, the sheet carrier concentration must be 5 × 10 ¹² cm ⁻² or more. I understand.

As described above, in the first embodiment, in the GaN-based MOSFET 200, the sheet carrier concentration in the resurf region 212 is set to 1 × 10 ¹² cm ⁻² or more and 5 × 10 ¹³ cm ⁻² or less in order to achieve both high breakdown voltage and large current. And the sheet resistance of the RESURF region 212 is set within a range of 100 Ω / sq. To 10 kΩ / sq.

In the normally-off type MOS field effect transistor (MOSFET) 200, in order to realize a normally-off operation with a high threshold, for example, a threshold of 3-5 (V), a semiconductor that is a p-type GaN layer. The acceptor concentration, for example, the Mg concentration of the layer 203 may be controlled within the range of 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ .

Next, a method for manufacturing the GaN-based MOSFET 200 according to the first embodiment shown in FIG. 1 will be described.
[Crystal growth process]
First, a p-type GaN layer (semiconductor layer 203) is epitaxially grown on a sapphire substrate (substrate 201) by MOCVD (metal organic chemical vapor deposition). Mg is used as the dopant, and the Mg concentration is controlled from 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ .

  Instead of the MOCVD method described above, an HVPE method (halide vapor phase epitaxy method), an MBE method (molecular beam epitaxy method), or the like may be used. Further, Si, SiC, ZrB2 or the like may be used as the substrate 201. Further, Be, Zn, C or the like may be used as the dopant.

[Element isolation]
Next, a photoresist is applied to the surface of the p-type GaN layer (semiconductor layer 203), and patterning for element isolation is performed through a photolithography process.

  Next, the p-type GaN layer is etched using a dry etching apparatus (ICP, RIE, etc.). Next, the photoresist is removed with acetone. As a result, element isolation is performed.

[Implanting process]
Next, a first mask layer (SiO2) having a thickness of about 1 μm is formed.
Next, an opening for the contact region (n + type GaN layer: n + type source region) 210 and an opening for the contact region (n + type GaN layer: n + type drain region) 211 are formed by a photo process.
Next, toward the opening of the first mask layer, Si (silicon) is dosed by ion implantation with a dose amount of 3 × 10 ¹⁴ cm ⁻³ , an acceleration voltage of 30 keV, a dose amount of 4 × 10 ¹⁴ cm ⁻³ , and an acceleration voltage of 60 Four-step implantation is performed with keV, a dose of 8 × 10 ¹⁴ cm ^-3 , an acceleration voltage of 120 keV, a dose of 1.5 × 10 ¹⁵ cm ^-3 , and an acceleration voltage of 160 keV. As a result, a contact region 210 that is an n + type source region and a contact region 211 that is an n + type drain region are formed. However, the contact regions 210 and 211 formed here are not activated by the ion-implanted impurities.
Next, the first mask layer is removed with a hydrofluoric acid aqueous solution.

[Resurf region formation process]
Next, a second mask layer (SiO2) having a thickness of about 1 μm is formed. Next, an opening for the RESURF region 212 is formed by a photo process.

Next, toward the opening of the second mask layer, Si (silicon) is dosed by ion implantation at a dose of 1 × 10 ¹³ cm ⁻³ , an acceleration voltage of 30 keV, a dose of 1.4 × 10 ¹³ cm ⁻³ , and an acceleration voltage of 60 Four-stage implantation is performed with keV, a dose of 2.6 × 10 ¹³ cm ^-3 , an acceleration voltage of 120 keV, a dose of 5 × 10 ¹³ cm ^-3 , and an acceleration voltage of 160 keV. As a result, a RESURF region 212 (but before activation of the ion-implanted impurity) is formed.
Next, the second mask layer is removed with a hydrofluoric acid aqueous solution.
Note that the dose amount of the RESURF region 212 may be changed according to the activation rate.
Next, a third mask layer (SiO2 layer) is formed to about 500 nm on the entire top surface of the device.
Next, the device is annealed at 1260 ^° C for 30 seconds in an N (nitrogen) atmosphere. Thereby, the ion-implanted impurity is activated.
Next, the third mask layer is removed with a hydrofluoric acid aqueous solution.

[Ohmic formation process]
Next, a gate oxide film (SiO 2 layer) 205 is formed on the p-type GaN layer (semiconductor layer 203).
Next, an opening for the source electrode 206 and an opening for the drain electrode 207 are formed in the gate oxide film 205 by a photo process.
Next, ohmic electrodes (source electrode 206 and drain electrode 207) made of Ti / Al are formed on the p-type GaN layer exposed from the opening of the gate oxide film 205.
The ohmic electrode may be an electrode other than Ti / Al as long as ohmic contact is realized.

[Gate formation process]
Next, poly-Si is deposited on the entire surface of the device by LPCVD or sputtering.
Next, poly-Si is doped at 900 ° C for 20 minutes in a thermal diffusion furnace filled with POCl ₃ gas.
Next, a photo process is performed so that poly-Si remains between the source electrode 206 and the drain electrode 207. Thereby, the gate electrode 208 is formed.
The poly-Si doping method may be a thermal diffusion method after P deposition. The gate electrode 208 may be Au, Pt, Ni, or the like.
Through the above steps, MOSFET 200 shown in FIG. 1 can be manufactured.
According to 1st Embodiment comprised as mentioned above, there exist the following effects.

  O By providing the RESURF region 212 in the MOSFET 200, the breakdown voltage can be increased.

○ The sheet carrier concentration in the RESURF region 212 is set within the range of 1 × 10 ¹² cm ^-2 or more and 5 × 10 ¹³ cm ^-2 or less, and the sheet resistance of the RESURF region is set to 100 Ω / sq. Or more and 10 kΩ / sq. By setting within the following range, a normally-off type MOSFET 200 that achieves both high breakdown voltage and large current can be realized.

○ By setting the sheet carrier concentration in the RESURF region 212 within the range of 5 × 10 ¹² cm ^-2 or more and 5 × 10 ¹³ cm ^-2 , the sheet resistance becomes smaller, higher withstand voltage and higher current normally off. Type MOSFET 200 can be realized.

  O In the N-channel GaN-based MOSFET 200, the semiconductor layer 203 is a p-type GaN layer and the RESURF region 212 is an n-type GaN layer, so that both high breakdown voltage and large current can be achieved.

  The RESURF region 212 is an n-type GaN layer formed by implanting an n-type impurity into the semiconductor layer 203, which is a p-type GaN layer, by an ion implantation method. Therefore, the sheet carrier concentration is the p-type impurity of the p-type GaN layer. It is not affected much by concentration.

○ By setting the p-type impurity concentration of the semiconductor layer 203, which is a p-type GaN layer, within the range of 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, the normally-off type MOSFET 200 has a threshold value. For example, a normally-off operation with a threshold value of about 3-5 (V) can be realized.

○ With the same film thickness of the semiconductor layer (p-type GaN layer) 203, the breakdown voltage decreases as the p-type impurity concentration (for example, Mg concentration) increases. This is because when the p-type impurity concentration is high, the depletion layer is narrowed below the n + layer on the drain side (contact region 211 in ohmic contact with the drain electrode 207), and the electric field concentrates and breaks. Increasing the threshold value of normally-off operation by setting the p-type impurity concentration of the semiconductor layer 203, which is a p-type GaN layer, within a range of 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less. However, as a result of intensive studies by the present inventors, it has been found that the p-type impurity concentration is related not only to the threshold value but also to the breakdown voltage. In other words, it was found that the breakdown voltage drops when the p-type impurity concentration is high for the above reason. By setting the p-type impurity concentration within a range of 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁷ cm ⁻³ or less, it is possible to suppress a decrease in breakdown voltage.

(Second Embodiment)
Next, a field effect transistor using a group III nitride semiconductor according to the second embodiment will be described with reference to FIG.

  The normally-off type MOS field effect transistor (MOSFET) 200 described in the first embodiment includes one resurf region 212. On the other hand, a field effect transistor (MOSFET) 200A using a group III nitride semiconductor according to the second embodiment includes two pieces formed side by side in the lateral direction (the X direction shown in FIG. 6A). Resurf regions 221 and 222 are provided. Of the two RESURF regions 221, 222, the carrier concentration of the RESURF region 222 on the gate electrode 208 side (doping concentration of n-type impurities such as Si) is lowered, and the carrier concentration of the RESURF region 221 on the drain electrode 207 side is reduced. To increase. Other configurations of the MOSFET 200A are the same as those of the MOSFET 200 of the first embodiment.

  Next, the difference in operation and effect between the MOSFET 200 and the MOSFET 200A will be described with reference to FIGS. 6 (A) and 6 (B) and FIGS. 7 (A) and 7 (B). 6A is a cross-sectional view showing a schematic configuration of the MOSFET 200 described in FIG. 1, and FIG. 6B is a graph showing the electric field strength at each position of the MOSFET 200. FIG. Similarly, FIG. 7A is a cross-sectional view showing a schematic configuration of the MOSFET 200A according to the second embodiment, and FIG. 7B is a graph showing the electric field strength at each position of the MOSFET 200A.

  In the MOSFET 200 having one resurf region 212, when the carrier concentration of the resurf region 212 (doping concentration of n-type impurities such as Si) is high (dense), as shown by a curve 230 in FIG. An electric field having a strength exceeding the breakdown electric field (3 MV / cm in the case of GaN) is generated in the semiconductor layer 203 on the lower drain side 208. As a result, the gate oxide film 205 causes dielectric breakdown at a dielectric breakdown voltage lower than that of the semiconductor layer 203. On the other hand, when the carrier concentration in the RESURF region 212 is low (thin), an electric field having a strength exceeding the breakdown electric field is generated in the semiconductor layer 203 at the drain end as shown by a curve 231 in FIG. This causes dielectric breakdown in the semiconductor layer 203 at the drain end. Therefore, the carrier concentration in the resurf region 212 has an optimum concentration.

  On the other hand, in the MOSFET 200A provided with the two resurf regions 221 and 222, the resurf region on the gate electrode 208 side of the two resurf regions 221 and 222 formed in the horizontal direction (X direction). The carrier concentration of 222 is decreased (n-layer), and the carrier concentration of the RESURF region 221 on the drain electrode 207 side is increased (n layer) (see FIG. 7A). Accordingly, as indicated by a curve 232 in FIG. 7B, an electric field having a strength exceeding the breakdown electric field is present in any part of the semiconductor layer 203 on the drain side below the gate electrode 208 and the semiconductor layer 203 on the drain end. Does not occur.

  According to 2nd Embodiment comprised as mentioned above, in addition to the effect which the said 1st Embodiment show | plays, there exist the following effects.

  O Two RESURF regions 221 and 222 are provided, the carrier concentration of the RESURF region 222 on the gate electrode 208 side is lowered, and the carrier concentration of the RESURF region 221 on the drain electrode 207 side is increased. Thereby, the strength of the electric field generated in each portion of the semiconductor layer 203 on the drain side below the gate electrode 208 and the semiconductor layer 203 at the drain end can be made smaller than the dielectric breakdown electric field. Thereby, when the number of the RESURF regions is two, the electric field concentration is more relaxed and the higher withstand voltage is obtained than when the RESURF region is one.

  This is for the following reason. When there is one resurf region, the electric field concentrates on the interface between the contact region (n + type GaN layer) 211 and the resurf region 212 and on the interface between the resurf region 212 and the semiconductor layer (p-type GaN layer) 203. Divided into locations. On the other hand, when there are two RESURF regions, the electric field concentrates at three locations: the interface between the contact region 211 and the RESURF region 221, the interface between the RESURF region 221 and the RESURF region 222, and the interface between the RESURF region 222 and the semiconductor layer 203. Therefore, the electric field concentration is divided into three places. Therefore, the electric field concentration is more relaxed in the case of two RESURF regions than in the case of one RESURF region.

  When there are three or more RESURF regions, as in the case of two RESURF regions, the electric field concentration is further relaxed and a higher breakdown voltage is obtained.

In addition, this invention can also be changed and embodied as follows.
In each of the above embodiments, the MOSFETs 200 and 200A that are N-channel MOSFETs (N-channel MOSFETs) have been described. However, the present invention is also applicable to P-channel MOSFETs (P-channel MOSFETs).

Sectional drawing which shows the field effect transistor which concerns on 1st Embodiment of this invention. The schematic diagram which showed each resistance of the current pathway in the field effect transistor which concerns on 1st Embodiment. The graph which showed the relationship between the sheet resistance of a RESURF area | region, and drain current with the pressure | voltage resistance and the sheet carrier density | concentration of a RESURF area | region. The graph which shows the relationship between a sheet carrier concentration and sheet resistance. Sectional drawing which shows the field effect transistor which concerns on 2nd Embodiment of this invention. (A) is sectional drawing which shows schematic structure of the field effect transistor which concerns on 1st Embodiment, (B) is a graph which shows the electric field strength in each position of the field effect transistor. (A) is sectional drawing which shows schematic structure of the field effect transistor which concerns on 2nd Embodiment, (B) is a graph which shows the electric field strength in each position of the field effect transistor.

Explanation of symbols

200, 200A Field effect transistor (MOSFET)
201 ... Substrate 203 ... First conductivity type semiconductor layer (p-type GaN layer)
203a ... Channel region 205 ... Gate oxide film (gate insulating film)
206 ... Source electrode 207 ... Drain electrode 208 ... Gate electrode 210, 211 ... Second conductivity type contact region (n + type GaN layer)
212 ... Resurf region (n-type GaN layer)
221, 222 ... RESURF area

Claims (5)

A semiconductor layer of a first conductivity type formed using a group III nitride semiconductor on a substrate; a gate electrode formed on a channel region of the semiconductor layer through a gate insulating film; a source electrode and a drain electrode; In a field effect transistor using a group III nitride semiconductor formed on both sides of the channel region of the semiconductor layer and having a second conductivity type contact region that is in ohmic contact with each of the source electrode and the drain electrode,
In the channel region of the semiconductor layer, comprising a RESURF region formed adjacent to the contact region on the drain side,
A field effect transistor using a group III nitride semiconductor, wherein a sheet carrier concentration in the RESURF region is in a range of 1 × 10 ¹² cm ^{−2 to} 5 × 10 ¹³ cm ⁻² . The semiconductor layer of the first conductivity type is a p-type GaN layer,
2. The electric field using a group III nitride semiconductor according to claim 1, wherein the RESURF region is an n-type GaN layer formed by implanting an n-type impurity into the p-type GaN layer by an ion implantation method. Effect transistor. 3. The group III according to claim 2, wherein a p-type impurity concentration of the semiconductor layer which is a p-type GaN layer is set in a range of 1 × 10 ¹⁵ cm ^{−3 to} 5 × 10 ¹⁷ cm ^−3. Field effect transistor using nitride semiconductor.   4. The RESURF region is composed of a plurality of regions having different sheet carrier concentrations, and the sheet carrier concentration is high in a region on the drain electrode side and low in a region on the gate electrode side. A field effect transistor using the group III nitride semiconductor according to one.   5. The field effect transistor using a group III nitride semiconductor according to claim 1, wherein the field effect transistor is a normally-off type MOS field effect transistor.

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