JPH0521800A - Soimosfet - Google Patents

Abstract

PURPOSE:To provide an SOIMOSFET which enables the control of a threshold voltage maintaining it high speed operation. CONSTITUTION:This SOIMOSFET includes layers 9-13 that is, N<+>-P- -i-P--N<+>, shown in the drawing, constituted by implanting oxygen ions into an Si single crystal to form a dielectric layer 1 of SiO2, thus separating the Si single crystal into two parts, an Si substrate (not shown) and an SOI film 8 isolated form each other by the dielectric film 1, and implanting impurities into the SOI film 8 on the dielectric layer 1. A gate electrode 6 is formed on the P--i-P- layers 10-12, a source electrode being formed on one N<+> layer 9, and a drain electrode being formed on the other N<+> layer 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI MOSFET (Silico) having a structure in which a single crystal is separated by an insulating layer.
n-On-Insulator-MOSFET).

[0002]

2. Description of the Related Art The structure of a conventional N-type SOI MOSFET is shown in FIG. This SOI MOSFET is manufactured by using, for example, an SOI substrate manufacturing method called SIMOX.
SiO ₂ Ya by implanting oxygen ions and nitrogen ions in the single crystal
An insulating layer 1 such as Si ₃ N ₄ is formed, the insulating layer 1 separates a Si single crystal into a Si substrate (not shown) and an SOI film 2, and the SOI film 2 on the insulating layer 1 is further doped with impurities. Is added to provide N ⁺ -P ^-- N ⁺ layers 3 to 5 as shown in the figure. Then, the gate electrode 6 is formed on the P ⁻ layer 4.
And a source electrode on one N ⁺ layer 3,
A drain electrode is provided on the other N ⁺ layer 5. Also, P is the channel layer ^- due to its high electron mobility lower the impurity concentration of the layer 4, the SOIMOSFET more for high-speed operation, the P ^- impurity layer 4 as possible remove, the intrinsic semiconductor There is known an SOI MOSFET shown in FIG. 3B in which the i layer 7 in a close state is used as a channel layer. Since the i layer 7 contains impurities at a very low concentration, it actually has N-type or P-type polarity, but ideally, it is an intrinsic semiconductor and is almost the same. Since it is a characteristic, it will be described below as an intrinsic semiconductor.

The SOI MOSFET shown in FIG. 3 (B)
Since the channel layer is the intrinsic semiconductor i layer 7, the gate electrode 6 must use an electrode having a polarity opposite to that of the source and drain layers manufactured by mixing impurities into polysilicon. , The source and drain layers are N ⁺ layers 3, 5
, The gate electrode 6 has a P ⁺ type polarity, and when the source layer and the drain layer are P ⁺ layers, the gate electrode 6 does not operate as an SOIMOSFET unless it has an N ⁺ type polarity. ..

[0004]

The threshold voltage of MOSFET is determined by the impurity concentration of the channel layer. However, if the channel layer is a low-concentration semiconductor close to an intrinsic semiconductor in order to operate the SOIMOSFET at high speed,
Since almost no impurities were mixed in, the threshold voltage could not be changed and was fixed at a fixed value.
There is a problem that the threshold voltage cannot be controlled to a desired value during designing and manufacturing. Therefore, the present invention provides an SOI in which the threshold voltage can be controlled while maintaining high-speed operation.
An object is to provide a MOSFET.

[0005]

As a means for achieving the above object, a channel layer containing a very low concentration of impurities is provided between a source layer having a high concentration first conductivity type and a drain layer. SOIMO with SOI film on insulating film
An SFET is provided which is characterized in that a layer having a low concentration second conductivity type is provided between the source layer and the channel layer and between the drain layer and the channel layer, respectively. To do.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the SOI MOSFET of the present invention will be described with reference to the drawings. FIG. 1 shows an example of an N-type SOI MOSFET. This SOI MOSFET is formed by implanting oxygen ions or nitrogen ions into a Si single crystal to produce SiO ₂ or Si ₃ N.
An insulating layer 1 such as ₄ is formed, the Si single crystal is separated by this insulating layer 1 into a Si substrate (not shown) and an SOI film 8, and an impurity is implanted into the SOI film 8 on the insulating layer 1. so,
N ⁺ -P ^-- i-P ^-- N ⁺ layers 9 to 13 as shown in the figure
Is provided. And this P ^-- i--P ^-- layer 1
A gate electrode 6 is provided on 0 to 12, a source electrode is provided on one N ⁺ layer 9, and a drain electrode is provided on the other N ⁺ layer 13. The i layer 11 also contains an extremely low concentration of impurities and actually has N-type or P-type polarity, but it will be described as an intrinsic semiconductor.

The N-type SOIMOSFE shown in FIG.
A method of manufacturing T will be described with reference to FIGS. In the same figure (A), by implanting oxygen ions into the Si single crystal
An insulating layer 1 of SiO ₂ is formed, and this insulating layer 1 separates a Si single crystal into a Si substrate (not shown) and an SOI film 8.
Then, a reduced pressure C is applied on the SOI film 8 on the SiO ₂ insulating film 1.
A polysilicon gate electrode 6 is provided by the VD method, and B (boron) is formed on the SOI film 8 using the gate electrode 6 as a mask.
Ions are implanted to form P ⁻ layers 14 and 15. Next, as shown in FIG. 7B, the P ^- layers 14 and 15 formed on the SOI film 8 are similarly patterned with As using the gate electrode 6 as a mask.
Further implanting (arsenic) ions, the P ⁻ + N ⁺ layer 16,
Form 17. Since the amount of thermal diffusion of B ions is larger than that of As ions, if thermal diffusion is performed in this state,
B ion diffuses toward the central i-layer 11 side, and P ⁻ + N ⁺ layer 1
6, 17 are N ⁺ layers 9 and 13 as shown in FIG.
And the P ⁻ layers 10 and 12 are separated from each other, and the SOI film 8 is N ⁺ −
The layers 9 to 13 are P ⁻ −i−P ⁻ −N ⁺ layers. afterwards,
By providing a source electrode and a drain electrode on the N ⁺ layers 9 and 13, respectively, the SOIMO shown in FIG.
SFETs can be manufactured. Such an SOIM
Since the OSFET uses an intrinsic semiconductor for the channel layer, it can maintain a high-speed operation, and the threshold voltage can be changed by changing the impurity concentration of the P ⁻ layers 10 and 12.

The SOI MOSFET described above is an SO
The I film 8 is an N-type SOIMOSFET composed of N ⁺ -P ^-- i-P ^-- N ⁺ layers 9 to 13, and the SOI film is P ⁺ -N ^-- i-N ^-- P ⁺ layers. P type SO consisting of
Of course, it may be an IMOSFET. Also,
By using the P ⁻ −i−P ⁻ layer or the N ⁻ −i−N ⁻ layer, the SOIMOSF can be formed regardless of the polarity of the gate electrode.
The ET operates, and the threshold voltage can be controlled by changing the impurity concentration of the P ⁻ layer or the N ⁻ layer. Therefore, in both P-type and N-type SOI MOSFETs, an N ⁺ -type gate electrode is used. Polysilicon can be used.

[0009]

The SOI MOSFET of the present invention has an SOI having a channel layer containing a very low concentration of impurities between a source layer having a high concentration first conductivity type and a drain layer.
In the SOIMOSFET in which the film is provided on the insulating film, the low-concentration second conductivity type layer is provided between the source layer and the channel layer and between the drain layer and the channel layer. By changing the impurity concentration of the low-concentration layer having the second conductivity type, the threshold voltage can be controlled while maintaining high-speed operation. Further, since the layer having the low concentration second conductivity type is provided, there is an effect that the same gate electrode (for example, N ⁺ type gate electrode) can be used regardless of the polarity of the SOIMOSFET.

[Brief description of drawings]

FIG. 1 is a structural diagram showing one embodiment of an SOIMOSFET of the present invention.

2A to 2C are process diagrams showing a manufacturing method of the embodiment shown in FIG.

3A and 3B are structural views showing a conventional example.

[Explanation of symbols]

1 Insulating layer 2,8 SOI layer 3,9 N ⁺ layer (source layer having high concentration first conductivity type) 4 P ^- layer (channel layer) 5,13 N ⁺ layer (high concentration first conductivity type) Type drain layer) 6 gate electrode 7,11 i layer (channel layer) 10, 12 P ^- layer (layer having low concentration second conductivity type)

Claims (1)

1. An SOI film having a channel layer containing a very low concentration of impurities between a source layer having a high concentration of a first conductivity type and a drain layer is provided on an insulating film. SOIMOS
In the FET, a SOI layer having a low concentration second conductivity type is provided between the source layer and the channel layer and between the drain layer and the channel layer, respectively.
SFET.