JPH07183498A - Semiconductor device - Google Patents

Abstract

PURPOSE:To ensure a sufficient saturation current while a stable high breakdown strength is maintained by a method wherein the drain offset region of a high-voltage MIS transistor is composed of an upper layer and a lower layer and the upper layer is a low impurity concentration region and the lower layer is a medium impurity concentration region. CONSTITUTION:After a P<-->-type offset region (low impurity concentration drain region) 7 is formed over a whole drain forming region by low acceleration ion implantation, a P<->-type offset region (medium impurity concentration drain region) 8 is formed under the region 7 by high acceleration ion implantation. Or, the counter-doping of N<-->-type which is the opposite conductivity type is applied over the whole drain forming region beforehand by low acceleration ion implantation and then a P<->-type offset region (medium impurity concentration drain region) 8 is formed to form a P<-->-type low impurity concentration drain region 7 near the surface only. Finally, a P<+>-type high impurity concentration drain region 6b is formed in the center part of the drain region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high breakdown voltage transistor.

[0002]

2. Description of the Related Art In a high breakdown voltage transistor, for example, a MIS type high breakdown voltage transistor, the breakdown voltage is -50 to -60V.
Is required. In order to achieve such a high breakdown voltage, an offset structure is essential in the drain region to which a high voltage is applied. In the offset structure, the drain region in contact with the gate region has a low concentration, and the high concentration drain region serving as an electrode is formed apart from the gate.

A conventional semiconductor device will be described with reference to FIG. FIG. 6 is a sectional view showing the structure of a conventional semiconductor device.

In FIG. 6, 1 is an N-type semiconductor substrate, 2 is a LOCOS region which is an element isolation region, 3 is a gate insulating film of a high breakdown voltage transistor, 4 is a polysilicon gate electrode of a high breakdown voltage transistor, 5 is a sidewall, 6a is a P-type high-concentration source region. 6b is a P-type high-concentration drain region, 7 is a low-concentration drain region, and the drain region has an offset structure.

[0005]

In such a conventional semiconductor device, when the impurity concentration of the low concentration drain region 7 is set to a low concentration, for example, about 10 ¹⁶ to 10 ¹⁷ / cm ³ , the low concentration drain region 7 is formed. The resistance becomes high, and it becomes difficult for the channel current of the high breakdown voltage transistor to flow. That is, it becomes difficult to secure the on-current. In this case, the ON current can be secured by widening the gate width, but there is a problem that the circuit size becomes large because the transistor size becomes large due to the widening of the gate width.

On the other hand, when the impurity concentration in the low concentration drain region is increased, the impurity concentration is increased to about 10 ¹⁷ to 10 ¹⁸ , for example.
It is easy to secure the on-current by increasing the number to the number / cm ³ , but when a high voltage is applied to the drain region, the electric field density is concentrated near the boundary between the gate insulating film 3 and the low-concentration drain region 7. In the boundary area, electrical stress increases and breakdown easily occurs. Therefore,
The electric charge generated due to the increase of the electrical stress and the breakdown induces the deterioration and the breakdown of the gate insulating film, which causes the deterioration of the characteristics of the high breakdown voltage transistor.
Therefore, there is a problem that reliability cannot be maintained.

An object of the present invention is to solve the above problems, and an object of the present invention is to provide a semiconductor device having a high breakdown voltage transistor capable of ensuring a sufficient on-current of the transistor while maintaining high reliability.

[0008]

In order to achieve the above object, the present invention provides a source region and a drain region of a second conductivity type which are provided on a surface of a semiconductor substrate of a first conductivity type and are separated from each other, and the source region. And a semiconductor having a transistor formed of a gate electrode provided on the surface of the semiconductor substrate sandwiched between the drain region and a gate insulating film, and a region of the drain region forming the transistor in contact with the gate insulating film and the semiconductor Part of the region in contact with the substrate surface is a low concentration region, the remaining region in contact with the semiconductor substrate surface is a high concentration region, and the regions immediately below the low concentration region and the high concentration region are medium concentration regions. It is characterized by.

[0009]

According to the present invention, the region of the drain region in contact with the insulating film has a low concentration, the region below the drain region has a medium concentration, and the region in contact with the semiconductor substrate surface and in contact with the medium concentration region has a high concentration. Therefore, when the transistor is turned on, the current flowing into the drain region flows through the medium-concentration region having a lower resistance than the low-concentration region and reaches the high-concentration drain region. A sufficient on-current can be secured without increasing the concentration.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device of the present invention will be described below with reference to FIG.

FIG. 1 is a sectional view showing the construction of the first embodiment of the present invention. In FIG. 1, 1 is an N-type semiconductor substrate, 2
Is a LOCOS region which is an element isolation region, 3 is a gate insulating film of a high breakdown voltage transistor, 4 is a polysilicon gate electrode of a high breakdown voltage transistor, 5 is a sidewall, and 6a is P.
High concentration source region of the mold. 6b is a P-type high-concentration drain region, 7 is a P-type low-concentration drain region, and 8 is a P-type medium-concentration drain region. High-concentration drain region 6b,
The low-concentration drain region 7 and the medium-concentration drain region 8 form a drain region having an offset structure.
Since the drain region forms the offset region, the transistor shown in FIG. 1 can be used as a MIS type high breakdown voltage transistor.

Next, a manufacturing method of the embodiment described with reference to FIG. 1 will be described with reference to FIGS.

2 to 5 are process diagrams of a method of manufacturing a semiconductor device. As shown in FIG. 2, a LOCOS region 2 which is an element isolation region is formed on the N-type semiconductor substrate 1, and a substrate region for mounting a high breakdown voltage transistor is formed. Next, the gate insulating film 3 and the polysilicon gate electrode 4 on the insulating film 3,
It is formed by using the usual photolithography technique and etching technique using the photoresist 9. At this time, the transistor structure is patterned into an open drain structure as shown in FIG. 2 so that the drain region of the high breakdown voltage transistor to be formed later does not contact the LOCOS region 2. Next, as shown in FIG. 3, the photoresist 9 is removed, and the substrate 1 and the polysilicon gate electrode 4 are thinly oxidized to form a thermal oxide film 10. Then acceleration 4
5.0 x 10 to 10.0 x 10 ¹¹ cm ^{-2 at 0 to} 50 keV
B ions are implanted to some extent to form a low concentration drain region 7 on the entire drain region. Next, as shown in FIG.
For example, by using TEOS oxide film deposition and a usual anisotropic dry etching technique, the sidewalls 5 are formed.
To form. After that, for example, acceleration voltage 80 to 100 k
B ion implantation of about 1.0 × 10 ^{12 to} 3.0 × 10 ¹² cm ⁻² was performed at eV, and directly below the low concentration drain region 7 in the source and drain regions and in contact with the low concentration drain region 7. The concentration drain region 8 is formed. Next, as shown in FIG. 5, BF ₂ ions are first implanted into the low-concentration drain region 7 near the surface of the substrate 1 by using a normal photolithography technique using the photoresist 9, and the high-concentration source region 6a and the high-concentration source region 6a are formed. The concentration drain region 6b is formed. After that, the photoresist 9 is removed, and then an interlayer insulating film, a contact window, a metal wiring, a surface protective film, and the like are formed under process conditions that are normally used, to complete a semiconductor device.

Next, another method for forming the low concentration drain region 7 and the medium concentration drain region 8 will be described with reference to FIGS. In the above method, B ions are implanted to form the low-concentration drain region 7. Instead, P ions or As ions of the opposite conductivity type (N type) are used, for example, at 40 to 100 keV and 5.0 ×. 10 ¹¹ ~ 10.0 x 1
Implantation of about 0 ¹¹ cm ^-2 is made to raise the N-type impurity concentration only in the low concentration drain region 7 near the surface of the substrate 1 in advance. Next, as shown in FIG. 4, the sidewall 5 is formed by using, for example, the deposition of the TEOS oxide film and the usual anisotropic dry etching technique. Then, for example, 2.0 × 10 ^{12 to} 5.0 × at an acceleration voltage of 50 to 80 keV.
B ion implantation of about 10 ¹² cm ^-2 is performed to form a medium-concentration drain region 8 in the drain region. At this time, since the N-type impurity concentration has been raised in the vicinity of the entire surface of the drain region in advance, the P-type impurity concentration decreases, and as a result, the low-concentration drain region 7 is formed. However, in the ion implantation performed here, the impurity concentration of the low-concentration drain region 7 and the medium-concentration drain region 8 is 10 ¹⁶ to 10 ¹⁷ / c in the completed semiconductor device, respectively.
The implantation conditions are such that the high-concentration drain region 6b to be formed later penetrates the low-concentration drain region 7 and extends over the middle-concentration drain region 8 so as to have the m ³ order, 10 ¹⁷ to 10 ¹⁸ pieces / cm ³ order. Need to be optimized.

As is apparent from the above embodiments, according to the present invention, the region of the drain region in contact with the insulating film has a low concentration, and the region below it has a medium concentration, is in contact with the surface of the semiconductor substrate and is in contact with the medium concentration region. Since the area is highly concentrated,
When the transistor is turned on, the current flowing into the drain region flows in the medium concentration region where the resistance value is lower than the low concentration region and reaches the high concentration drain region, increasing the impurity concentration in the low concentration region in contact with the gate insulating film. It is possible to secure a sufficient on-current without causing it.

If a photoresist is not used when forming the low concentration drain region 7, impurity ions for forming the low concentration drain region are also formed in the high concentration source region 6a and the high concentration drain region 6b which will be formed later. However, since there is a sufficiently large concentration ratio between the ion concentration injected to form the low concentration drain region and the ion concentration injected to form the high concentration drain region, there is no problem.

[0017]

According to the semiconductor device of the present invention, the region of the upper region of the drain region of the transistor which is in contact with the gate insulating film is the low concentration region and the lower region thereof is the medium concentration region. Is applied to the edge of the high-concentration region, that is, electrical stress increases and breaks away from the gate insulating film. It is possible to prevent the electric charges that are sometimes generated from causing deterioration and destruction of the gate insulating film and causing characteristic deterioration of the high breakdown voltage transistor, and as a result, it is possible to maintain stable high breakdown voltage and its high reliability.

Secondly, when the high breakdown voltage transistor is turned on because the lower layer of the drain region is of medium concentration, the current flowing into the low concentration drain region flows through the medium concentration drain region of the lower layer of low resistance and becomes high. Since it reaches the concentration drain region, a sufficient on-current can be secured without widening the gate width. With the above effects, the present invention can realize a semiconductor device having an excellent MIS type high voltage transistor.

Although the case of the P-channel type high breakdown voltage transistor has been described in the present invention, the same holds true for the N channel type high breakdown voltage transistor by changing the impurity type of each region.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process diagram of a manufacturing method according to an embodiment of the present invention.

FIG. 3 is a process diagram of a manufacturing method according to an embodiment of the present invention.

FIG. 4 is a process chart of a manufacturing method according to an embodiment of the present invention.

FIG. 5 is a process diagram of a manufacturing method according to an embodiment of the present invention.

FIG. 6 is a sectional view showing the configuration of a conventional semiconductor device.

[Explanation of symbols]

 1 substrate 2 LOCOS region 3 gate insulating film 4 polysilicon gate electrode 5 sidewall 6a high concentration source region 6b high concentration drain region 7 low concentration drain region 8 medium concentration drain region 9 photoresist 10 thermal oxide film

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a source region and a drain region of a second conductivity type provided on the surface of the semiconductor substrate at a distance from each other, and the semiconductor substrate sandwiched between the source region and the drain region. A transistor having a gate electrode provided on the surface via a gate insulating film, wherein the drain region is a low concentration region, a medium concentration region,
And a part of a region of the drain region which is in contact with the gate insulating film and a part of the drain region which is in contact with the semiconductor substrate surface is a low concentration region which is in contact with the low concentration region and in contact with the semiconductor substrate surface. A semiconductor device, wherein the remaining region is a high-concentration region, and the regions immediately below the low-concentration region and the high-concentration region are medium-concentration regions.