JPH05235350A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which both n-type and p-type MOSFETs, easily adjustable in threshold, are formed in a semiconductor wafer of good quality that is easily manufactured. CONSTITUTION:A semiconductor device comprises p-type and n-type MOSFETs formed in a semiconductor layer 4 on an insulating layer 3. Both p-type and n-type MOSFETs have channel regions of the same conductivity type at impurity concentration of more than 1X10<13>/cm<3>. The semiconductor layer 4 has a thickness equal to or less than the depth of the depletion layer that extends from the surface of the semiconductor layer 4 when no gate voltage is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device formed by forming a MOS field effect transistor in a semiconductor layer on an insulating layer.

Recent improvements in the performance of semiconductor devices are largely due to improvements in the performance of individual transistors due to the miniaturization of transistors. One of the high-performance transistors that has recently attracted attention is SOI (semiconductor o).
n insulator) is a thin film MOSFET formed on a substrate.

[0003]

2. Description of the Related Art As a substrate for forming a semiconductor device, an SOI substrate formed by a bonding method, SIMOX or the like has been proposed. FIG. 4A shows a general sectional structure in which a complementary MOS field effect transistor (CMOSFET) is formed on the element forming semiconductor layer of the SOI substrate.
In the figure, the interlayer insulating film, the wiring layer and the like are omitted.

The nMOSFET is on the left side of FIG. 4 (a).
As shown, it is formed on the insulating film 41 of the SOI substrate 40.
On the device forming semiconductor layer 42 with the insulating film 43 interposed.
Of the LDD structure on both sides thereof.
Forming n-type source / drain layers 45s and 45d
And the channel region C below the gate electrode 44₁Is p ^-
It is a type.

Further, as shown in the right side of FIG. 4A, the pMOSFET has a device forming semiconductor layer 46 on the insulating film layer 41.
A gate electrode 48 formed on top of the insulating film 47
And p ⁺ type source / drain layers 49s and 49d formed on the element forming semiconductor layer 46 on both sides thereof, and the channel region C ₂ thereof is n ⁻ type.

According to such a structure, the nMOSFET
The threshold voltages Vth of the pMOSFET and the pMOSFET are matched with each other by using a CMOSF formed on a normal bulk semiconductor substrate.
Similar to ET, it is performed by ion-implanting impurities.

However, nMOSFET and pMOSFET
Of the element forming semiconductor layers 42 and 47 of the channel regions C ₁ and C
_It takes time and labor to form a mask for implanting ions into the _second layer, and since the element forming semiconductor layers 42 and 47 are thin, the impurity concentration distribution due to diffusion fluctuates depending on the thickness.

In order to avoid such a problem, the applicant of the present invention has proposed a MOSFET having a structure shown in FIG. 4 (b) in Japanese Patent Application No. 2-306844. This device includes an nMOSFET and a pM formed on an SOI substrate 50.
The channel regions C ₁ and C ₂ of both the element forming semiconductor layers 52 and 56 of the OSFET are intrinsic semiconductors or an extremely low impurity concentration close to it (for example, 1 × 10 ¹³ / cm ³ or less).

In the figure, reference numeral 51 is an insulating film layer below the element forming semiconductor layers 52 and 56, 53 and 57 are gate insulating films, 54 and 58 are gate electrodes, 55s and 59s are source layers, and 55d and 59d. Indicates the drain layer.

In this case, the gate electrode 5 of the nMOSFET
When 4 is an n-type, the drain current / gate voltage characteristic becomes a depletion type due to the work function difference, so the conductivity type is made a p-type to form an enhancement type transistor. The pMOSFET 58 uses an n-type gate electrode because the polarity of the gate voltage is opposite.

As a result, the element forming semiconductor layers 52 and 57 are formed.
It is not necessary to introduce impurities into the channel region of. In addition,
Impurity introduction into the gate electrode 54 of the nMOSFET is pM
It suffices to carry out at the same time when the source / drain layers 55s and 55d of the OSFET are formed, and the gate electrode 58 of the pMOSFET is the source / drain layer 5 of the nMOSFET.
Since it may be performed when forming 9s and 59d, there is no particular problem.

[0012]

However, according to the device of this structure, the impurity concentration of the element forming semiconductor layers 42 and 47 is lowered as it becomes closer to the true value, so that a high-quality wafer with few crystal defects can be manufactured. This is difficult, and when an SOI substrate having the element forming semiconductor layers 42 and 47 formed from this wafer is used, the yield is poor and mass productivity cannot be expected.

The present invention has been made in view of the above problems, and an nMOS in which a device forming semiconductor layer is formed from a wafer of good quality and easy to manufacture, and the threshold value can be easily adjusted.
An object of the present invention is to provide a semiconductor device capable of coexisting an FET and a pMOSFET.

[0014]

[Means for Solving the Problems]
As illustrated in (i), in the semiconductor device configured by coexisting a p-type MOS field effect transistor and an n-type MOS field effect transistor in the element forming semiconductor layer 4 on the insulating layer 3, the element forming semiconductor layer 4, of the p-type M
The impurity concentration of the channel regions of both the OS field effect transistor and the n-type MOS field effect transistor is 1 × 1.
The element forming semiconductor layer 4 has a thickness of 0 ¹³ / cm ³ or more and has the same conductivity type, and the thickness of the element forming semiconductor layer 4 is a depletion spreading from the surface of the element forming semiconductor layer 4 without applying a gate voltage. This is achieved by a semiconductor device characterized in that it is formed to be equal to or less than the depth of the layer.

Alternatively, the gate electrode G ₁ of the n-type MOS field effect transistor is formed of a p-type impurity-containing semiconductor, while the gate electrode G ₂ of the p-type MOS field-effect transistor is formed of an n-type impurity-containing semiconductor. It is achieved by a semiconductor device characterized in that

[0016]

[Operation] According to the present invention, a pMOSFET and an nMOSF formed on the element forming semiconductor layer 4 on the insulating layer 3 are formed.
Both the channel regions of ET have the same conductivity type, the impurity concentration thereof is 1 × 10 ¹³ / cm ³ or more, and the thickness of the element forming semiconductor layer 4 is the same as the depth of the depletion layer extending from the surface thereof. Or it is smaller than that.

For this purpose, pMOSFET and nMOSF
The element-forming semiconductor layer 4 in the channel region of ET is completely depleted to a depth reaching the insulating film 3 thereunder when a gate voltage is not applied, and the influence of the conductivity type of impurities disappears, and normal transistor operation does not occur. You can do it.

Therefore, the semiconductor layer 4 for element formation can be formed from a wafer having a general impurity concentration, and it becomes possible to manufacture a high-performance device with good crystal quality and good mass productivity.

The gate electrode G _{1 of the} pMOSFET is formed of an n-type impurity-containing semiconductor, while the nMOSFE is formed.
Since the gate electrode G _{2 of} T is formed of a p-type impurity-containing semiconductor, its MO
The SFET becomes an enhancement type without implanting impurities in the channel region. Therefore, the process is also simplified.

[0020]

1 to 3 are cross-sectional views showing a manufacturing process of an embodiment device of the present invention, and FIG. 3 (i) shows an embodiment device of the present invention formed through the process. Is.

In the figure, reference numeral 1 is a bonding method, SIM.
The SOI substrate 1 is made of OX or the like, and the SOI substrate 1 includes a support layer 2 made of silicon, a buried insulating layer 3 made of SiO ₂ , and n ⁻ made of single crystal silicon having a film thickness of 200 to 5000 Å, for example. The element-forming semiconductor layer 4 of which is 1 × 10
It is formed to contain phosphorus at a low concentration of about ¹³ to 1 × 10 ¹⁷ / cm ³ .

Therefore, first, as shown in FIG. 1A, a photoresist is applied, exposed and developed to form an nMOS.
After forming the resist mask 5 covering the formation region X and the pMOS formation region Y, the element formation semiconductor layer 4 in the region exposed from the resist mask 5 is removed by etching by a reactive ion etching (RIE) method using a chlorine-based gas. The element forming semiconductor layer 4 is left in the nMOS forming region X and the pMOS forming region Y in an island shape (FIG. 1B).

Next, after removing the resist mask 5,
The island-shaped element forming semiconductor layer 4 is thermally oxidized to form 10
After forming the SiO ₂ insulating film 6 of 0 to 200Å, for example, C
The non-doped polycrystalline silicon film 7 is made to 2000 by the VD method.
Å About Å growth, the surface is thermally oxidized 100 ~ 200 Å
The SiO ₂ film 8 having the film thickness is formed (FIG. 1 (c)). Examples of the reaction gas include SiH ₄ and Si ₂ H ₆ .

After this, as shown in FIG. 2 (d), pMO
A resist mask 9 covering the S formation region Y is formed, and boron is ion-implanted into the exposed polycrystalline silicon film 7 in the nMOS formation region X to make it p-type. The conditions for ion implantation in this case are, for example, a dose of 1 × 10 ¹⁵ to 1 × 10 5.
¹⁶ / cm ² and acceleration energy of 30 keV.

Further, after removing the resist mask 9, this time, as shown in FIG. 2 (e), the nMOS formation region X is formed.
A resist mask 10 is formed to cover the pMOS formation region Y, and phosphorus or arsenic is ion-implanted into the pMOS formation region Y to make the polycrystalline silicon film 7 in that region n-type. Ion implantation in this case is performed under the same conditions as the p-type impurities in the previous step.

Then, after removing the resist mask 10, a photoresist is applied again, and the photoresist is exposed and developed to form a resist mask 11 covering each gate region of the nMOS formation region X and the pMOS formation region Y. The SiO ₂ film and the n-type and p-type polycrystalline silicon film 7 exposed from the resist mask 11 are removed by the RIE method as shown in FIG. 2 (f). Subsequently, the resist mask 11 is removed.

As a result, the pMOS formation region Y and the nMO are formed.
The polycrystalline silicon films 7 remaining in the S formation region X are used as gate electrodes G ₁ and G ₂ , respectively. Next, as shown in FIG. 3G, a resist mask 12 is formed and a pMOS formation region Y is formed.
And the n ^-- type semiconductor layer 4 on both sides of the gate electrode G ₁ after covering the gate electrode G ₁ of the nMOS formation region X.
Then, for example, phosphorus is ion-implanted at a dose of 1 × 10 ¹³ / cm ² to form an n ⁻ type layer 4n.

After this, the SiO ₂ film 1 is entirely formed by the CVD method.
3 is formed to a thickness of 1000 to 2000Å, and this is RI
Anisotropic etching is performed in the vertical direction by the E method, and the Si
The O ₂ film 13 is left only on the sides of the gate electrodes G ₁ and G ₂ (FIG. 3 (h)).

Subsequently, the gate electrode G ₂ in the pMOS formation region Y and the nMOS formation region X are covered with a resist mask (not shown), and boron is added at 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm 3.
Ion implantation is performed at a dose of ² to form a pMOSFET source layer 4ps and a drain layer 4p as shown on the right side of FIG. 3 (i).
to form d.

Further, by replacing the resist mask, n
Gate electrode G of MOS formation region X₁And pMOS formation area
Y and Y are covered with a resist (not shown),
Pole G ₁On both sides of^-Arsenic 1 × 10 in the mold layer 4n¹⁵~
1 x 10¹⁶/cm²Ion implantation with a dose of
Nns source layer 4ns as shown on the left side of
The drain layer 4nd is formed. Those source layers 4ns
And the drain layer 4nd are the gate electrode G₁Near n^-Type
The LDD structure is formed by including the layer 4n.

Then, after that, an interlayer insulating film is formed, activation heat treatment, aluminum wiring, etc. are performed to complete the transistor. The impurities ion-implanted into the element-forming semiconductor layer 4 and the polycrystalline silicon film 7 are activated by the film-forming temperature after implantation or an independent heat treatment.

Next, the nMO formed through the above steps
The operation of the SFET and pMOSFET will be described. Due to the work function difference between the channel region of the nMOSFET and the gate electrode, the depletion layer spreads from the surface of the nMOSFET even when the gate is at zero bias, and its depth has the following relationship.

[Depletion layer depth] ∝ [impurity concentration] ^-1/2 For example, in the case of 1 × 10 ¹⁴ / cm ³ , the depth is 1 μm, and in the case of 1 × 10 ¹⁶ / cm ³ . Has a depth of 0.1 μm.

The impurity concentration of the channel regions of the nMOSFET and pMOSFET formed in the element forming semiconductor layer 4 is 1 × 10 ¹³ to 1 × 10 ¹⁷ / cm ³ , and the depletion layer generated from the surface of the channel region is formed. Depth is
Since it is about 3 to 0.03 μm, the element forming semiconductor layer 4
If the thickness of P is adjusted to that, the channel region is completely depleted.

The gate electrode of the nMOSFET has p
Type impurities and n-type impurities are introduced into the gate electrode of the pMOSFET, the MOSFETs are enhancement type due to the work function difference.
There is no need to adjust the threshold voltage. Therefore, it is not necessary to separately implant the impurity ions in the channel region, and the process is simplified.

Therefore, if the element forming semiconductor layer 4 is formed from the one having an impurity concentration of about 1 × 10 ¹⁵ / cm ³ which is usually used as a wafer and the thickness thereof is set to 0.3 μm or less, the crystal quality is improved. In addition, mass production is possible, and high-performance devices can be manufactured at low cost.

When the impurities are implanted into the gate electrodes G ₁ and G ₂ , they may be independently implanted as shown in FIGS. 2 (d) and 2 (e). Layer 4nd,
If impurities are ion-implanted into 4 pd, if the mask pattern is changed and the impurities are simultaneously implanted, the process is simplified.

In the above embodiment, pMOSFE is used.
Although the impurity of the element forming semiconductor layer 4 to be the channel region of the T and nMOSFET is n ^-- type in which phosphorus or arsenic is introduced, the channel region is depleted even if it is p ^-- type using boron or the like. Become. In this case, the nMOSFET has a lateral n ⁺ -p-n ⁺ structure, and the pMOSFET has p
^{A +} -p-p ⁺ structure is formed, and the p-type impurity concentration in that region and the thickness of the element forming semiconductor layer are determined under the same conditions as above.

Further, the control of the threshold voltage is performed by nMOSFE.
This is achieved by making the gate electrodes of the T and pMOSFETs have different conductivity types.
Alternatively, the impurity may be ion-implanted into one of the channel regions of the pMOSFET to make the concentration different and fine adjustment is performed. The channel regions thus formed have the same conductivity type.

Further, the impurity concentration is not limited to the above-mentioned numbers, and may be 10 ¹³ / cm ³ or more, and the thickness of the semiconductor layer for element formation is determined according to the depth of the depletion layer determined by this. Just decide.

[0041]

As described above, according to the present invention, the pMOSF formed on the element forming semiconductor layer on the insulating layer.
The channel regions of both ET and nMOSFET have the same conductivity type, and the impurity concentration thereof is 1 × 10 ¹³ / cm ³
In addition, since the thickness of the element formation layer is made equal to or smaller than the depth of the depletion layer spreading from the surface thereof, the impurity concentration of the wafer used as the element formation semiconductor layer is set to a general value. The same can be done, the crystallinity of the element forming semiconductor layer is improved, and a high-performance device capable of mass production can be manufactured.

Further, since the gate electrode of the pMOSFET is formed of the n-type impurity-containing semiconductor and the gate electrode of the nMOSFET is formed of the p-type impurity-containing semiconductor, the MOSFETs are
It is possible to make an enhancement type without separately implanting impurities in the channel region. Therefore, the process can be simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view (1) showing a manufacturing process of a device according to an embodiment of the present invention.

FIG. 2 is a sectional view (No. 2) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 3 is a sectional view (3) showing the manufacturing process of the device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an example of a conventional device.

[Explanation of symbols]

1 SOI Substrate 2 Support Layer 3 Buried Insulation Layer 4 Element Forming Semiconductor Layer 5, 9, 10, 11, 12 Resist Mask 6 Insulation Film 7 Polycrystalline Silicon Film (Semiconductor Film) 8, 13 SiO ₂ Film G ₁ , G ₂ Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/12 Z 8728-4M

Claims (2)

[Claims] 1. A device forming semiconductor layer (4) on an insulating layer (3).
In a semiconductor device configured by coexisting a p-type MOS field effect transistor and an n-type MOS field effect transistor, in the element forming semiconductor layer (4), the p-type MOS field effect transistor and the n-type MOS field effect transistor are included. Both channel regions of the effect transistor have an impurity concentration of 1 × 10 ¹³ /
The element-forming semiconductor layer (4) has the same conductivity type by containing impurities of cm ³ or more, and the thickness of the element-forming semiconductor layer (4) spreads from the surface of the element-forming semiconductor layer (4) without applying a gate voltage. A semiconductor device, wherein the semiconductor device is formed to be equal to or less than the depth of the depletion layer. 2. The gate electrode (G ₁ ) of the n-type MOS field effect transistor is formed of a semiconductor containing p-type impurities, while the gate electrode (G ₂ ) of the p-type MOS field effect transistor contains n-type impurities. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a semiconductor.