JPH0472770A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lessen a chip in area and to enable a transistor which is made to operate with a power supply of high voltage to be formed by a method wherein a groove is provided to an insulating substrate, silicon ions are implanted into the surface of the groove, a silicon crystal layer is formed inside the groove through a selective epitaxial growth method, and a single transistor is provided onto the silicon crystal layer concerned. CONSTITUTION:Grooves 5 are provided to an insulating substrate 1, silicon ions are implanted into the surface of the grooves 5, a silicon crystal layer 7 is formed in the grooves 5 through a selective epitaxial growth method respectively, and a transistor 11 composed of a gate oxide film 8, a gate electrode 9, a drain region 10, and a source region 10 is provided onto the silicon crystal layers respectively. Therefore, as the transistors 11 are isolated by insulation through the insulating substrate 1, parasitic capacitance between the transistors 11 can be lessened and the transistors can be enhanced in insulation resistance. Furthermore, a field oxide 19 used in a conventional one can be dispensed with, and the width of a field region 16' can be reduced to the irreducible minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device.

[Conventional technology]

FIGS. 2A to 2C are process-order cross-sectional views showing an N-channel type MO3) run lister to which a conventional semiconductor device manufacturing method is applied.

As shown in FIG. 2(a), a protective oxide film 13 with a thickness of approximately 300 mm and a protective oxide film 13 with a thickness of approximately 950 mm are formed on a P-type silicon substrate 12.
After silicon nitride H(S 1N) 14 is sequentially formed, the silicon nitride film 14 in the field region 16 is removed by etching using a resist pattern 15 formed on the silicon nitride film 14. . After that, using the silicon nitride film 14 and the resist pattern 15 as a mask, a dose of approximately 3×101 cm (cm-”) is applied.
By ion-implanting boron 17, a P-type channel stopper region 18 is formed.

The acceleration energy of this boron-17 ion implantation is approximately 50
(k e V).

Next, as shown in FIG. 2(b), the resist pattern 15 is
After removing the field oxide film 19, a selective oxidation method is used to form a field oxide film 19.
is formed. 20 is a transistor formation region.

Next, as shown in FIG. 2C, after the silicon nitride film 14 in the transistor formation region 20 is removed, a gate oxide film 8 is formed, and a gate electrode made of a polysilicon film is formed on this gate oxide film 8. 9 is formed. Thereafter, n-type impurity ions are implanted using gate oxide film 8 and gate electrode 9 as masks, thereby forming source/drain regions 10.

[Problems to be Solved by the Invention] However, in the N-channel type MO3) run lister to which such a conventional semiconductor device manufacturing method is applied, the junction breakdown voltage ( Junction breakdown voltage) is low. That is, the insulation between the transistors 20 was insufficient. Therefore, a high voltage power supply (for example, 5 [V) power supply. ), it is not possible to form a transistor that operates with

Therefore, in such a case, the impurity concentration of the source/drain region 10 near the contact with the channel stopper region 18 is made low, and the vicinity of the junction is made high resistance, thereby reducing the junction between the source/drain region 10 and the channel stopper region 18. The junction breakdown voltage in the vicinity was improved. However, when such a method is applied, there is a problem in that the width of the field slope 16 becomes large and the chip area increases.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce the chip area and form a transistor that operates using a high voltage power supply.

[Means to solve the problem]

The method for manufacturing a semiconductor device according to the present invention is as follows.

A trench is formed in the transistor formation region by selectively etching the insulating substrate, silicon ions are implanted into the surface of the trench, and then a silicon crystal layer is formed inside the trench by selective epitaxial growth. Form a single transistor on the layer.

[Effect]

According to the structure of the present invention, a groove is formed in an insulating substrate, silicon ions are implanted into the surface of the groove, and then a silicon crystal layer is formed inside the groove by selective epitaxial growth, and a silicon crystal layer is formed on the silicon crystal layer. By forming a single transistor, each transistor is insulated and separated by an insulating substrate, so the parasitic capacitance between each transistor can be made extremely small, and the insulation resistance can be increased. Furthermore, the conventional field oxide film is not required, and the width of the field oxide film can be minimized.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 1(aJ to 1C).

FIGS. 1A to 1C are process-order cross-sectional views showing an N-channel MOs transistor to which a method of manufacturing a semiconductor device according to an embodiment of the present invention is applied.

As shown in FIG. 1(a), for example, sapphire (Af
fi□0. ) etc., a resist pattern 2 is formed on an insulating substrate 1 such as
After forming the resist pattern 2, the insulating substrate 1 is etched using the resist pattern 2, thereby forming a groove 5 with a depth of about 1 [μm] in the transistor formation region 4. Then, using the resist pattern 2 as a mask, ions of silicon and boron 6 as an impurity are implanted into the surface of the groove 5.

Next, as shown in FIG. 1(b)A, the resist pattern 4 is
After removing , an island-shaped P-type silicon crystal layer 7 is formed inside the substrate 5 by selective epitaxial growth.

Then, as shown in FIG. 1(C), a silicon crystal layer 7
forming gate oxide 1118 and gate electrode 9 on top;
Source/drain regions 10 are formed by ion-implanting n-type impurities using gate oxide film 8 and gate electrode 9 as masks.

After forming the groove 5 in the insulating substrate 1 in this way and implanting silicon-containing ions into the surface of the groove 5, a silicon crystal layer 7 is formed inside the groove 5 by selective epitaxial growth. On layer 7, gate oxide H
8. A transistor 11 consisting of a gate electrode 9 and a drain/source region 10 is formed. Therefore, since each transistor 11 is insulated and isolated by the insulating substrate 1, the parasitic capacitance between each transistor 11 can be reduced, and the insulation resistance can be increased. Even more conventional field oxidation! 19 is no longer necessary, and field area 1
The width of 6' can be the minimum width. As a result, the chip area can be reduced and the transistor 11 operated by a high voltage power supply can be formed.

In the embodiment, a case has been described in which the present invention is applicable to an N-channel type MO3) run lister, but it can also be applied to a P-channel type MOS transistor and a CuO2) run lister.

〔Effect of the invention〕

According to the method of manufacturing a semiconductor device of the present invention, a groove is formed in an insulating substrate, silicon ions are implanted into the surface of the groove, and then a silicon crystal layer is formed inside the groove by selective epitaxial growth. By forming a single transistor on a crystal layer, each transistor is insulated and separated by an insulating substrate, so that the parasitic capacitance between each transistor can be extremely reduced, and the insulation resistance can be increased. Furthermore, a conventional field oxide film is not required, and the width of the field region can be minimized. As a result, the chip area can be reduced, and a transistor that operates using a high voltage power supply can be formed.

[Brief explanation of drawings]

1(a) to 1(C) are step-by-step cross-sectional views showing an N-channel MOS transistor to which a method of manufacturing a semiconductor device according to an embodiment of the present invention is applied, and FIG. 2(a) to 2(C) are sectional views of a conventional N-channel MO using the semiconductor device manufacturing method
3) It is a process order sectional view showing a run disc. l...Insulator substrate, 4...Transistor formation region,
5...Groove, 6...Silicon, 7...Silicon crystal layer, 11...Transistor...8F! Sewing board No. 2 Figure 11...Transistor (b) △ 2゜

Claims (1)

[Claims] A step of forming a groove in a transistor formation region by selectively etching an insulating substrate, a step of implanting silicon ions into the surface of this groove, and forming a silicon crystal layer inside the groove by selective epitaxial growth. and forming a single transistor on the silicon crystal layer.