JP3348517B2 - Method for manufacturing thin film field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film field effect transistor (thin film FET) capable of preventing a variation in threshold voltage Vth and a reduction in drain withstand voltage.

[0002]

2. Description of the Related Art During operation of a field effect transistor (FET), carriers injected from a source region into a channel region collide with a crystal lattice in a high electric field region generated at a drain end, and electron-hole pairs are generated. . In the case of an FET formed on a bulk semiconductor substrate, even if any one of these minority carriers flows into the channel region, it does not pose a particular problem because it eventually leaks as a substrate current.

In recent years, instead of conventional bulk semiconductor substrates,
2. Description of the Related Art An FET is formed on an SOI (silicon on insulator) substrate. this is,
This is a method of forming an FET on a silicon thin film on an insulating substrate, and has advantages in speeding up operation by reducing junction capacitance and facilitating isolation between elements. However, the thin-film FET formed on the SOI substrate is in a floating state in which the periphery of the silicon thin film is surrounded by the insulating substrate, so that minority carriers generated by impact ionization cannot leak to the substrate side. For this reason, the minority carriers are accumulated in the channel region to change the potential, and the threshold voltage Vth
And the drain breakdown voltage is reduced.

This phenomenon is particularly remarkable in NMOS.
FIG. 8 shows the energy of a conventional thin film FET (NMOS).
The band diagram is shown. E _v is the upper end of the valence band, E _c is the energy level representing respectively the lower end of the conduction band, the minority carriers in this case is a Hall H. Since a positive voltage is applied to the n-type drain region, between the channel region and the drain region, the pseudo-Fermi levels E _f2 , E _f
A reverse bias b _cd corresponding to the energy difference between _f3 is applied.

On the other hand, between the source region and the channel region, the accumulation of holes causes the pseudo-Fermi levels E _f1 ,
A forward bias b _sc corresponding to the energy difference between E _f2 is applied. That is, part H ₁ of holes generated in the drain region by impact ionization, electrons injected from the source region e ^- and recombine and disappear, but other hole H ₂ is the diffusion current diffuses to the source region Is generated. However, holes are accumulated near the source region in the channel region, and the potential of the channel region increases because the charge disappearance rate due to diffusion is generally slow and the diffusion current cannot leak to the substrate. is there. This potential rise stops when the number of generated holes and the number of holes that disappear or flow out are balanced (steady state), whereby the threshold voltage V _th of the FET is reduced.
Changes.

As a thin film FET for solving this problem, Japanese Patent Application Laid-Open No. Hei 4-313242 discloses that a source region made of a silicon thin film is ion-implanted with germanium (Ge), and the bandgap of the source region is reduced. A thin film FET is disclosed in which the gap is made narrower than that of the channel region to promote the outflow of holes from the channel region to the source region.

[0007] Energy band diagram of the thin film FET is what is shown in Figure 9, the band gap BG _s of the source region is smaller than the band gap BG _ch of the channel region. Accordingly, the energy barrier h ₁ is lowered for holes H ₂ injected from the channel region to the source region, the outflow hole of H ₂ to the source region is promoted.

[0008]

In the above-described thin film FET, the control of the Ge diffusion profile has a great effect on the actual device characteristics. Where Ge
Is doped into the silicon thin film in a self-aligned manner by ion implantation using the patterned gate electrode as a mask, but then slightly diffuses into the channel region immediately below the gate electrode when undergoing heat treatment to recover crystal defects. I do.
Then, as illustrated, the band gap in the channel region near the source region also decreases, decreases from resulting in the source region to the barrier h ₂ for electrons injected into the channel region. For this reason, there has been a problem that the efficiency of injecting electrons into the channel region is increased due to the above-described potential increase, and the fluctuation of the threshold voltage _Vth and the deterioration of the drain withstand voltage are promoted.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a thin film FET in which the diffusion profile of Ge can be controlled to effectively promote the flow of minority carriers into the source region.

[0010]

SUMMARY OF THE INVENTION The present invention is proposed to achieve the above-mentioned object. That is, the method of manufacturing a thin-film FET of the present invention comprises the steps of: ion-implanting germanium into the silicon thin film using the gate electrode formed on the silicon thin film via the gate insulating film as a mask;
Forming a sidewall on the side wall surface of the gate electrode; and ion-implanting germanium into the silicon thin film using both the gate electrode and the sidewall as a mask.

As the above-mentioned sidewalls, those generally formed in the process of manufacturing a MOS-FET having an LDD structure can be used as they are.

A thin-film FET manufactured by such a manufacturing method is formed on a semiconductor thin film on an insulating substrate, and the forbidden band width of the source region is reduced in two steps as the distance from the channel region increases. is there.

Here, the source region of the FET generally has a symmetrical positional relationship with the drain region with the gate electrode interposed therebetween.
Both regions are formed simultaneously by ion implantation using the gate electrode as a mask in the manufacturing process. Therefore,
In the thin-film FET manufactured by this manufacturing method, the band gap of the drain region is similarly reduced in two steps as the distance from the channel region increases.

Here, it is particularly preferable that the maximum width of the forbidden band of the source region is smaller than or equal to the forbidden band of the channel region. In this thin film FET, by using a silicon thin film for the semiconductor thin film and a silicon thin film containing germanium for the source region, a practical thin film FET with good lattice constant matching can be obtained.

[0015]

According to the method of manufacturing a thin film FET of the present invention, a first Ge ion implantation using the gate electrode as a mask and a second Ge ion implantation using both the gate electrode and the sidewall formed on the side wall surface as a mask. By performing Ge ion implantation, a region immediately below the gate electrode into which Ge is not introduced (channel region), a region immediately below the sidewall where Ge is introduced only during the first ion implantation (low-concentration source region), and two times Ge-doped regions (high-concentration source regions) can be formed in a self-aligned manner by ion implantation.

In the thin-film FET manufactured by such a manufacturing method, the band gap of the source region is reduced in two steps as the distance from the channel region is increased. Thereby, the mobility of minority carriers in the source region is increased. This effect is expected even if the maximum width of the forbidden band in the source region is the same as the forbidden band in the channel region.
In other words, the thin film FE manufactured by this manufacturing method
In T, the maximum width of the forbidden band in the source region is not particularly reduced, and therefore, even if the energy barrier in this portion is not different from that of the conventional thin film FET, the outflow of minority carriers can be smoothed. This means that, for example, when the band gap is controlled by doping Ge into the silicon thin film, it is not necessary to increase the Ge concentration at the end of the source region so much. Therefore, in the manufacturing method, the diffusion of Ge from the source region to the channel region can be extremely suppressed, and there is no concern that the energy barrier for electrons between the source and the channel is reduced as described above. As a result,
The effect of preventing fluctuation of the threshold voltage _Vth and deterioration of the drain withstand voltage can be obtained.

Of course, if the maximum width of the forbidden band of the source region is set smaller than the forbidden band of the channel region, the injection of minority carriers into the source region itself will increase.
The above-described prevention effect is further improved.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described.

First, a thin film NMOS-FET manufactured by the manufacturing method of the present invention will be described with reference to the energy band diagram of FIG. E _v is the upper end of the valence band, the E _c is the energy level representing respectively the lower end of the conduction band, the minority carriers in this case is a Hall H _2.
Since a positive voltage is applied to the n-type drain region, a reverse bias b _cd corresponding to the energy difference between the pseudo-Fermi levels E _f2 and E _f3 is applied between the channel region and the drain region. I have. On the other hand, a forward bias _bsc corresponding to the energy difference between the pseudo-Fermi levels E _f1 and E _f2 is applied between the source region and the channel region due to the accumulation of holes.

[0020] In this case, the forbidden band width BG _s of the source region,
It is largest at the junction region with the channel region, and is reduced as the distance from the channel region increases. Also,
The maximum width of the forbidden band in the junction region is approximately equal to or slightly smaller forbidden band width BG _ch of the channel region. That is, the band gap of this portion is not extremely different from the band gap of the source region of the conventional thin film NMOS-FET without Ge doping.

Thin-film NMOS-F having such a band structure
In ET, the mobility of minority carriers in the source region increases due to the contribution of the drift electric field formed by the potential gradient. Further, since the maximum width of the forbidden band of the source region is slightly smaller than the band gap BG _ch of the channel region, injecting themselves hole of H ₂ to the source region is also promoted. Furthermore, the energy barrier for electrons between the source and the channel has not been reduced. Therefore, fluctuation of the threshold voltage Vth and deterioration of the withstand voltage between the source and the drain due to the accumulation of holes in the channel region do not occur.

Although the embodiment has been described with reference to the NMOS-FET, the same effect can be obtained for the PMOS-FET.

Embodiment 1 In this embodiment, the above-described NMOS-FET is replaced with an LDD.
A method of manufacturing by applying the process will be described with reference to FIGS. First, as shown in FIG. 2, the surface layer of the SiO _x substrate is formed into an island shape with a thickness of about 0.1 μm.
An SOI substrate having the polysilicon thin film 2 was prepared.
This polysilicon thin film 2 is doped with boron (B) in order to control the threshold voltage _Vth . Subsequently, a gate electrode 4 is formed facing the polysilicon thin film 2 by growing a gate insulating film 3 on the entire surface of the substrate and patterning the polysilicon layer deposited on the entire surface.

Here, the SOI substrate is bonded by a bonding method or a SIMOX method (Separation by I
planted Oxygen). In this state, self-aligned first ion implantation of Ge was performed using the gate electrode 4 as a mask. The dose was 1 × 10 ¹⁵ to 10 ¹⁶ / cm ² . In the figure, ×
The mark represents the region where Ge has been introduced.

Next, as shown in FIG. 3, a first ion implantation of phosphorus (P) was performed using the gate electrode 4 as a mask. The dose amount is, for example, 2 × 10 ^{15 /} cm
^{And 2} . As a result, the conductivity type of the region not masked by the gate electrode 4 becomes n-type. Further, the substrate was annealed at 800 ° C. to recover crystal defects generated in the polysilicon thin film 2 by the first ion implantation of Ge and P, and to activate the impurity (P). As a result of this annealing, as shown in FIG. 4, the n-type source region 2s and the drain region 2
d is formed, and the channel region 2 is formed immediately below the gate electrode 4.
c was formed.

Next, a SiOx (not shown) is formed on the entire surface of the substrate.
After depositing the film, the film was etched back by RIE (Reactive Ion Etching) to form a side wall 5 on the side wall surface of the gate electrode 4 as shown in FIG. Subsequently, a second ion implantation of Ge was performed at the same dose as before. In this ion implantation, the gate electrode 4
Ge was introduced only in a region that was not masked either by the side walls 5. Therefore, the concentration distribution of Ge in the horizontal direction is a region immediately below the side wall 5 that receives only the first ion implantation with the channel region 2c not receiving any of the first and second ion implantations interposed therebetween, and furthermore, both ion implantations are performed. To the area that receives it. Since the band gap of the polysilicon thin film decreases as the content of Ge increases, the energy band diagram of this NMOS-FET has a slope of the upper end EV of the valence band in the source region as shown in FIG. However, as the distance from the channel region increases, the forbidden bandwidth becomes smaller.

Thereafter, as shown in FIG. 6, a second ion implantation of P was performed with the same dose as before. Further, the substrate was annealed to recover crystal defects and activate impurities, thereby completing an NMOS-FET having an LDD structure as shown in FIG. In this embodiment, since the sidewall used in a general LDD process is also used as a mask for Ge ion implantation,
A gradient of the Ge content also occurs on the drain region 2d side. That is, the energy band diagram of the NMOS-FET of this embodiment has a pattern in which the upper end of the valence band in the drain region in FIG. 1 is similarly inclined, and the forbidden band width decreases as the distance from the channel region increases. However, since the original object of the present invention can be achieved by giving a gradient to the Ge content only on the source region 2s side, for example, a region from the gate electrode 4 to the drain region 2d is masked with a resist pattern, and Only Ge ion implantation may be performed in two stages.

[0028]

As is clear from the above description, the present invention can be manufactured by directly applying the LDD process for manufacturing the low concentration impurity region, and therefore has good compatibility with the conventional process. It is also very economical. The improvement of the energy band structure of the source region promotes the flow of minority carriers to the source region, and the variation of the threshold voltage _Vth even on a substrate such as an SOI substrate where the substrate current cannot be leaked. And a thin-film FET that can prevent deterioration of the source-drain breakdown voltage can be manufactured.

[Brief description of the drawings]

FIG. 1 is an energy band diagram of a thin-film FET manufactured by a manufacturing method to which the present invention is applied.

FIG. 2 is a schematic diagram showing a state in which Ge + ions are implanted using a gate electrode formed on a silicon thin film on an insulating substrate via a gate oxide film as a mask in the method of manufacturing a thin film FET of the present invention. It is sectional drawing.

FIG. 3 is a schematic cross-sectional view showing a state in which P ion implantation is continuously performed.

FIG. 4 is a schematic sectional view showing a state where the wafer of FIG. 3 is annealed.

5 is a schematic cross-sectional view showing a state in which sidewalls are formed on the side wall surface of the gate electrode in FIG. 4 and Ge ions are implanted using these as masks.

FIG. 6 is a schematic cross-sectional view showing a state in which P ion implantation is continuously performed.

FIG. 7 is a schematic sectional view showing a state where the wafer of FIG. 6 is annealed.

FIG. 8 is an energy band diagram of a conventional thin film FET in which the forbidden band widths of the source region and the channel region are equal.

FIG. 9 is an energy band diagram of a conventional thin-film FET in which the forbidden band width of the source region is smaller than that of the channel region.

[Explanation of symbols]

1 SiO _x substrate, second polysilicon film, 2s source region, 2c channel region, 2d drain region, 3 a gate oxide film, 4 a gate electrode, 5 a side wall, _{E C}
The lower end of the conduction band, _{E V} value the upper end of the electron _{band, E f1,}
E _f2 , E _f3 quasi-Fermi level, band gap of BGs source region, band gap of BG _ch channel region, b _sc
Source-channel bias, b _cd channel-drain bias, H ₂ hole

Claims (1)

(57) [Claims] A step of ion-implanting germanium into the silicon thin film using a gate electrode formed on the silicon thin film via a gate insulating film as a mask; and a step of forming a sidewall on a side wall surface of the gate electrode. Implanting germanium into the silicon thin film using both the gate electrode and the sidewall as a mask.