JP2988067B2 - Manufacturing method of insulated field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a P-channel insulated field-effect transistor having a Zener diode between a gate and a source, and more particularly to a method of manufacturing a P-channel insulated field-effect transistor in which a high concentration layer of a Zener diode is sufficiently activated. The present invention relates to a method for manufacturing an effect transistor.

[0002]

2. Description of the Related Art A method of manufacturing a conventional P-channel insulated field effect transistor of this type will be described with reference to FIG. FIG. 3 is a cross-sectional view showing the conventional method in the order of manufacturing steps. In this method, an oxide film 3 is formed on a P-type epi 1 and the oxide film 3 is etched to form an N-type well 2. (Step A), the gate oxide film 3, the gate polysilicon 4
Is formed, and N is formed using the gate polysilicon 4 as a mask.
Form a mold base 5 region. At this time, the zener low-concentration N-type polysilicon 6 is also formed at the same time (step B).

Next, after the back gate 7 is formed (step C), a high-concentration P-type polysilicon 10 layer of zener is formed simultaneously with the formation of the source 9 (step D), and a zener diode is formed between the gate and the source. Is obtained (step E). In FIG. 3, reference numeral 8 denotes a resist, 10 denotes a high-concentration P-type polysilicon, 11 denotes a P-type gate polysilicon, 12 denotes a gate electrode, 13 denotes an interlayer insulating film, and 14 denotes a source electrode.

That is, in the conventional method, after the N-type well 2 is formed, the gate oxide film 3 and the gate polysilicon 4 are formed, and the N-type base 5 is formed using the gate polysilicon 4 as a mask.
And the source 9 are formed. Further, in order to lower the temperature of the heat treatment after the formation of the source, the back gate 7 is formed before the formation of the source 9. As for the formation of the Zener diode, when the N-type base 5 is formed, the low-concentration N-type polysilicon 6 is formed at the same time, and then the high-concentration P-type polysilicon 1 is formed simultaneously with the formation of the source 9.
0 is formed.

[0005]

By the way, in the conventional method, as described above, the high concentration layer of the zener is formed at the same time as the formation of the source 9, but when the gate polysilicon 4 is of a P type, for example, When boron is used as a P-type impurity, in order to prevent the penetration of boron,
The source 9 needs to be formed by heat treatment at about 850 ° C. For this reason, the conventional method has a disadvantage that the high concentration of the Zener diode is not sufficiently activated, and has a problem that the gate leakage current increases.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of manufacturing an insulated field effect transistor which solves the above-mentioned drawbacks and problems. More specifically, a high-concentration layer of a Zener diode is sufficiently activated. Prevent gate leakage current,
An object of the present invention is to provide a method for manufacturing a P-channel insulated field-effect transistor having a stable Zener diode.

[0007]

According to the present invention, the activation is performed simultaneously with the heat treatment of the back gate in order to sufficiently activate the high-concentration layer of the Zener diode. It is. That is, the present invention provides: (1) a step of selectively forming first and second N-type well regions on the surface of a P-type semiconductor layer; and (2) a step of forming polysilicon via an oxide film. (3) removing the oxide film and the polysilicon on the first N-type well region; and (4) forming an N-type base region and forming the polysilicon with a low-concentration N-type polysilicon. (5) forming an N-type back gate region in the N-type base region; and (6) forming a zener diode in the N-type polysilicon.
(7) selectively forming a high-concentration P-type polysilicon region constituting the N-type back- gate region and the P-type polysilicon region by performing a heat treatment at 900 to 1000 ° C. And (8) after the step of activating, the source region in contact with the N-type back gate region and the N-type region in the N-type base region.
Implantation of P-type impurities into p-type polysilicon and before
Heat treatment at a temperature lower than the heat treatment temperature in the activation step,
Is performed to obtain a P-type source region and a P-type gate region.
Is formed under the oxide film under the P-type gate region.
Between the P-type source region and the P-type semiconductor layer.
A step to make a, and (9) the P-type source region and the P-type polysilicon region
And a step of connecting the electrodes by electrode wiring . As described above, in the present invention, in particular, the back gate formation ("(5) step") is performed before the source formation ("(8) step"), and a Zener diode is formed between the gate and the source. In the method for manufacturing a P-channel insulating field effect transistor having the above, the activation of the high-concentration layer of the Zener diode (the heat treatment of the P-type polysilicon region in the above “Step (7)”) is performed simultaneously with the heat treatment of the back gate. It is characterized by the following.

The present invention is carried out in the order of the steps (1) to ( 9 ). The gate polysilicon is P-type and the P-type polysilicon is applied to the gate polysilicon at the time of source formation.
This is a method of simultaneously introducing a type impurity and forming a back gate before forming a source, in which an ion of an N type impurity is implanted into a back gate portion, and ions of a P type impurity are implanted into a part of the Zener. The high-concentration P-type polysilicon layer is activated by performing an implantation and performing a heat treatment at a high temperature simultaneously with the back gate portion. Next, the source part,
P-type impurity ions are implanted into the gate polysilicon portion and heat treatment is performed at a low temperature to form a source and a P-type polysilicon gate. According to the above method of the present invention,
The heat treatment in the high-concentration P-type polysilicon can be performed at a higher temperature than in the conventional method, so that the high-concentration layer of the Zener diode is sufficiently activated.

[0009]

Next, an embodiment of the present invention will be described in detail with reference to FIGS. (Embodiment 1) FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps. First, an oxide film 3 is formed on a P-type epi 1 and the oxide film 3 is formed by photolithography. Etching is performed to form an N-type well 2 (step A), and then the whole is covered with an oxide film 3 and polysilicon 4 is grown (step B). Then, after the oxide film 3 and the polysilicon 4 are etched by photolithography, an N-type base 5 region is formed. At this time, the low concentration N of the Zener
A mold polysilicon 6 is also formed at the same time (step C).

Next, N-type impurities are ion-implanted into the back gate 7, P-type impurities are ion-implanted into a part of the Zener, and heat treatment is performed at 900 to 1000 ° C. A P-type polysilicon 10 is formed (Step D). Thereafter, the source 9 and the P-type gate polysilicon 11 are formed by using a photoresist technique (Step E), and then the interlayer insulating film 13, the gate electrode 12, and the source electrode 14 are formed (Step F). In steps D and E, reference numeral 8 denotes a resist.

(Embodiment 2) FIG. 2 is a sectional view showing another embodiment of the present invention in the order of manufacturing steps. In this embodiment 2, of the first embodiment, the back gate is formed by ion implantation. In that it is a hot gas diffusion.
For this reason, as shown in step A of FIG. 2, after the formation of the N-type base 5, first, ion implantation of a P-type impurity is selectively performed in the low-concentration polysilicon 6, and then, in step B of FIG. As shown, the back gate 7 is opened by the photoresist technique, and the formation of the back gate 7 and the activation of the high-concentration P-type polysilicon 10 are simultaneously performed by diffusion of hot gas.

[0012]

As described in detail above, the present invention is characterized in that the activation of the high-concentration layer of the Zener diode is performed simultaneously with the heat treatment of the back gate. Are sufficiently activated to prevent a gate leakage current, thereby obtaining a stable Zener diode.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating another embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a sectional view showing a conventional method in the order of manufacturing steps.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type epi 2 N-type well 3 Oxide film 4 Polysilicon 5 N-type base 6 Low concentration N-type polysilicon 7 Back gate 8 Resist 9 Source 10 High-concentration P-type polysilicon 11 P-type gate polysilicon 12 Gate electrode 13 Interlayer Insulating film 14 Source electrode

Claims (1)

(57) [Claims] (1) First and second N layers are formed on the surface of a P-type semiconductor layer.
Selectively forming a type well region, (2) removing forming a polysilicon through the oxide film, and (3) the oxide film and the polysilicon on the first N-type well region a step of, while forming a (4) N-type base region, forming a step of the polysilicon and low-concentration N-type polysilicon, the N-type back gate region in (5) the N-type base region And (6) placing a zener diode in the N-type polysilicon.
(7) selectively forming a high-concentration P-type polysilicon region constituting the N-type back- gate region and the P-type polysilicon region by performing a heat treatment at 900 to 1000 ° C. And (8) after the step of activating, the source region in contact with the N-type back gate region and the N-type region in the N-type base region.
Implantation of P-type impurities into p-type polysilicon and before
Heat treatment at a temperature lower than the heat treatment temperature in the activation step,
Is performed to obtain a P-type source region and a P-type gate region.
Is formed under the oxide film under the P-type gate region.
Between the P-type source region and the P-type semiconductor layer.
A step to make a, and (9) the P-type source region and the P-type polysilicon region
Connecting the electrodes with an electrode wiring .