JPH0669439A - Manufacture of cmos semiconductor device - Google Patents

Abstract

PURPOSE:To reduce steps by decreasing a photolithography step in manufacturing a CMOS semiconductor device having a MOS type transistor of an LDD structure. CONSTITUTION:A manufacture of a CMOS semiconductor device comprises the steps of forming a gate electrode 5 and then forming a sidewall 6 on the side of the gate electrode 5, covering a part other than a transistor region of one conductive channel out of a P channel or an N channel with a mask material 7 and introducing an impurity into the transistor region and forming source and drain region layers 8, removing the gate sidewall 6 of the transistor region by an etching and then introducing the impurity and forming an LDD layer 9, covering a part other than a transistor region of the other conductive channel with a mask material 10 and introducing the impurity into the transistor region and forming source and drain region layers 11, and removing the gate sidewall 6 of the transistor region by the etching and then introducing the impurity and forming an LDD layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a CMOS semiconductor device, and more particularly to a method of manufacturing a MOS transistor having an LDD structure (hereinafter referred to as an LDD transistor).

[0002]

CM having a conventional LDD transistor
As a method of manufacturing an OS semiconductor device, a method as shown in FIG. 3 is adopted. In this example, the LDD of the transistor
Only the manufacturing process of the layer and the source / drain layer (SD layer) is extracted. First, as shown in FIG. 3A, the P-type substrate 2
An N well 202 is formed on 01, a field oxide film 203 to be an element isolation region is formed by the LOCOS method, and a gate oxide film 204 and a gate electrode 205 are formed. Then, a pattern is formed using a photoresist so as to cover the region other than the N-channel transistor region, and phosphorus is added to 40 Ke.
The LDD layer 207 is formed by ion implantation of V, about 3 × 10 ¹³ cm ^-2 .

Next, as shown in FIG. 3B, the photoresist 206 is removed, and this time, the region other than the P-channel transistor region is covered, and boron is ion-implanted, for example, at 30 KeV, 3 × 10 ¹³ cm ^-2, and LDD The layer 209 is formed. Then, after removing the photoresist 208, the photoresist 950 is removed in a nitrogen atmosphere.
The LDD layer is activated by performing heat treatment at about 20 ° C. for about 20 minutes.
Subsequently, as shown in FIG. 3C, an oxide film having a thickness of about 0.2 μm is grown on the entire surface, and the entire surface is etched back to leave the oxide film only on the side of the gate electrode.
Form 0. Further, a 20 to 30 nm oxide film is deposited on the entire surface by the CVD method.

Thereafter, as shown in FIG. 3D, aluminum is deposited on the entire surface by about 1 μm, and a pattern is formed so that the aluminum 211 remains in areas other than the N channel region. Then, arsenic is ion-implanted at 70 KeV and about 5 × 10 ¹⁵ cm ⁻² to form an N ⁺ layer 212 as an SD layer. At this time, arsenic does not enter under the side wall, and only the LDD layer 207 introduced previously is formed. That is, the LDD structure is obtained.

Further, as shown in FIG. 3 (e), after the aluminum pattern 211 is removed, a pattern is formed by the same procedure as described above so that the aluminum 213 is left except in the P channel region. Next, add boron to 30 Ke
V, about 5 × 10 ¹⁵ cm ^{-2 is} ion-implanted and P as SD layer
^{A +} layer 214 is formed. As with the N channel side, boron does not enter under the side wall, and only the LDD layer 209 is formed,
It has an LDD structure. After this, the aluminum pattern 21
By removing 3 and performing heat treatment at 900 ° C. for about 10 minutes in a nitrogen atmosphere to activate the source / drain layers, the N-channel and P-channel transistor portions are completed.

[0006]

In this conventional method of manufacturing an LDD transistor, the photolithography process for pattern formation is performed by using the LDD of an N-channel transistor.
Layer formation, LDD layer formation of P-channel transistor, SD layer formation of N-channel transistor, SD layer formation of P-channel transistor are required four times, therefore four pattern masks are required and the process is long. was there. An object of the present invention is to provide a method for manufacturing a CMOS semiconductor device in which the photolithography process is reduced and the process is shortened.

[0007]

According to the manufacturing method of the present invention, after a gate electrode is formed, a sidewall is formed on the side surface of the gate electrode, and a transistor having one of P-channel and N-channel conductive channels is formed. A step of covering a region other than the region with a mask material and introducing an impurity into the transistor region to form a source / drain layer, and etching and removing a gate sidewall of the transistor region, and then introducing an impurity to form an LDD layer And a step of covering the portion other than the transistor region of the other conductive channel with a mask material, introducing impurities into the transistor region to form a source / drain layer, and etching and removing the gate sidewall of the transistor region. And the step of forming impurities to form an LDD layer.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a manufacturing process according to an embodiment of the present invention.
First, as shown in FIG. 1A, an N well 2 is formed on a P-type substrate 1.
And the field oxide film 3 to be an element isolation region is formed as L
It is formed by the OCOS method, and then the gate oxide film 4 and the gate electrode 5 are formed. Further, in order to form the side wall 6, a silicon nitride film is deposited on the entire surface by the CVD method to a thickness of about 0.2 μm, and the entire surface is etched back until the upper part of the gate electrode is exposed. As a result, the sidewall 6 of the nitride film is formed on the side surface of the gate electrode 5.

Next, as shown in FIG. 1B, a pattern is formed so as to cover the side wall 6 and a material having etching selectivity, here, a photoresist 7, so as to cover portions other than the N channel region, and ion implantation is performed. Arsenic is used at 70 KeV, 5 × 10 ¹⁵ cm
By implanting at ^-2 , the N ⁺ layer 8 as the SD layer is formed. Then, as shown in FIG. 1C, the sidewall nitride film 6 is removed by using isotropic plasma etching to remove phosphorus by 40.
The LDD layer 9 is formed by ion implantation at KeV of about 3 × 10 ¹³ cm ^-2 . Since the side wall is removed here, the LDD layer is formed below the side wall. At this time, the P channel side is not affected because it is entirely covered with the photoresist 7. And
After removing the photoresist pattern 7, the SD layer and L
For the DD layer, heat treatment at 950 ° C. for about 20 minutes is performed in a nitrogen atmosphere.

Next, as shown in FIGS. 1 (d) and 1 (e), P
The photoresist pattern 10 is formed on the channel region by the same procedure, and the SD layer 1 is formed using the photoresist pattern 10.
1 and the LDD layer 12 are formed. Ion implantation is performed with S
Boron is implanted at 30 KeV, 5 × 10 ¹⁵ cm ^-2 when the D layer 11 is formed, and boron is implanted at 30 KeV, 3 × 10 ¹³ when the LDD layer 12 is formed.
Inject about cm ^-2 . And the photoresist pattern 1
After removing 0, heat treatment at 900 ° C. for about 10 minutes is performed in a nitrogen atmosphere in order to activate the SD layer and the LDD layer in the P channel region.

According to this manufacturing method, the SD layer and the LDD layer in the N channel region can be formed by one photolithography step, and the SD layer and the LDD layer in the P channel region can be formed by another photolithography step. Is possible. This makes it possible to perform C in only two photolithography steps in total.
An LDD transistor having a MOS structure can be formed, only two photomasks are required, and the process can be significantly shortened.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps. The process of FIG. 2A is almost the same as the example of FIG. 101 is a P type substrate, 102 is an N well, 1
03 is a field insulating film, 104 is a gate oxide film, 10
Reference numeral 5 is a gate electrode, and 106 is a side wall. However, the side wall 1
As the material of 06, titanium is used instead of the silicon nitride film. That is, after forming the gate electrode 105 of polycrystalline silicon, titanium having a thickness of about 0.2 μm is sputter-deposited on the entire surface, and the entire surface is etched back by ion etching until the upper portion of the gate electrode is exposed.

Next, as shown in FIG. 2B, 20 to 30 are formed on the entire surface.
An oxide film 107 having a thickness of about nm is deposited by the CVD method. Further, a nitride film of about 0.5 μm is deposited on the entire surface by plasma CVD, and the nitride film is etched by using a photolithography technique so that the nitride film pattern 108 is left in regions other than the N channel region. Subsequently, arsenic is ion-implanted at 70 KeV and 5 × 10 ¹⁵ cm ⁻² to form an N ⁺ layer 109 as an SD layer. After that, heat treatment is performed in a nitrogen atmosphere at 950 ° C. for about 10 minutes to activate the SD layer.

Next, as shown in FIG. 2C, the oxide film 107 and the side wall 106 are sequentially etched using the nitride film pattern 108 as a mask. Titanium on the side wall can be etched with a mixed solution of hydrogen peroxide and ammonia. Then, phosphorus is implanted at 40 KeV and about 3 × 10 ¹³ cm ^-2 to form the LDD layer 110.
To form. Next, in order to activate the LDD layer, heat treatment is performed in a nitrogen atmosphere at 950 ° C. for about 10 minutes, and in addition, oxidation is performed at 900 ° C. for about 10 minutes in dry oxygen. By this oxidation, an oxide film of about 20 to 30 nm is formed around the gate electrode 105 of polycrystalline silicon.

After removing the nitride film pattern 108 with phosphoric acid, a nitride film pattern 112 is formed in the same procedure as shown in FIGS. 2D and 2E, and the P channel region is formed by using the nitride film pattern 112. Then, the SD layer 113 and the LDD layer 114 are formed. Ion implantation and the like may be performed in the same manner as in the example of FIG. Further, heat treatment is performed at 900 ° C. for about 10 minutes in a nitrogen atmosphere to activate the SD layer and the LDD layer, and the nitride film pattern 11
After removing 2, the process may proceed to the next step.

In the second embodiment, since the heat-resistant material such as titanium or silicon nitride film is used for the side wall and the mask material for ion implantation, it is possible to heat-treat the SD layer and the LDD layer separately. The design is flexible. Moreover, similar to the example of FIG. 1, the LDD structure of the N-channel and P-channel transistors can be realized by only two photolithography steps of two masks. In the above-mentioned embodiments, the examples of the combination of the sidewall material and the ion implantation mask material which are required to have selectivity for etching are silicon nitride film and photoresist, titanium and silicon nitride film. It goes without saying that the present invention in which the LDD transistor is realized by using the photolithography technique twice can be applied even if the combination is used.

[0017]

As described above, according to the present invention, when forming the LDD transistors of the P and N channels, the sidewalls of the gate electrodes are uniformly formed, and then one and the other transistor regions are masked in order. Since the SD layer is formed in this state and the LDD is formed by removing the gate sidewall, the N-channel LDD transistor and the P-channel transistor can be manufactured only by two photolithography steps. Therefore, the number of photomasks is reduced to two, and at the same time, the manufacturing process can be significantly reduced, resulting in low cost
It is possible to supply a semiconductor device with a short delivery time.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a cross-sectional view showing an example of a conventional manufacturing method in the order of manufacturing steps.

[Explanation of symbols]

 1,101 P-type substrate 2,102 N well 5,105 Gate electrode 6,106 Side wall 7 Photoresist 8,11 SD layer 9,12 LDD layer 10 Photoresist 107 Oxide film 108 Nitride film 109,113 SD layer 110,114 LDD layer 111 Oxide film 112 Nitride film

Claims (1)

[Claims] 1. When manufacturing a CMOS semiconductor device having N-channel and P-channel MOS transistors having an LDD (Lightly Doped Drain) structure, after forming a gate electrode, forming a side wall on the side surface of the gate electrode, A step of forming a source / drain layer by introducing an impurity into the transistor region by covering a portion other than the transistor region of one conductive channel with a mask material, and removing the gate side wall of this transistor region by etching and then introducing the impurity To form an LDD layer, a step of forming a source / drain layer by covering an area other than the transistor region of the other conductive channel with a mask material and introducing an impurity into the transistor area, and a gate sidewall of the transistor area. LD after etching and removing impurities
CMOS including the step of forming a D layer
Manufacturing method of semiconductor device.