KR100201775B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100201775B1 KR100201775B1 KR1019950031710A KR19950031710A KR100201775B1 KR 100201775 B1 KR100201775 B1 KR 100201775B1 KR 1019950031710 A KR1019950031710 A KR 1019950031710A KR 19950031710 A KR19950031710 A KR 19950031710A KR 100201775 B1 KR100201775 B1 KR 100201775B1
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- South Korea
- Prior art keywords
- mask layer
- forming
- layer pattern
- oxide mask
- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 12
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000010408 film Substances 0.000 abstract 3
- 239000010409 thin film Substances 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
본 발명은 소자분리가 이루어지지 않은 반도체 기판 상에 게이트 절연막 및 게이트 전도막 패턴을 형성하는 단계; 이온주입으로 소오스/드레인의 저농도 불순물 영역을 형성하는 단계; 상기 게이트 전도막 패턴을 덮으면서 소자분리영역의 반도체 기판이 오픈된 산화마스크층 패턴을 형성하는 단계; 상기 산화마스크층 패턴이 덮히지 않은 상기 반도체 기판을 산화시켜 필드산화막을 형성하는 단계; 상기 산화마스크층 패턴을 비등방성 전면식각하여 상기 게이트 전도막 패턴의 측벽에 산화마스크층 스페이서를 형성하는 단계; 이온주입으로 소오스/드레인의 고농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치 제조 방법에 관한 것으로, LOCOS 공정시의 산화마스크층과 트랜지스터 측벽의 스페이서를 동일한 박막으로 각각 사용함으로써 공정 단계를 획기적으로 감소시켜 소자의 신뢰도 및 수율 증가와 생산성 향상을 가져오는 효과가 있다.The present invention includes forming a gate insulating film and a gate conductive film pattern on a semiconductor substrate without device isolation; Forming a low concentration impurity region of a source / drain by ion implantation; Forming an oxide mask layer pattern on which the semiconductor substrate in the device isolation region is opened while covering the gate conductive layer pattern; Oxidizing the semiconductor substrate not covered with the oxide mask layer pattern to form a field oxide film; Anisotropically etching the oxide mask layer pattern to form an oxide mask layer spacer on sidewalls of the gate conductive layer pattern; A method for fabricating a semiconductor device, comprising forming a highly doped impurity region of a source / drain by ion implantation, wherein the process step is performed by using an oxide mask layer and a spacer of a transistor sidewall as the same thin film in the LOCOS process. This drastically reduces the reliability and yield of the device, and increases the productivity.
Description
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 반도체 장치 제조 공정도.1A through 1D are diagrams illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 실리콘 기판 2 : 게이트 산화막1 silicon substrate 2 gate oxide film
3 : 게이트 폴리실리콘막 4 : N-이온주입영역3: gate polysilicon film 4: N - ion implantation region
5 : 산화막 6,6a,6b : 질화막5: oxide film 6,6a, 6b: nitride film
7 : 필드산화막 8 : N+이온주입영역7: field oxide film 8: N + ion implantation region
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 반도체 장치를 구성하는 트랜지스터를 먼저 형성한 후, 소자간의 절연을 위한 필드산화막을 이후에 실시하여, 트랜지스터의 게이트 측벽 스페이서 및 아이솔레이션시의 산화마스크층을 동시에 사용하는 반도체 장치 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a transistor constituting the semiconductor device is first formed, and then a field oxide film for insulation between the devices is subsequently performed to form a gate sidewall spacer of the transistor and an oxide mask layer at the time of isolation. It relates to a semiconductor device manufacturing method to be used at the same time.
통상적인 반도체 장치 제조 방법은, 먼저 소자간의 절연을 위한 아이솔레이션 공정을 실시하여 반도체 기판 상에 필드산화막을 형성한 다음, 이 필드산화막에 의해 분리된 각 활성영역의 반도체 기판 상에 트랜지스터를 형성하고 있다.In a conventional semiconductor device manufacturing method, a field oxide film is formed on a semiconductor substrate by first performing an isolation process for insulation between devices, and then a transistor is formed on a semiconductor substrate in each active region separated by the field oxide film. .
아이솔레이션 공정은 국부산화공정인 LOCOS(Local Oxidation Of Silicon) 공정이 널리 이용되고 있으며, LOCOS 공정은 보통 질화막을 반도체기판의 산화 마스크로 사용하여 반도체 기판을 선택적으로 산화시킴으로써 필드산화막을 형성하는 방법이다.Localization of silicon (LOCOS) process, which is a local oxidation process, is widely used. The LOCOS process is a method of forming a field oxide film by selectively oxidizing a semiconductor substrate using a nitride film as an oxide mask of a semiconductor substrate.
한편, 트랜지스터 형성시에는 저농도 불순물 주입 영역 및 고농도 불순물 주입 영역으로 이루어지는 LDD(Lightly Doped Drain)구조의 소오스/드레인 접합을 얻기 위하여 트랜지스터의 게이트 측벽에 절연막 스페이서를 형성하고 있다.On the other hand, when forming the transistor, an insulating film spacer is formed on the gate sidewall of the transistor to obtain a source / drain junction of a lightly doped drain (LDD) structure including a low concentration impurity implantation region and a high concentration impurity implantation region.
상기한 바와 같이 종래에는 아이솔레이션 공정을 실시한 다음, LDD 구조의 트랜지스터를 형성하고 있는데, 그 세부적인 공정 단계는 다음과 같다.As described above, the transistor of the LDD structure is formed after the isolation process is performed. The detailed process steps are as follows.
종래에는 반도체 기판 상에 아이솔레이션 마스크 패턴(산화방지막 패턴)을 형성하는 공정, 열산화에 의해 필드산화막을 성장시키는 공정, 마스크 패턴을 제거하는 공정, 게이트 산화막 및 게이트 전극 패턴을 형성하는 공정, 저농도 불순물 이온주입을 실시하는 공정, 게이트 전극 측벽에 스페이서 절연막을 형성하는 공정, 및 고농도 불순물을 이온주입하는 공정이 차례로 이루어지게 된다.Conventionally, a process of forming an isolation mask pattern (antioxidation film pattern) on a semiconductor substrate, a process of growing a field oxide film by thermal oxidation, a process of removing a mask pattern, a process of forming a gate oxide film and a gate electrode pattern, and low concentration impurities A step of ion implantation, a step of forming a spacer insulating film on the sidewall of the gate electrode, and a step of ion implantation of high concentration impurities are performed in this order.
이와 같이 종래에는 반도체 장치가 점차 고집적화 되어가고 그에 따라 공정 역시 매우 복잡해지고 있으며, 많은 공정 단계가 수행됨에 따라 파티클(paticle)의 다량 발생으로 소자의 신뢰성 및 수율이 떨어지는 문제점이 발생한다.As such, in the related art, semiconductor devices are gradually becoming highly integrated, and accordingly, the process is also very complicated, and as many process steps are performed, a large amount of particles are generated, resulting in a problem that the reliability and yield of the device are lowered.
본 발명은 공정 단계를 최소화하여 공정을 간소화하는 반도체 장치 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device, which minimizes the process steps and simplifies the process.
상기 목적을 달성하기 위하여 본 발명은 반도체 장치 제조 방법에 있어서; 소자 분리가 이루어지지 않은 반도체 기판 상에 게이트 절연막 및 게이트 전도막 패턴을 형성하는 단계; 이온주입으로 소오스/드레인의 저농도 불순물 영역을 형성하는 단계; 상기 게이트 전도막 패턴을 덮으면서 소자분리영역의 반도체 기판이 오픈된 산화마스크층 패턴을 형성하는 단계; 상기 산화마스크층 패턴이 덮히지 않은 상기 반도체 기판을 산화시켜 필드산화막을 형성하는 단계; 상기 산화마스크층 패턴을 비등방성 전면식각하여 상기 게이트 전도막 패턴의 측벽에 산화마스크층 스페이서를 형성하는 단계; 이온주입으로 소오스/드레인의 고농도 불순물 영역을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the present invention provides a semiconductor device manufacturing method; Forming a gate insulating film and a gate conductive film pattern on a semiconductor substrate in which device isolation is not performed; Forming a low concentration impurity region of a source / drain by ion implantation; Forming an oxide mask layer pattern on which the semiconductor substrate in the device isolation region is opened while covering the gate conductive layer pattern; Oxidizing the semiconductor substrate not covered with the oxide mask layer pattern to form a field oxide film; Anisotropically etching the oxide mask layer pattern to form an oxide mask layer spacer on sidewalls of the gate conductive layer pattern; Forming a high concentration impurity region of the source / drain by ion implantation.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 살펴본다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1d도는 본 발명의 일실시예에 따른 반조체 장치 제조 공정도로서, 먼저, 제1a도와 같이 아이솔레이션이 이루어지지 않은 실리콘 기판(1) 상에 게이트 산화막(2) 및 게이트 전극용 폴리실리콘막(3)을 패터닝하고 저농도 불순물을 이온주입하여 저농도 불순물 이온주입 영역, 예컨대 N-이온주입영역(4)을 형성한다.1A to 1D are process charts for manufacturing a semi-fabricated device according to an embodiment of the present invention. First, as shown in FIG. The silicon film 3 is patterned and ion implanted with low concentration impurities to form a low concentration impurity ion implantation region, such as an N − ion implantation region 4.
이어서, 제1b도와 같이 전체구조 상부에 스트레스 방지용 산화막(5) 및 산화 마스크 물질인 질화막(6)을 차례로 형성한다.Subsequently, as shown in FIG. 1B, an oxide film 5 for preventing stress and a nitride film 6 as an oxide mask material are sequentially formed on the entire structure.
이어서, 제1c도에 도시된 바와 같이, 마스크 및 식각 공정으로 질화막 패턴(6a)을 형성하고 열산화 공정으로 소자분리용 필드산화막(7)을 형성한다. 이때 질화막 패턴(6a)을 형성할 시 아이솔레이션 영역의 실리콘 기판이 노출되어도 되며 산화막(5)이 잔류하고 있어도 무방하다.Subsequently, as shown in FIG. 1C, the nitride film pattern 6a is formed by a mask and an etching process, and the field oxide film 7 for device isolation is formed by a thermal oxidation process. At this time, when forming the nitride film pattern 6a, the silicon substrate in the isolation region may be exposed or the oxide film 5 may remain.
이어서, 제1d도와 같이 상기 질화막 패턴(6a)을 비등방성 전면식각하여 폴리실리콘막(3)이 측벽에 질화막 스페이서(6b)를 형성한 다음, 고농도 불순물을 이온주입하여 고농도 불순물 이온주입영역, 예컨대 N+이온주입영역(8)을 형성하므로써, N-이온주입영역(4) 및 N+이온주입영역(8)으로 이루어지는 소오스/드레인 접합을 형성한다.Subsequently, as shown in FIG. 1D, the nitride film pattern 6a is anisotropically etched to form the nitride film spacer 6b on the sidewall of the polysilicon film 3, and then ion implantation is performed to implant a high concentration impurity ion implantation region, for example, by forming N + ion implantation regions 8, N - ion implantation region 4 and a N + ion-implanted region 8 is formed in the source / drain junctions made of.
상기한 바와 같은 본 발명은 LOCOS 공정시의 기판산화방지막인 질화막을 트랜지스터 측벽의 스페이서로 사용할 수 있어, 공정 단계를 획기적으로 감소시켜 파티클의 발생을 억제함으로써 반도체 장치의 신뢰도 및 수율 증가와 생산성 향상을 가져오는 효과가 있다.As described above, the present invention can use a nitride film, which is a substrate anti-oxidation film in the LOCOS process, as a spacer on the sidewalls of the transistor, thereby significantly reducing process steps and suppressing generation of particles, thereby improving reliability and yield and increasing productivity of semiconductor devices. It has an effect.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031710A KR100201775B1 (en) | 1995-09-25 | 1995-09-25 | Method of manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950031710A KR100201775B1 (en) | 1995-09-25 | 1995-09-25 | Method of manufacturing semiconductor device |
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| Publication Number | Publication Date |
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| KR970018254A KR970018254A (en) | 1997-04-30 |
| KR100201775B1 true KR100201775B1 (en) | 1999-06-15 |
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| KR1019950031710A KR100201775B1 (en) | 1995-09-25 | 1995-09-25 | Method of manufacturing semiconductor device |
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1995
- 1995-09-25 KR KR1019950031710A patent/KR100201775B1/en not_active IP Right Cessation
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| KR970018254A (en) | 1997-04-30 |
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