JPH04257267A - Manufacture of soi-structured semiconductor device - Google Patents

Abstract

PURPOSE:To provide a back-channel control suitable for each of a p-channel transistor and n-channel transistor of a CMOS transistor by controlling a threshold value of a back-channel selectively and easily. CONSTITUTION:In the manufacture of this device, a process in which an impurity-doped region 6 for controlling a back-channel is formed on the surface of a supporting-side silicon substrate 1 through a thin silicon layer 2 and an insulated film 3 formed in the rear of the layer 2 and a process in which a MOSFET is formed in the thin silicon layer are included.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to SOI (silico
MOSFET (metal ox
ide semiconductor field
The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing an effect transistor.

[0002] In general, semiconductor devices using SOI structure substrates are superior to semiconductor devices using ordinary bulk substrates in terms of operating speed, degree of integration, and radiation resistance. Although much effort is being put into it, problems remain to be resolved, such as back channel issues.

0003

[Prior Art] Normally, when using an SOI structure substrate, the operating speed of a semiconductor element can be improved by bonding a support side Si substrate with an insulating film made of silicon dioxide (SiO2). A major reason for this is that the Si layer into which semiconductor elements are built has become thinner. However, when the Si layer is made thinner, in addition to a normal channel called a front channel that appears on the surface side, a channel also appears on the back side at the interface with the insulating film, and it has an effect as a so-called back channel. turn into. Since this back channel changes the threshold voltage of the MOSFET, it is necessary to control the threshold voltage of the back channel so as not to adversely affect the operation of the MOSFET.

MOSFE using conventional SOI structure substrate
At T, a back bias voltage is applied to the supporting Si substrate to control the back channel of the MOSFET built in the Si layer.

[0005]

[Problem to be Solved by the Invention] As mentioned above, back bias voltage is applied to the supporting side Si substrate.
To reduce the channel effects, it is necessary to apply a negative back bias voltage to the n-channel transistor and a positive back bias voltage to the p-channel transistor. Therefore, for example, C
MOS (complementary metal)
oxide semiconductor) transistors, it is necessary to apply different voltages to the p-channel transistor and the n-channel transistor, but CM using an SOI structure substrate
In OS transistors, since the support side Si substrate is common, it is difficult to control the threshold voltages of the p-channel transistor and the n-channel transistor by applying a back bias voltage.

The present invention allows selective and easy control of back channel thresholds, such as
It is intended to enable suitable back channel control for each p-channel transistor or n-channel transistor in an OS transistor.

[0007]

[Means for Solving the Problems] FIG. 1 is a cross-sectional side view of a main part of a MOSFET using an SOI structure substrate for explaining the principle of the present invention. In the figure, 1 is the support side Si
The substrate, 2 is a thin Si layer, 3 is silicon dioxide (
4 is a gate insulating film made of SiO2, 5 is a channel region, 6 is an impurity introduced region, 7 is a source region, 8 is a drain region, 9 is a polycrystalline Si
The reference numeral 10 indicates a gate electrode made of SiO2, and an element isolation region made of SiO2.

In this MOSFET, the impurity introduced region 6
If the impurity doped region 6 is an n-type, the back channel also tends to become an n-type, and if the impurity-introduced region 6 is a p-type, the back channel also tends to become a p-type. Therefore, by utilizing this phenomenon, the back channel threshold can be made larger compared to the front channel threshold, and M
The threshold value as an OSFET becomes dominated by the front channel threshold value.

For these reasons, in the method of manufacturing a semiconductor device according to the present invention, (1) a thinned silicon layer (for example, a thinned Si layer 2 ) and the insulating film (for example, the insulating film 3 made of SiO2) on the back side, and implant impurity ions into the surface of the supporting silicon substrate (for example, the supporting Si substrate 1) to control the back channel. a step of forming an impurity-introduced region (for example, an impurity-introduced region 6) for the active layer, and a step of forming a MOSFET in the thinned silicon layer that is the active layer;
Alternatively, (2) in (1) above, the implantation of impurity ions to form the impurity introduction region for controlling the back channel is also performed as a channel dose to the thinned silicon layer that is the active layer. (3) In the above (1) or (2), the back
The implantation of impurity ions forming the impurity introduction region for controlling the channel is selectively performed using impurity ions having different conductivity types, or (4)
) In (1) or (2) above, the implantation of impurity ions forming the impurity introduction region for controlling the back channel is carried out using impurity ions with selectively different concentrations. Features.

0010

[Function] In the present invention, as mentioned above, the active layer S
Impurity ions are also implanted into the surface of the supporting Si substrate 1 through the i-layer 2 and the underlying insulating film 3 to form an impurity-introduced region 6. Normally, impurities of a conductivity type different from that of the channel region 5 are introduced into the polycrystalline Si constituting the gate electrode 9, so that the thickness of the gate insulating film 4 is equal to that of the underlying insulating film 3. , and if the impurity concentration in the channel region 5 is uniform, the threshold value of the back channel will be larger than that of the front channel. For this reason, the threshold value of the MOSFET is dominated by the threshold value of the front channel, and the influence of the back channel can be suppressed.
If the conductivity type is appropriately selected, both p-channel transistors and n-channel transistors are equivalent, so it is particularly effective for incorporating CMOS transistors into SOI structure substrates. , CMO
Good results can be obtained by applying this method not only to S transistors but also to manufacturing semiconductor devices in which it is necessary to change the applied voltage depending on the semiconductor element.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 2 and 3 are cross-sectional side views of essential parts of a MOSFET at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures. Furthermore, Figure 1
The same symbols used in the above shall represent the same parts or have the same meaning.

Refer to FIG. 2 2-(1) A wafer having an SOI structure prepared by applying a conventional technique is prepared. Examples of the main data are as follows. Thickness of Si layer 2 as active layer: 100 [nm] Thickness of insulating film 3 as base: 15 [nm] 2-(2) By applying the ion implantation method, channels and This step is a characteristic feature of the present invention. That is, for example, an n-channel MOSFE
In the case of T, boron (B) ions are implanted at a dose of about 1012 [cm-2] and an accelerating voltage of about 50 [keV]. Boron is also implanted into the surface of the supporting Si substrate 1 by penetrating the silicon substrate 3. By going through this process, the surface of the support side Si substrate 1 has a thickness of 1016 [cm-3].
] to 10<17>[cm<-3>] of boron is implanted to form the impurity-introduced region 6, and the threshold of the back channel can be made larger than that of the front channel. Note that this step can be performed after removing the oxidation-resistant mask formed in step 3-(1), which will be explained later, and the heat treatment for impurity activation can also be performed to activate other impurity regions. Just go.

Refer to FIG. 3 3-(1) For example, selective thermal oxidation (for example, l
ocal oxidation of silico
By applying the n:LOCOS) method, SiO2
An inter-element isolation region 10 is formed. 3-(2) After removing the oxidation-resistant mask, by applying a thermal oxidation method, S with a thickness of, for example, 15 [nm] is
A gate insulating film 4 made of iO2 is formed. 3-(3) Chemical vapor deposition
A polycrystalline Si film having a thickness of, for example, 300 [nm] is formed by applying a chemical vapor deposition (CVD) method. 3-(4) The polycrystalline Si film is patterned to form the gate electrode 9 by applying a normal photolithography technique. 3-(5) By applying the ion implantation method, arsenic ions are implanted using the gate electrode 9 and the isolation region 10 as a mask to form the source region 7 and drain region 8.
form. 3-(6) Thereafter, a conventional technique is applied to form an insulating film, an electrode contact window, a source electrode, a drain electrode, other wiring, etc., and complete the process.

FIG. 4 is a diagram showing the impurity concentration profile when impurity ions are implanted as explained in step 2-(2), and the horizontal axis shows distance [μm].
, and the impurity concentration [cm-3] is plotted on the vertical axis. The vertical axis is a log scale, and the same symbols as those used in FIG. 1 represent the same parts or have the same meaning. As is clear from the figure, the support side S
The surface of the i-substrate 1 has a thickness of about 1 x 1016 [cm-3] to 1
It can be seen that approximately x1017 [cm-3] of boron has been introduced.

[0015] In the above embodiment, the case of manufacturing an n-channel MOSFET was explained, but a p-channel MOSFET
If ET is to be manufactured, in step 2-(2), arsenic ions or phosphorus ions are implanted instead of boron ions, and in step 3-(5),
Boron ions can be implanted instead of arsenic ions, and if CMOS transistors are to be manufactured, impurities of the conductivity type required for the areas where n-channel transistors and p-channel transistors are to be formed can be implanted. This can be obtained by forming the introduction region 6 and forming source and drain regions of opposite conductivity types.

As another modification, it is also possible to make the impurity introduced regions 6 all of the same conductivity type but with selectively different impurity concentrations.

[0017]

[Effects of the Invention] In the method for manufacturing an SOI structure semiconductor device according to the present invention, a back channel is formed on the surface of the supporting silicon substrate by penetrating the thinned silicon layer and the insulating film on the back side thereof. A step of forming an impurity introduction region for controlling the
A step of forming a T is included.

By adopting the above structure, if the thickness of the gate insulating film is equal to the thickness of the insulating film at the bonding interface, and the impurity concentration in the channel region is uniform, the back - The threshold of the channel is larger compared to that of the front channel, so the MOSFE
As for the threshold value T, the threshold value of the front channel becomes dominant, and the influence of the back channel can be suppressed.

[0019] Furthermore, since such an effect is the same in both p-channel transistors and n-channel transistors as long as the conductivity type of the impurity-introduced region is appropriately selected, it can be applied to SOI structure substrates. This is particularly effective when incorporating CMOS transistors.

Furthermore, good results can be obtained by applying the present invention not only to CMOS transistors but also to manufacturing semiconductor devices in which it is necessary to change the applied voltage depending on the semiconductor element.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional side view of a main part of a MOSFET using an SOI structure substrate for explaining the principle of the present invention.

FIG. 2 is a cutaway side view of a main part of a MOSFET at key points in the process for explaining an embodiment of the present invention.

FIG. 3 is a cutaway side view of a main part of a MOSFET at a key point in the process for explaining an embodiment of the present invention.

FIG. 4 is a diagram showing an impurity concentration profile when impurity ions are implanted as described in step 2-(2).

[Explanation of symbols]

1 Support side Si substrate, 2 Thinned Si layer 3
Insulating film 4 made of silicon dioxide (SiO2)
Gate insulating film 5 made of SiO2 Channel region 6 Impurity introduced region 7 Source region 8 Drain region 9 Gate electrode made of polycrystalline Si

Claims (4)

[Claims] Claim 1: Impurity ions are implanted into the surface of the supporting silicon substrate through the thinned silicon layer, which is the active layer in which the MOSFET is to be fabricated, and the insulating film on the back side of the silicon layer to form a back channel. A method for manufacturing an SOI structure semiconductor device, comprising the steps of forming an impurity-introduced region for control, and then forming a MOSFET in the thinned silicon layer that is the active layer. . [Claim 2] A claim characterized in that implantation of impurity ions to form an impurity introduction region for controlling a back channel is carried out also as a channel dose to a thinned silicon layer which is an active layer. 2. A method for manufacturing an SOI structure semiconductor device according to item 1. 3. Implantation of impurity ions to form an impurity introduction region for controlling a back channel is selectively performed using impurity ions having different conductivity types. 2. The method for manufacturing an SOI structure semiconductor device according to 2. 4. The implantation of impurity ions forming the impurity introduction region for controlling the back channel is performed using impurity ions with selectively different concentrations. 3. A method for manufacturing an SOI structure semiconductor device according to item 2.