JP2611363B2 - Insulated gate field effect transistor and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an insulated gate field effect transistor and a method for manufacturing the same.

[Conventional technology]

An insulated gate field effect transistor (MISFET) used for a VLSI uses an N-type gate electrode using polysilicon doped with phosphorus for a P-channel MISFET. For this purpose, a P-type impurity is ion-implanted into the channel region to form a structure called a buried channel, and the threshold voltage _{Vth of the} transistor is set to a desired value.

The buried channel structure is a structure in which a channel is formed not at the interface between the gate insulating film and the silicon substrate but at a deep place away from the gate insulating film. In this buried channel structure, when the transistor is shortened, a phenomenon called punch-through in which a current that cannot be controlled by the gate flows becomes remarkable. In order to prevent this punch-through, as shown in FIG. 3, it is desirable that the transistor has a surface channel structure using the P-type gate electrode 204. 201 is N
Type silicon substrate, 202, 203 'are source / drain regions, 2
Reference numeral 03 denotes a gate insulating film, in which polysilicon doped with boron is used as the P-type gate electrode 204, and an undoped oxide film is used as the gate insulating film 203. The surface channel structure is a structure in which a channel is formed at an interface between a gate insulating film and a silicon substrate.

[Problems to be solved by the invention]

In a conventional insulated gate field effect transistor having a surface channel structure, polysilicon doped with boron is used as a P-type gate electrode, and an undoped oxide film is used as a gate insulating film. However, it is known that boron has a “boron penetration phenomenon” that diffuses in an oxide film at an abnormal speed when subjected to a high temperature treatment. For this reason, in the conventional insulated gate field effect transistor having the surface channel structure, there is a problem that boron diffuses to the channel region and the threshold voltage _Vth is difficult to control.

Furthermore, mobile ions such as sodium in the gate insulating film, which cannot be removed by the current process technology, move freely in the oxide film that is not doped at all, and cause unstable operation of the transistor. Was.

An object of the present invention is to suppress the penetration of boron by making the gate insulating film have a two-layer structure of an insulating film to which phosphorus is added and an insulating film to which no impurity is added, and to use a gettering effect by phosphorus. P-channel MIS suitable for VLSI by immobilizing mobile ions
An object of the present invention is to provide an FET structure and a manufacturing method for realizing the structure.

[Means for solving the problem]

According to the present invention, in a P-channel insulated gate field effect transistor using a P-type gate electrode, a gate insulating film has a two-layer structure of an insulating film doped with phosphorus and an insulating film doped with no impurity. It is characterized by.

The present invention also provides a method of manufacturing a P-channel type insulated gate field effect transistor using a P-type gate electrode, wherein a step of forming a first insulating film to which no impurity is added on a substrate; The method is characterized by including a step of forming a second insulating film to which phosphorus is added on the insulating film, and a step of forming a P-type gate electrode on the second insulating film.

[Action]

It has long been known that when phosphorus and boron coexist in a gate electrode, boron does not cause a penetration phenomenon. By taking the above measures, phosphorus and boron can coexist, and the penetration phenomenon of boron can be suppressed.

It has also been known for some time that a phosphorus-added insulating film has a gettering effect of immobilizing mobile ions. Therefore, by taking the above measures,
An insulating film to which phosphorus is added can be formed in part of the gate insulating film, and mobile ions can be immobilized by a gettering effect of the film.

〔Example〕

FIG. 1 is a schematic sectional view of a P-channel insulated gate field effect transistor which is an embodiment of the insulated gate field effect transistor of the present invention. The gate insulating film has a two-layer structure of a non-doped oxide film 103 to which no impurity is added and a phosphorus-doped oxide film 104 to which phosphorus is added. The other structure is the same as that of the conventional structure shown in FIG. 3, wherein 101 indicates an N-type silicon substrate, 102 and 102 'indicate P-type source / drain regions, and 105 indicates a P-type gate electrode.

 Next, the manufacturing method will be described.

2 (a) to 2 (f) are schematic cross-sectional views showing the steps of manufacturing the P-channel insulated gate field effect transistor shown in FIG.

First, in FIG. 2A, an N-type silicon substrate 101 is formed.
A non-doped oxide film 103 is formed thereon.

Next, as shown in FIG. 2 (b), a non-doped oxide film
A phosphorus-doped polysilicon film 110 is formed on 103.

After that, high temperature treatment of about 1000 ° C. is performed, and FIG. 2 (c)
A phosphorus-doped oxide film 104 as shown in FIG.

After the above steps, the phosphorus-doped polysilicon film 110 is removed as shown in FIG.

A non-doped polysilicon film 106 is deposited on the exposed phosphorus-doped oxide film 104 to form the structure shown in FIG.

Thereafter, as shown in FIG. 2 (f), the non-doped polysilicon film 106, the phosphorus-doped oxide film 104, and the non-doped oxide film 103 are etched to perform boron ion implantation for source / drain formation and impurity activation. Heat treatment to form a P-type gate electrode 105, a P-type source / drain region 1
02, 102 'are formed to form the P-channel insulated gate field effect transistor shown in FIG.

〔The invention's effect〕

As described above, by adopting the structure as in the present invention, phosphorus and boron can coexist, and the phenomenon of boron penetration can be suppressed. Further, since an insulating film to which phosphorus is added can be formed in part of the gate insulating film, mobile ions can be immobilized by a gettering effect of the film.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a P-channel insulated gate field effect transistor which is one embodiment of the insulated gate field effect transistor of the present invention. FIGS. 2 (a) to (f) are shown in FIG. FIG. 3 is a schematic sectional view showing a manufacturing process of a P-channel insulated gate field-effect transistor. FIG. 3 is a schematic sectional view of a P-channel insulated gate field-effect transistor according to the prior art. 101 N-type silicon substrate 102, 102 'source-drain region 103 non-doped oxide film 104 phosphorus-doped oxide film 105 P-type gate electrode 106 non-doped polysilicon film 110 phosphorus-doped polysilicon film

Claims (2)

(57) [Claims] In a P-channel type insulated gate field effect transistor using a P-type gate electrode, a gate insulating film has a two-layer structure of an insulating film to which phosphorus is added and an insulating film to which no impurity is added. An insulated gate field effect transistor, characterized in that: 2. A method of manufacturing a P-channel type insulated gate field effect transistor using a P-type gate electrode, comprising: forming a first insulating film to which no impurity is added on a substrate; A method for manufacturing an insulated gate field effect transistor, comprising: forming a second insulating film to which phosphorus is added on an insulating film; and forming a P-type gate electrode on the second insulating film. Method.