JPS61287160A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a process by implanting ions for source-drain on the P channel MOS transistor side in a self-alignment manner by utilizing a thermal oxide film formed when shaping source-drain on the N channel MOS transistor side. CONSTITUTION:The ions of As 16 are implanted in high dose in order to form source-drain to a P well layer 12, and the N well layer 14 side is covered with a resist 18 at that time. N<+> layers 17 are shaped in the P well layer 12 through heat treatment by N2 gas, and the N<+> layers 17 function as source-drain in an N channel MOS transistor. Since As 16 is doped onto an active region in the P well layer 12 in high concentration, a thick oxide film 20 is formed. Boron 22 is implanted to the whole surface in order to shape the N well layer 14 while employing the thick oxide film 20 as a mask, thus enabling self- alignment.

Description

Detailed Description of the Invention (Field of Industrial Application) This invention is directed to implanting ions into the source/drain on the P-MOS side of a complementary MOS into an oxide film formed by heat treatment during the formation of the source/drain into the P-well layer. The present invention relates to a method for manufacturing a MOS type semiconductor device in which the process can be simplified by using a self-alignment line.

(Prior art) The conventional technology uses complementary MOS, as shown in Figure 2.
N channel MOS 4 and P channel M on the same board
Since the OS5 is configured, in order to form the source φ drains 2 and 3, A (N-type impurity) is implanted on the N-channel MOSJ side, and the P-channel M
Boron (P-type impurity) is implanted on the OSS side using implantation technology.

However, since the impurities are different, they cannot be formed at the same time, and one of the MOS sides is protected with a resist 6 using photolithography and used as a mask during implantation.

(Problem to be solved by the invention) However, according to the method described above, the P-channel MOS
K, who performs implantation on the S side, covers the N channel MOS 4 side with Renostro.
There is a problem in that the number of photolithography steps is increased and the semiconductor device manufacturing period is extended, resulting in a drop in yield.

This invention solves the problems of the above-mentioned prior art.
The present invention provides a method for manufacturing a MOS semiconductor device that solves the problems of increasing the number of photolithography steps, requiring a long manufacturing period, and reducing yield.

(Means for Solving the Problems) This invention is a method for manufacturing a %MO5ffi semiconductor device, in which the ion implantation work on the %N channel MOS side is performed by increasing the thickness of the annealed film and utilizing it. This method introduces a process that involves

(Function) This invention introduces the above-mentioned steps into the method of manufacturing a MOS type semiconductor device, so when forming the source/drain layer of a P channel/channel MOS@ by ion implantation, the KN channel MOSN A y# oxide film is formed by heat treatment during source/drain formation, and ion implantation of an N-channel MOS@ is performed using this oxide film.

(Example) Hereinafter, an example of the method for manufacturing a MOS type semiconductor device of the present invention will be described based on the drawings. FIGS. 1(a) to 1(6) are process explanatory diagrams of one embodiment, and are cross-sectional structural diagrams of an embodiment of the complementary FF11MOS.

First, as shown in FIG. 1(a), a P well fi12 is formed on a needle substrate ll as a semiconductor substrate, with a hole 7 and a hole t7.
ft concentration 1.5XI O" ~ 2 X 10""0
! n/ajt' is implanted to a depth of approximately 4 μm.

Then, using the LOGO8 process, field oxidation a
13 to about 7000A type a and P91-le ff1l 2
After that, the N-well layer 14 is irradiated with phosphorus ions at 1@
It is formed at a depth of approximately 2 μm with an atom concentration of 1×10 to 3×10 /−.

Next, poly-5it-p is grown by KCVD on the entire surface, and poly-81 resistance is adjusted to 25 to 30 Ω/hole by phosphorus diffusion. Next, r-)poly-8i was formed on the P-well r@12 and N-well #11D active areas using photolithography.
form 15. Note that 30 and 40 are channel stoppers, respectively.

Thereafter, as shown in FIG. 1(b), in order to form a source/drain in the %P well 612, ion implantation of AB16 is performed at a high dose.

In this case, the accelerating voltage is 40-60KV% and the concentration is lX10
1s~1.5×l1016atO/aIte.

At this time, the N-well r@14 side is covered with a resist 18 using photolithography. Resost 18 has a thickness of 90
00-120001.

Next, as the first annealing condition, N2 gas (atmosphere 9
00-1000° C.) for about 100 minutes to form N''l'i#17 in the %P well ff112.

This N layer 17 is a region that becomes the source and drain of the N channel MOS transistor.

When forming this N'' * 17, as shown in Fig. 1(c) K
As shown, the active region of the P-well 1112 is doped with Ag2S at a high concentration, as described above, and therefore has a thick oxidation of more than 700A! [20 (5to2) is formed.

Next, using this thick oxide film 20 as a mask, implantation of &ron 22 is performed on the entire surface of the N-well layer 14 using an accelerated electric current EE4 as shown in FIG. 1(d).
0~70KV, dark [lX101s~1.5XIO1s&
Go to t0m/cd.

In this way, self-alignment can be achieved by implanting the Poron 22 ions over the entire surface.

This eliminates the work of covering the LP well 912 with resist, simplifies the process, reduces processing time in the semiconductor device manufacturing process, and can be expected to improve yield.

After the ion implantation of Poron 22, the second annealing process was performed at approximately 950°C in a 02 gas atmosphere at 20~4°C.
A heat treatment is performed for 0 minutes to form a thin oxide film (SIO, ) 21 (FIG. 1(C), FIG. 1(t5)) of about 250A.

In this way, a thick oxide film 20 is formed on the N-channel MOS transistor side, and a thin oxide film 21 is formed on the P-channel MOS transistor side, but since impurities are implanted and the oxidation rate of the substrate surface becomes faster. , N-channel and P-channel MOS) There is a difference in the thickness of the oxide film on the transistor side.

Thereafter, as shown in FIG. 1(e), D
A P8G intermediate insulating film 23 with a thickness of about 7000A is formed.

Thereafter, flattening is performed and a PSG flow is performed. The conditions at this time are dry 03, gas temperature of about 900℃, and about 5
min, weight 02 in gas at a temperature of about 900°C, about 15
minutes, dry 0. The temperature is about 900°C in gas for about 20 minutes.

At the same time as performing this PSG flow, %P channel MOS
) The source and drain on the Lanzoster side are simultaneously diffused and formed.

Hereinafter, the intermediate insulating film 23 of the PSG will serve as an intermediate isolation lIk film when forming a two-layer wiring layer.

(Effects of the Invention) As described above in detail, the present invention provides a P-channel MMOS transistor using a heat removal film formed when forming the source/drain on the transistor side.
Since the ion implantation of the source and drain on the OS) transistor side can be performed in self-alignment, the diffusion photolithography process for P-channel MOS) transistors can be eliminated, simplifying the process and improving yield. You can expect it.

[Brief explanation of drawings]

FIG. 1 (1 to 1(e) is a process explanatory diagram of an embodiment of the method for manufacturing a MOS type semiconductor device of the present invention, and FIG. 2 is for explaining a method for manufacturing a conventional complementary MOS) runnostar. This is a diagram. 11.-N daughter board, 12...P well lit, 13.
...Field oxide film, 14...Nwael 7i! 1.
15...r-Toboly Si, 16...A8%
17...N11i, 18...Resist, 20...
Thick oxide film, 21...Thin oxide film, 23...Intermediate insulating film%30.40...Channel stopper. fPFF applicant Oki Electric Industry Co., Ltd.'s 1i!
Diagnostic blindness 2 Diagram 2

Claims (1)

[Claims] (a) A step of forming a P-well layer on a semiconductor substrate and separating this P-well layer with a field oxide film, and then forming an N-well layer; (b) forming an N-well layer between the P-well layer and the N-well layer; (c) forming a gate poly-Si on the active region of the well layer; (c) covering the N-well layer with photoresist;
By performing ion implantation into the well layer and heat treatment, N
(d) ion implantation into the N-well layer using the thick oxide film as a mask in a self-aligned manner; a step of forming a source/drain of a P-channel MOS transistor by applying heat treatment to the P-channel MOS transistor;
A method for manufacturing an OS type semiconductor device.