JPH04260331A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a collector.base.emitter in a self-alignment manner, and enable the connection of a base leading-out electrode and an inner base, by using a photo mask and performing oblique incidence ion implantation. CONSTITUTION:Impurity ions 8 of a conductivity type are obliquely projected in an aperture 6, from the direction of a collector contact electrode 4B by ion implantation method. Thereby an inner base 9 is formed in a semiconductor substrate 1 on the base contact electrode 4A side of the aperture 6. The inside of the aperture 6 is coated with a second insulating film 10, and a side wall insulating film 10A is formed on the side wall of the aperture 6 by anisotropic etching. A second poly Si film 11 is buried in the aperture 6 and turned into an emitter contact electrode 11A. By heat-treating the semiconductor substrate 1, impurities are diffused from a poly Si film 4, and a collector contact diffusion layer 14 isolated from an emitter 12, an outer base 13 and an inner base 9 is formed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bipolar LSI.

In recent years, there has been a demand for higher integration and higher speed for ICs, and for this reason, it has become necessary to reduce the area of elements such as transistors constituting the IC and to reduce the parasitic capacitance of the transistors.

0003

2. Description of the Related Art FIG. 5 is an explanatory diagram of a conventional example. In the figure, 40 is a semiconductor substrate, 41 is a buried diffusion layer, 42 is an epitaxial layer, 43 is a field SiO2 film,
44 is an element isolation layer, 45 is a base contact electrode,
46 is a collector contact electrode, 47 is a cover SiO
2, 48 is a sidewall SiO2 film, 49 is an emitter contact electrode, 50 is an emitter, 51 is an internal base, 52 is an external base, 53 is a collector contact electrode, and 54 is an Al electrode.

In the conventional bipolar LSI, as shown in FIG.
As shown in Figure 3, since the collector and base/emitter regions were formed in separate areas on the semiconductor substrate, allowance for alignment using masks had to be taken into account, which increased the size of the transistor. , the capacitance between the collector and the semiconductor substrate also increased.

[0005]

[Problems to be Solved by the Invention] Therefore, there has been a problem in that progress toward higher integration and higher speeds has been hindered. In view of the above-mentioned problems, the present invention is provided for the purpose of providing a method that contributes to higher integration and higher speed of bipolar transistors.

[0006]

[Means for Solving the Problems] FIG. 1 is an explanatory diagram of the principle of the present invention, and FIG. 4 is a schematic diagram of the second and third embodiments of the present invention.

In the figure, 1 is a semiconductor substrate, 2 is a field insulating film, 3 is a well, and 4 is a first polycrystalline silicon (
4A is a base contact electrode, 4B is a collector contact electrode, 5 is a first insulating film, 6 is an opening, 7 is a through insulating film, 8 is an impurity ion, 9 is an internal base, 10A is a sidewall Insulating film, 11A
is an emitter contact electrode, 12 is an emitter, 13
is an external base, 14 is a collector contact diffusion layer,
15 is an aluminum (Al) electrode, 36 is a collector buried diffusion layer, 37 is an epitaxial layer, 38 is an element isolation layer, and 39 is a high melting point metal silicide film.

The above problem can be solved by forming the emitter, base, and collector in a self-aligned manner using only one photomask. That is, the object of the present invention is to form a field insulating film 2 as shown in FIG. 1(a).
As shown in FIG. 1(b), a step of forming a well 3 of an opposite conductivity type in a semiconductor substrate 1 of one conductivity type divided by and introducing impurities of one conductivity type into the region where the base contact electrode 4A is to be formed and impurities of the opposite conductivity type into the region where the collector contact electrode 4B is to be formed. A step of forming an insulating film 5 on the semiconductor substrate 1 to cover the poly-Si film 4, and a step of sequentially opening the insulating film 5 and the poly-Si film 4 to form an opening 6 for forming a base. , Impurity ions 8 of one conductivity type are obliquely injected into the opening 6 from the direction of the collector contact electrode 4B by ion implantation, and the base contact electrode 4A of the opening 6 is formed.
forming an internal base 9 in the side semiconductor substrate 1;
As shown in FIG. 1(d), a step of covering the inside of the opening 6 with a second insulating film 10 and forming a sidewall insulating film 10A on the side wall of the opening 6 by anisotropic etching; A second poly-Si film 11 is buried in the opening 6 to form an emitter contact electrode 11A, and the semiconductor substrate 1 is heat-treated to diffuse impurities from the poly-Si film 4 to form the emitter 12 and the external base 13. , and a collector contact diffusion layer 14 spaced apart from the internal base 9.
Alternatively, as shown in Figure 4,
Instead of forming the well 3 of the opposite conductivity type in the semiconductor substrate 1, a collector buried diffusion layer 36 of the opposite conductivity type is formed on the semiconductor substrate 1, and an epitaxial layer of the opposite conductivity type is formed on the semiconductor substrate 1. Form 37, and then,
This is achieved by forming an element isolation layer 38 of one conductivity type impurity in the element isolation region, and further by laminating a high melting point metal silicide film 39 subsequent to the coating of the first polycrystalline silicon film 4. .

[0009]

According to the present invention, the collector, base, and emitter can be formed in a self-aligned manner by using one photomask and performing oblique incidence ion implantation.

Furthermore, depending on the ion implantation angle of the base, the base extraction electrode and the internal base can be connected in a self-aligned manner.

[0011]

Embodiments FIGS. 2 and 3 are schematic cross-sectional views in the order of steps of a first embodiment of the present invention, and FIG. 4 is a schematic structural diagram of second and third embodiments of the present invention.

In the figure, 16 is a Si substrate, 17 is a field SiO2 film, 18 is an n-well, 19 is a first poly-Si film, 20 is a first photoresist film, 21 is a B+ film, and 22 is a second photoresist film. Resist film, 23 is P+
, 24 is the first SiO2 film, 25 is the first opening, 2
6 is a through SiO2 film, 27 is B+, 28 is an internal base, 29 is a second SiO2 film, 30 is a second poly-Si film, 31 is an emitter, 32 is an external base, 33
is a collector contact diffusion layer, 34 is a second opening,
35 is an Al electrode.

As shown in FIG. 2(a), a silicon nitride film (not shown) is placed on a p-type Si substrate 16 as a mask.
A field SiO2 film 17 with a thickness of 6,000 Å is formed in the element isolation region by selective oxidation.

[0014] Next, phosphorus ions (P+) were implanted into the activated region at an accelerating voltage of 100 k.
eV and a dose of 5 x 1013/cm2, and activation annealing was performed at 1,100 °C for 60 minutes.
A well 18 is formed.

As shown in FIG. 2(b), a first poly-Si film 19 is deposited on the Si substrate 16 in a thickness of 3.0% using the CVD method.
Coat to a thickness of 0.00 Å and pattern. Figure 2(c)
), boron ions (B+) are implanted into the first poly-Si film 19 using the first photoresist film 20 as a mask at an acceleration voltage of 30 keV and an ion implantation method.
The base contact electrode 19A is formed by implanting at a dose of 1.times.10.sup.15/cm.sup.2. form 18.

As shown in FIG. 2(d), the first polySi
Arsenic ions (As + ) are injected into the film 19 by ion implantation using the second photoresist film 22 as a mask.
Accelerating voltage 100keV, dose 1x1015/
cm2, and the collector contact electrode 19
Form B.

As shown in FIG. 2(e), a first SiO2 film 24 is deposited on the S substrate 16 with a film thickness of 5,000 nm by CVD.
Coat to a thickness of 0 Å. As shown in FIG. 2(f), the first SiO2 film 24 and the first poly-Si film 19 are sequentially opened to form a first opening 25 for forming a base.

As shown in FIG. 2(g), the first opening 2
The through SiO2 film 26 is oxidized at 850°C in the
Coat to a thickness of 00 Å. As shown in FIG. 2(h), B + 27 is implanted into the first opening 25 from the direction of the collector contact electrode 19B at an angle of 80° at an acceleration voltage of 10 keV and a dose of 3 x 1013/cm2. The internal base 28 is formed in the Si substrate 16 on the side of the base contact electrode 19A of the first opening 25.

As shown in FIG. 3(i), a second SiO2 film 29 is deposited on the Si substrate 16 using the CVD method.
Coat to a thickness of 0 Å. As shown in Figure 3(j), RI
By anisotropic etching with E, the second SiO2
The film 29 is dry etched to form a sidewall insulating film 29A on the sidewall of the first opening 25.

As shown in FIG. 3(k), a second poly-Si film 30 is deposited on the Si substrate 16 using a CVD method.
Coat to a thickness of 0.00 Å. As shown in Figure 3(l),
The second poly-Si film 30 is patterned to fill the first opening 25 and form an emitter contact electrode 30A.

As shown in FIG. 3(m), As+ was implanted into the emitter contact electrode 30A using an ion implantation method at an acceleration voltage of 40 keV and a dose of 1 x 1016/cm2, and activated at 1,100°C for 30 seconds. The emitter 31 and the external base 32 are annealed.
, forming a collector contact diffusion layer 33.

As shown in FIG. 3(n), the first SiO2
A second opening 34 for electrode connection is opened in the membrane. Figure 3 (
As shown in o), an Al film is coated on the Si substrate 16 to a thickness of 1 μm by sputtering and patterned to form Al electrodes 35 on the emitter, base, and collector, respectively, to complete the bipolar transistor. .

As a second embodiment, as shown in FIG. 4, instead of forming the well 3 of the opposite conductivity type in the semiconductor substrate 1, a collector buried diffusion layer of the opposite conductivity type is formed on the semiconductor substrate 1. 15 is formed, then an epitaxial layer 16 of the opposite conductivity type is formed on the semiconductor substrate 1, and then an element isolation layer 17 of one conductivity type impurity is formed in the element isolation region.

Further, as a third embodiment, as shown in FIG. 4, a high melting point metal silicide film 18 may be laminated subsequent to the coating with the first poly-Si film 4.

[0025]

[Effects of the Invention] As explained above, according to the present invention, the collector, base, and emitter can be formed by self-alignment by using one photomask and the oblique incidence ion implantation method. Depending on the implantation angle, it is possible to connect the base extraction electrode and the internal base in a self-aligned manner, which greatly contributes to higher integration and higher speed of bipolar LSIs.

[Brief explanation of the drawing]

[Figure 1] Diagram explaining the principle of the present invention

[Fig. 2] Schematic sectional view of the process order of the first embodiment of the present invention (Part 1)

[Fig. 3] Schematic cross-sectional view of the process order of the first embodiment of the present invention (Part 2)

[Figure 4] Schematic configuration diagram of second and third embodiments of the present invention

[Figure 5] Explanatory diagram of conventional example

[Explanation of symbols]

1 Semiconductor substrate 2 Field insulation film 3 Well 4 Poly-Si film 4A base contact electrode 4B Collector contact electrode 5 First insulating film 6 Opening 7 Through insulation film 8 Impurity ions 9 Internal base 10A sidewall insulation film 11A emitter contact electrode 12 Emitter 13 External base 14 Collector contact diffusion layer 15 Al electrode 16 Si substrate 17 Field SiO2 film 18 n-well 19 First poly-Si film 20 First photoresist film 21 B+ 22 Second photoresist film 23 P+ 24 First SiO2 film 25 First opening 26 Through SiO2 film 27 B+ 28 Internal base 29 Second SiO2 film 30 Second poly-Si film 31 Emitter 32 External base 33 Collector contact diffusion layer 34 Second opening 35 Al electrode. 36 Collector buried diffusion layer 37 Epitaxial layer 38 Element isolation layer 39 High melting point metal silicide film

Claims (3)

[Claims] 1. A step of forming a well (3) of an opposite conductivity type in a semiconductor substrate (1) of one conductivity type partitioned by a field insulating film (2),
) is coated with a first polycrystalline silicon film (4), and patterned to inject impurities of one conductivity type into the region where the base contact electrode (4A) is planned to be formed, and the impurity of one conductivity type into the region where the collector contact electrode (4B) is planned to be formed. a step of introducing impurities of each conductivity type, and a step of introducing impurities of each conductivity type into the semiconductor substrate (1);
The first insulating film (
5) a step of sequentially opening the first insulating film (5) and the first polycrystalline silicon film (4) to form an opening (6) for forming a base; Impurity ions (of one conductivity type) are implanted into the opening (6) from the direction of the collector contact electrode (4B) by ion implantation
8) forming an internal base (9) in the semiconductor substrate (1) on the base contact electrode (4A) side of the opening (6) by obliquely injecting the internal base (9) into the opening (6); A sidewall insulating film (10) is formed on the side wall of the opening (6) by anisotropic etching.
10A), embedding a second polycrystalline silicon film (11) in the opening (6) to form an emitter contact electrode (11A), and heat-treating the semiconductor substrate (1). , impurities are diffused from the first polycrystalline silicon film (4) to form an emitter (12),
A method of manufacturing a semiconductor device, comprising the step of forming an external base (13) and a collector contact diffusion layer (14) spaced apart from the internal base (9). 2. Instead of forming a well (3) of an opposite conductivity type in the semiconductor substrate (1), a collector buried diffusion layer (36) of an opposite conductivity type is formed on the semiconductor substrate (1).
), forming an epitaxial layer (37) of opposite conductivity type on the semiconductor substrate (1), and then forming an element isolation layer (38) of one conductivity type impurity in the element isolation region. 2. The method of manufacturing a semiconductor device according to claim 1. 3. The first polycrystalline silicon film (4)
2. The method of manufacturing a semiconductor device according to claim 1, further comprising laminating a high melting point metal silicide film (39) subsequent to the coating.