JPH05235029A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently lower the resistance of a source layer and a drain layer in the gate length direction by a resistance lowering film for restraining the pattern formation of the resistance lowering layer as well as insulating the source layer, a drain layer and a gate electrode without fail in relation to the title manufacturing method of semiconductor device having resistance lowering structure for MIS transistor diffusion layer. CONSTITUTION:The title manufacturing method of semiconductor device is composed of the three steps enumerated as follows i.e., the first step forming the gate electrode 7 of a MIS transistor wherein the upper part and the side part of the electrodes 7 are covered with insulating films 5, 8 on a semiconductor layer 1 through the inter intermediary of an insulating film 3, the second step introducing impurities in the semiconductor layer 1 on both sides of the gate electrode 7 so as to form source layer 9s and a drain layer 9d of a MIS transistor and the third step selectively growing a slilicide film (conductive tungsten film) 10 on the source layer 9s and the drain layer 9d by selective vapor deposition process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a MIS (Metal Insulator Semic).
The present invention relates to a method for manufacturing a semiconductor device having a structure in which a diffusion layer of a transistor has a low resistance.

In recent years, with the miniaturization of elements, the diffusion layer is becoming shallower, but the resistance in the surface direction increases, so that it is necessary to reduce the resistance by a metal silicide technique or the like.

[0003]

2. Description of the Related Art MIS transistors are shown in FIGS.
As illustrated in (a), the insulating film 3 is formed on the semiconductor substrate 31.
And a semiconductor substrate 3 on both sides of the gate electrode 33 made of a polycrystalline silicon film
1 has a source layer 34 and a drain layer 35 formed by introducing impurities. Reference numeral 36 in the figure denotes a selective oxide film for element isolation formed on the surface of the semiconductor substrate 31,
Reference numeral 37 denotes an insulating side wall formed on the side wall of the gate electrode 33.

With the shrinking of the MIS transistor, the source layer 34 and the drain layer 35 are made shallow as one measure against the short channel effect. As these layers become shallower, the gate length direction becomes smaller. There is an inconvenience that the resistance of is increased.

Therefore, the source layer 34 and the drain layer 35
A silicide film of titanium silicide, tungsten silicide, or the like is formed on the surface of, to reduce the resistance of these layers.

Next, the step of forming titanium silicide on the surfaces of the source layer and the drain layer will be described with reference to FIG. First, as shown in FIG. 3 (a), MI of the above structure is
An S-transistor is formed on the semiconductor substrate 31, and then titanium 3 is formed on the entire surface by sputtering as shown in FIG.
When 8 are stacked and heated, the titanium 38 on the surfaces of the source layer 34 and the drain layer 35 is silicidized to form a titanium silicide (TiSi) layer 38a.

Then, as shown in FIG. 3 (c), titanium 38 on the selective oxide film 36 and the insulating sidewall 37 is formed.
Are selectively removed by a mixed solution of hydrogen peroxide and ammonium hydroxide to separate the gate electrode 33 from the source layer 34 and the drain layer 35.

Thereafter, as shown in FIG. 3D, an interlayer insulating film 39 is formed, and then the interlayer insulating film 39 is patterned by photolithography to form the source layer 34.
Contact hole 34 in each of the drain and drain layers 35
a and 35a are formed and electrode wiring 40 passing therethrough is formed.
a and 40b are formed.

Next, the step of forming tungsten silicide on the surfaces of the source layer and the drain layer will be described with reference to FIG. First, as shown in FIG. 4A, the MIS transistor having the above structure is formed on the semiconductor substrate 31, and then, as shown in FIG. 4B, selective vapor deposition (selective CV
The tungsten silicide (WSi) layer 41 is selectively grown on the surfaces of the gate electrode 33, the source layer 34 and the drain layer 35 by the method D).

Thereafter, as shown in FIG. 4D, an interlayer insulating film 42 is formed, and the interlayer insulating film 42 is patterned by photolithography to make contact with the source layer 34 and the drain layer 35, respectively. Hall 34
b, 35b, and electrode wirings 43, 44 passing therethrough
To form.

[0011]

However, according to the former method, the shallowly formed source layer 34 and drain layer 35 are formed.
If titanium 38 is thickly laminated on the above, there is a disadvantage that a spike is generated by the TiSi layer 38a and a junction leak occurs. For this reason, the TiSi layer 38a cannot be made thick, and the reduction in resistance becomes insufficient.

On the other hand, according to the latter method, spikes are less likely to occur and the WSi 41 can be made thicker.
If the WSi layer 41 becomes thicker, the source layer 34 and the drain layer 3
The WSi layer 41 on the gate electrode 33 and the WSi layer 41 on the gate electrode 33 are close to each other, and dielectric breakdown is likely to occur, and as shown in FIG.

Further, if the film thickness is increased, the WSi layer 41 is likely to collapse on the gate electrode 33, and the pattern is likely to be deformed. The present invention has been made in view of such problems, and includes a source layer,
A semiconductor in which the resistance in the gate length direction of the drain layer is sufficiently reduced by the resistance-reducing film, pattern deformation of the resistance-reducing layer is suppressed, and the source layer, the drain layer and the gate electrode can be reliably insulated. An object is to provide a method for manufacturing a device.

[0014]

[Means for Solving the Problems]
2, a step of forming the gate electrode 5 of the MIS transistor whose upper and side portions are covered with the insulating films 5 and 8 on the semiconductor layer 1 via the insulating film 3, and the gate electrode 5 By introducing impurities into the semiconductor layer 1 on both sides of
First impurity layer 9s and second impurity layer 9 of the IS transistor
the step of forming d and the first vapor deposition method
A conductive film 10 is formed on the impurity layer 9s and the second impurity layer 9d.
And a step of selectively growing the semiconductor device.

Alternatively, the height of the conductive film 10 grown by the selective vapor deposition method is substantially the same as that of the gate electrode 7, which is achieved by a method of manufacturing a semiconductor device.

[0016]

According to the present invention, the conductive film 10 is selectively grown on the first impurity layer 9a and the second impurity layer 9d with the gate electrode 7 of the MIS transistor covered with the insulating films 5 and 8. It is not formed on the gate electrode 7.

Therefore, when the conductive film 10 is selectively grown and separated from each other, a short circuit accident of the gate electrode 7, the first impurity layer 9s, and the second impurity layer 9d and a decrease in withstand voltage can be prevented.

Moreover, since the conductive film 10 selectively grown does not need to consider the junction leak, there is no problem even if the film thickness is increased, and the first impurity layer 9s and the second impurity layer 9d are not affected. The resistance in the gate length direction is sufficiently reduced.

Further, the conductive film 10 is not formed on the protruding gate electrode 7, the shape is not collapsed by the selective CVD method, and the deformation of the pattern is suppressed. Further, according to the present invention, since the conductive film 10 that is selectively grown is grown to almost the same height as the gate electrode 7, the first impurity layer 9s is formed.
Also, the interlayer insulating film formed on the second impurity layer 9d is thinned and flattened, and the contact hole formed there is shallow, so that the step coverage is improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment of the Present Invention FIGS. 1 and 2 are sectional views showing an embodiment of the present invention.

In the figure, reference numeral 1 is a p-type semiconductor substrate made of silicon or the like, and an oxide film 2 for element isolation is formed on the surface thereof.
Are formed by a selective oxidation method, and a thin SiO ₂ film 3 of about 100 to 200 Å is formed in the active region surrounded by the oxide film 2.

In such a state, first, as shown in FIG.
, A polycrystalline silicon film 4 is grown on the entire surface by, for example, 3000 to 4000 Å by the CVD method, and further, Si
The O ₂ film 5 is grown by 1000Å, for example.

Then, a photoresist is applied and exposed and developed to form a resist mask 6 covering the gate region. Next, the SiO ₂ film 5 and the polycrystalline silicon film 4 in the region not covered with the mask 6 are subjected to reactive ion etching (R
The polycrystalline silicon film 4 left under the mask 6 is continuously etched by the (IE) method, and thus the polycrystalline silicon film 4 left under the mask 6 is subjected to MOS (Metal).
Oxide Semiconductor) The gate electrode 7 of the transistor (FIG. 1 (b)).

Further, as shown in FIG. 1C, after removing the resist mask 6 with a solvent, the semiconductor substrate 1 on both sides of the gate electrode 7 is masked with the gate electrode 7 and the element isolation oxide film 2, for example. Impurities such as phosphorus and arsenic are shallowly ion-implanted. The dose is 1 × 10 ¹³ pieces / cm
^{At 2} , the acceleration energy is set to 60 keV.

Then, a total film thickness of 400 is formed by the CVD method.
A SiO ₂ film 8a having a thickness of about 0Å is laminated and anisotropically etched in the vertical direction by the RIE method to leave the SiO ₂ film 8a on both sides of the gate electrode 7 as the insulating sidewall 8 ( Figure 1 (d)).

Further, the sidewall 8 and the gate electrode 7
Also, using the element isolation oxide film 2 as a mask, impurities are deeply ion-implanted into the semiconductor substrate 1 on both sides of the gate electrode 7 (FIG. 2 (e)). The dose amount at the time of ion implantation is 5 × 10 ¹⁵ ions / cm ² , and the acceleration energy is 60 keV.

At this stage, the semiconductor substrate 1 is subjected to heat treatment.
The impurities introduced into the gate electrode 7 are activated, and the impurity diffusion layers formed on both sides of the gate electrode 7 are used as the source layer 9s and the drain layer 9d of the MOS transistor (FIG. 2 (f)). In this case, the source layer 9s and the drain layer 9d have an LDD structure.

After this, the source layer 9s and the drain layer 9d
After removing the SiO ₂ film 2 on the surface with hydrofluoric acid, as shown in FIG. 2 (g), tungsten containing silicon (W or WSi) is formed by a CVD method using a gas containing WF ₆ and SiH _4.
x ) the film 10 on the source layer 9a and the drain layer 9d
Selectively grow to a thickness of about 000 to 5000Å. Next, the interlayer insulating film 11 is formed of SiO ₂ , PSG or the like by the CVD method, and subsequently, the SiO ₂ film 2 on the gate electrode 7 and the interlayer insulating film 11 are patterned by the photolithography method to form the gate. Contact holes 12g, 12s, on the electrode 7, the source layer 9s and the drain layer 9d,
12d is formed. Further, a polycrystalline silicon film is formed and patterned, and as shown in FIG. 2 (h),
A gate lead electrode 13g, a source electrode 13s, and a drain electrode 13d that pass through the contact holes 12g, 12s, and 12d are formed.

As described above, since the tungsten film 10 is grown by the selective CVD method while the gate electrode 7 made of polycrystalline silicon is covered with the SiO ₂ film 5, the tungsten film 10 is grown on the source layer 9s and the drain layer 9d. The tungsten film 10 is deposited only on the gate electrode 7, and is not formed on the gate electrode 7.

Therefore, when the tungsten film 10 is selectively grown and mutually separated, the gate electrode 7 and the source layer 9 are formed.
of the tungsten film 10 that has been selectively grown.
According to this, since it is not necessary to consider the junction leak, there is a problem even if the silicide is grown to the same height as the gate electrode 7.

As a result, the source layer 9s and the drain layer 9d
The resistance in the gate length direction is sufficiently reduced, and the interlayer insulating film 11 formed on these layers is thinned and flattened.
2d becomes shallower and the step coverage is improved.

Further, the tungsten film 10 is not formed on the projecting gate electrode 7, the shape collapse due to the selective CVD method does not occur, and the pattern deformation is suppressed. (B) Description of Other Embodiments of the Present Invention In the above embodiments, the semiconductor substrate 1 was p-type and the source / drain layers 9s and 9d were n-type, but the polarities may be opposite.

Although the above-described device is formed on the semiconductor substrate 1, it can be similarly applied to the case where it is formed on a semiconductor layer such as an SOI substrate. Further, although tungsten silicide is selectively grown on the source layer 9s and the drain layer 9d in the above-described embodiment, the material may be a conductive film.

Although the MOS transistor has been described in the above embodiments, the gate insulating film is not limited to SiO ₂ and may be Si ₃ N ₄ or SiON, and the same can be applied to the MIS transistor.

When the conductive film is selectively grown, the lower layer connected to the conductive film is not limited to the source and drain of the transistor.

[0036]

As described above, according to the present invention, MI
With the gate electrode of the S transistor covered with an insulating film,
Since the conductive film is selectively grown on the first impurity layer and the second impurity layer and is not formed on the gate electrode, when the conductive film is selectively grown and separated from each other, It is possible to prevent a short circuit accident of the impurity layer and the second impurity layer and a decrease in withstand voltage.

Moreover, since the conductive film that has been selectively grown does not need to consider the junction leak, there is no problem even if the film thickness is increased, and the gate lengths of the first impurity layer and the second impurity layer are not affected. The resistance in the direction can be sufficiently reduced.

Further, the conductive film is not formed on the protruding gate electrode, the shape is not collapsed by the selective CVD method, and the pattern deformation can be suppressed. Further, according to the present invention, since the conductive film is grown to almost the same height as the gate electrode, the interlayer insulating film formed on the first impurity layer and the second impurity layer is thinned and flattened. The contact hole formed therein can be shallowed to improve the step coverage.

[Brief description of drawings]

FIG. 1 is a sectional view (1) showing an embodiment of the present invention.

FIG. 2 is a sectional view (2) showing an embodiment of the present invention.

FIG. 3 is a sectional view showing a first example of a conventional method.

FIG. 4 is a sectional view showing a second example of a conventional method.

[Explanation of symbols]

1 semiconductor substrate (semiconductor layer) 2 oxide film 3 SiO ₂ film (insulating film) 4 polycrystalline silicon film 5 SiO ₂ film (insulating film) 6 resist mask 7 gate electrode 8 sidewall 8 a SiO ₂ film (insulating film) 9s source Layer (first impurity layer) 9d Drain layer (second impurity layer) 10 Tungsten film (conductive film) 11 Interlayer insulating film 12s, 12d, 12g Contact hole 13s, 13d, 13g Lead electrode

Claims (2)

[Claims] 1. A step of forming a gate electrode (5) of a MIS transistor whose upper and side portions are covered with an insulating film (5, 8) on a semiconductor layer (1) through an insulating film (3). An impurity is introduced into the semiconductor layer (1) on both sides of the gate electrode (5) to form a first impurity layer (9) of the MIS transistor.
s), a step of forming the second impurity layer (9d), and a conductive film (10) is selectively formed on the first impurity layer (9s) and the second impurity layer (9d) by a selective vapor deposition method. And a step of growing into a semiconductor device. 2. The manufacturing of a semiconductor device according to claim 1, wherein the height of the conductive film (10) grown by the selective vapor deposition method is substantially the same as that of the gate electrode (7). Method.