JPH0773127B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device.

[Prior art and its problems]

Since the 1970s, the trend toward higher integration of semiconductor devices has been increasing, and progress has been made to ultra-large scale integrated circuits (VLSI), where millions or more elements can be integrated on one semiconductor chip. I've been to

By the way, high integration of integrated circuits is realized by miniaturization of elements. With the miniaturization and high integration of elements, the wiring tends to be thin and thin, and the wiring length tends to be long. on the other hand,
The PN junction is also formed to have a shallow depth, and the contact area for making electrical connection between the gate electrode, the source diffusion layer, the drain diffusion layer, etc. and the metal wiring layer tends to be reduced. Resistance is getting higher. Such an increase in wiring resistance is a major obstacle to speeding up integrated circuits.

Therefore, recently, a method of lowering the wiring resistance by selectively forming a low-resistance metal film on the gate electrode or the source / drain diffusion layer by a vapor phase growth method has been attempted.

As an example of this, an attempt has been made to selectively form a tungsten (W) film on the source / drain and gate electrodes by a vapor phase growth method using, for example, tungsten hexafluoride (WF ₆ ) gas.

In this method, for example, first, as shown in FIG.
After forming a field oxide film 52 on a P-type silicon substrate 51, a high-concentration phosphorus-doped polycrystalline silicon film is formed through the gate oxide film 53 and patterned to form a gate electrode 54, and the gate electrode 54 is formed. With the field oxide film as a mask and the acceleration voltage of 40 keV, the implantation amount is 1 × 10 ¹⁴ /
Phosphorus ions (P ⁺ ) are ion-implanted at cm ² to form shallow n ⁻ diffusion layers 55a and 55b in the source / drain regions.

Next, as shown in FIG. 3B, a silicon oxide film (insulating film) 56 having a thickness of 0.3 μm is deposited on the entire surface of the substrate by the CVD method.

Further, it is anisotropically etched only in the vertical direction by reactive ion etching using a Freon-based gas to leave only the silicon oxide film 56 on the side wall of the gate electrode 54.

Subsequently, as shown in FIG. 3 (c), arsenic ions (As ⁺ ) were ion-implanted at an acceleration voltage of 50 keV and an implantation dose of 1 × 10 ¹⁶ / cm ² .
Deep n ⁺ diffusion layers 57a and 57b are formed in the source / drain regions.

Thereafter, as shown in FIG. 3 (d), WF ₆ gas and argon (Ar) gas or, WF ₆ gas and hydrogen (H ₂₎ was used and the gas, by selective vapor deposition, the gate electrode and A tungsten film 58 is grown on the source / drain regions.
At this time, tungsten causes an interface (SiO ₂ / Si) between the silicon oxide film forming the field oxide film or the gate oxide film and the silicon layer forming the gate and the source / drain.
It grows so as to bite along the interface), increasing the leakage current of the PN junction between the diffusion layer and the substrate, and in the extreme case, causing a short circuit. There was a problem that I could not adapt.

Also, to prevent deterioration of the junction characteristics due to the embedding of the SiO ₂ / Si interface of such tungsten, setting the vapor deposition conditions for the tungsten, SiO ₂ / Si, as shown in FIG. 3 (e) However, the problem arises that tungsten grows so as to rise above SiO ₂ and the source / drain and the gate are short-circuited. In any case, there is a problem that cannot be solved when the device is miniaturized.

[Object of the Invention]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable MOS type semiconductor device capable of achieving high integration and high speed without deteriorating the junction characteristics. .

[Outline of Invention]

Therefore, the present invention relates to a MOS type semiconductor device,
Prior to forming the refractory metal film for reducing the contact resistance to the drain region, an insulating film is formed so as to cover the gate electrode, and the refractory metal film is formed on the side wall of the gate electrode by the selective CVD method. Is formed so as to rise above the insulating film that covers the insulating film, and then an insulating film is further formed, and a contact hole is formed in this insulating film, and the contact hole, the gate electrode, and the source / drain regions are formed. Wiring is formed.

That is, first, element isolation is performed to form a predetermined element formation region, and then a gate oxide film and a gate electrode are formed.

Next, after forming an insulating film so as to cover the gate electrode, a diffusion window for forming a source / drain region is opened in the insulating film, and a source / drain region is formed by impurity diffusion.

After that, a refractory metal film is formed on the source / drain regions by, for example, a selective CVD method so as to rise to the surrounding insulating film.

Further, an insulating film is formed on the upper layer, contact holes are bored, and wirings are formed so as to contact the gate electrode and the refractory metal, that is, the source / drain regions, respectively.

In this method, since the gate electrode is covered with the insulating film in advance when the refractory metal film is formed, the growth condition is set so as to prevent the undercut of the insulating film, that is, the SiO ₂ / Si interface. Thus, even if the refractory metal film is formed so as to rise above the insulating film, a short circuit between the source / drain and the gate does not occur. Therefore, it is possible to reduce the wiring resistance without deteriorating the bonding characteristics. That is, it is possible to form a contact wiring which can be miniaturized and has low resistance and high reliability.

Further, preferably, this selective growth step is performed by a first selective CVD step using a reaction gas containing WF ₆ as a main component and a first selective CVD step using a reaction gas containing a mixed gas of WF ₆ and H ₂ as a main component. It is characterized in that it comprises a selective CVD step of 2 and selectively grows a W film. That is, a reaction gas containing WF ₆ as a main component is used to form a W film having a shape that crawls onto the oxide film to protect the interface between the oxide film and the substrate. Then, H _{2 is} added to increase the film thickness.

Further, since the refractory metal film is formed up to the source / drain region and its periphery, that is, the side wall of the gate electrode, this acts as an etching stopper when forming the contact hole at the time of forming the wiring layer, and the source / drain region is over-etched. It is also possible to prevent bonding failure due to over-etching of the field oxide film caused by etching and displacement.

Further, the source / drain regions can be made smaller by forming the contact holes to the source / drain regions so that the contact holes to the regions are formed on the inner side, that is, to the side wall portions of the gate electrode, so that the source / drain regions can be made smaller and the device area can be reduced. Also in this case, when the contact hole is formed, the refractory metal film extending to the side wall of the gate electrode acts as an etching stopper, so that overetching does not occur.

〔The invention's effect〕

As described above, according to the manufacturing method of the present invention, it is possible to prevent a short circuit between the source / drain and the gate and reduce the wiring resistance of the source / drain even at the time of high integration. It is possible to provide a high-performance MOS semiconductor device.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1 (a) to 1 (f) are views showing a manufacturing process of a MOSFET according to an embodiment of the present invention.

First, a field oxide film (insulating film) 12 for element isolation is formed on a P-type silicon substrate 11 to form an element formation region, and then a thin phosphorus oxide film 13 formed in this region is heavily doped with phosphorus. A gate electrode 14 made of the polycrystalline silicon layer is formed. Then, the gate electrode 14 and the field oxide film 12 as a mask, an acceleration voltage 40keV by ion implantation at implantation amount 1 × 10 ¹⁴ / cm ^2, phosphorus (P ⁺⁾
Ion implantation, shallow n ^- diffusion layer in source / drain regions
Form 15a and 15b. (FIG. 1 (a)) After that, as shown in FIG. 1 (b), hydrogen combustion oxidation is performed by heating to 750 ° C., and an oxide film is formed on the surface of the gate electrode 14 and the shallow diffusion layer in the source / drain regions. (Insulating film) 16 is formed. Here, by performing hydrogen combustion oxidation at a low temperature of 750 ° C., the dependence of the oxidation rate on the impurity concentration can be increased, and a thicker oxide film is formed on the gate electrode than on the source / drain regions. (The film thickness of the oxide film was 600Å on the gate electrode and 100Å on the source / drain regions.) Then, as shown in FIG. 1 (c), this surface was reacted with a Freon-based gas. The oxide film 16 is etched until the source / drain regions are exposed by selective ion etching or wet etching using a diluting solution of hydrofluoric acid. After that, an acceleration voltage is 50 keV and an implantation amount is 1 × 10 5 by an ion implantation method. Arsenic (As ⁺ ) ions are implanted at ¹⁶ / cm ² to form deep n ⁺ diffusion layers 17a and 17b in the source / drain regions.

Then, as shown in FIG. 1 (d), a tungsten film 18 is so formed as to rise above the deep n ⁺ diffusion layers 17a, 17b in the source / drain regions and the insulating films 12, 16 around them by a low pressure CVD method. Grow selectively.

Here, in the low pressure CVD process for forming the tungsten film, WF ₆ gas and Ar gas were used as reaction gases, and the substrate temperature was set to 550.
℃, vacuum degree 0.2Torr, WF ₆ partial pressure 0.01Torr, deposition time 3
Insulating films 12, 16 on and around n ⁺ diffusion layers 17a, 17b
The first step of forming a thin tungsten film of about 200 Å on top, and further, using WF ₆ gas and H ₂ gas (molar ratio H ₂ / WF ₆ = 20) as reaction gas, and substrate temperature of 300 to 600 ° C. Reactor pressure 0.
In the range of 01 to 5 Torr, the thin tungsten is formed in two steps including a second step of increasing the thickness to a predetermined film thickness.

By the way, when a tungsten film is grown under the growth conditions of the first step, a reaction product of tungsten and silicon is generated.
The tungsten film is also adsorbed on the insulating films 12 and 16 around the n ⁺ diffusion layers 17a and 17b, and the reaction between the adsorbed silicon fluoride (SiF _x ) and WF ₆ forms a tungsten film. As a result, the tungsten film 18
Are formed so as to extend also on the insulating films 12 and 16 around the n ⁺ diffusion layers 17a and 17b.

Further, as shown in FIGS. 1 (e) and (f), a silicon oxide film (SiO ₂ ) is formed by a plasma CVD method using silane (SiH ₄ ) gas and nitrogen oxide (N ₂ O) gas. After depositing the insulating film 19, contact holes 20a, 20b, 20c are drilled by a reactive ion etching method using a Freon-based gas using a resist pattern (not shown) formed by a photolithography etching method as a mask. Source / drain regions (n ⁺ diffusion layers 17a, 17
b) The oxide film is thicker than above. Therefore, when the contact to the gate electrode is formed, the source / drain regions are over-etched in the usual process, but since the tungsten film is formed, in this etching process,
Since the tungsten film 18 acts as an etching stopper, the insulating film 1 on the sidewalls of the n ⁺ diffusion layers 17a and 17b and the gate electrode 1
6 is never etched. Here, FIG. 1 (e) corresponds to the AA cross section of FIG. 1 (f).

Then, on this upper layer, as shown in FIG.
An 8 μm aluminum (Al) film is deposited by the stopper method and patterned to form the source / drain wiring 21.
Wirings (not shown) for a and 21b and the gate are formed.

In the MOSFET thus formed, the source / drain junction characteristics are not deteriorated, the source / drain and the gate are not short-circuited, and the tungsten film is interposed on the surface of the shallow diffusion layer in the source / drain region. , The wiring resistance and contact resistance are small, and the circuit operation is fast.

In addition, since the presence of the tungsten film prevents overetching of the source / drain regions and overetching of the field oxide film due to misalignment when forming the contact hole, the junction characteristics are deteriorated even when the element is miniaturized. Without fail, a highly reliable MOSFET can be obtained.

Furthermore, since the contact with the source / drain diffusion layer can be extended to the gate electrode or the field oxide film, the source / drain region can be made smaller, and higher integration can be achieved.

Next, the manufacturing process of the MOSFET of another embodiment of the present invention will be described.

First, as shown in FIG. 2 (a), a field oxide film 32 for element isolation is formed on a P-type silicon substrate 31 to form an element formation region, and then a gate oxide film 33 and a high concentration of phosphorus are sequentially doped. A polycrystalline silicon film 34 'and an insulating film 35 made of a silicon oxide layer by the CVD method are formed.

Subsequently, the silicon oxide film 35 is patterned by photolithography as shown in FIG. 2 (b).

Then, using the silicon oxide film 35 as an etching mask, the gate oxide film 33 and the polycrystalline silicon film 34 'are selectively removed by reactive ion etching using a Freon-based gas to form a gate electrode 34.

After that, as shown in FIG. 2 (c), phosphorus ions (P ⁺ ) are implanted by an ion implantation method at an acceleration voltage of 40 keV and an implantation dose of 1 × 10 ¹⁴ / cm ² to form shallow n ⁻ diffusion in the source / drain regions. layer
36a and 36b are formed.

Furthermore, as shown in FIG. 2 (d), CVD is performed on the entire surface of the substrate.
Film made of silicon oxide film with a thickness of 0.3μm
Deposit 7.

Then, this surface is etched by a reactive ion etching method using a Freon-based gas to leave the insulating films 35 and 37 in a shape that covers the gate electrode.
In this reactive ion etching method, since the etching proceeds only in the vertical direction, the insulating film 37 remains on the side wall of the gate electrode 34. On the other hand, since the insulating film 37 is laminated on the insulating film 35 formed in the previous step on the gate electrode, the insulating film 35 remains even if the insulating film 37 on the source / drain regions is removed. .

In this manner, as shown in FIG. 2 (e), arsenic ions (As ⁺ ) are implanted by an ion implantation method at an acceleration voltage of 50 keV and an implantation dose of 1 × 10 ¹⁶ / cm ² to form a deep source / drain region. ⁺ Diffusion layers 38a and 38b are formed.

After that, the same steps as those in the above embodiment may be performed.

That is, the insulating films 32, 3 on and around the deep n ⁺ diffusion layers 38a, 38b in the source / drain regions are formed by the low pressure CVD method.
After selectively growing a tungsten film 39 so as to rise above 7,35, an insulating film 40 made of a silicon oxide film is deposited by a plasma CVD method, and contact holes 41a, 41b and the like are formed by reactive ion etching. Pierce. (Second
(F)) Here, the contact holes are formed outside the source / drain regions, that is, on the field oxide film, but in this case also, since the tungsten film 39 acts as an etching stopper, n ⁺
The diffusion layers 38a and 38b and the field oxide film 32 are not etched.

Thereafter, as shown in FIG. 2 (g), a wiring layer made of an aluminum film is formed by a sputtering method, and this is patterned to form source / drain wirings 42a, 42b and gate wirings (not shown). To do.

This step is different from the above-described embodiment in the step of forming the insulating film that covers the gate electrode, but the MOSFET thus formed has extremely high reliability as in the above-described embodiment. There is.

In the embodiment, the tungsten film is selectively formed on the source / drain region and the insulating film around the source / drain region. However, in addition to this, molybdenum (Mo), tantalum (Ta), titanium (Ti), etc. Needless to say, other refractory metal film may be used. In this case, the reaction gas may be changed.

In addition, the method of the present invention is not limited to the manufacturing process of MOSFET, and the manufacturing of another semiconductor device including a process of forming a low resistance contact in a predetermined region in an element region in which an oxide film is mixed on the surface. The method is also effective.

[Brief description of drawings]

1 (a) to 1 (g) are manufacturing process diagrams of a MOSFET according to an embodiment of the present invention, and FIGS. 2 (a) to (g) are manufacturing process diagrams of a MOSFET according to another embodiment of the present invention. 3 Figures (a) to (e)
FIG. 4 is a manufacturing process diagram of a conventional MOSFET. 11,31,51 …… P-type silicon substrate, 12,32,52 …… Field oxide film, 13,33,53 …… Gate oxide film, 14,34,54 ……
Gate electrode, 15a, 15b, 36a, 36b, 55a, 55b ... Shallow n diffusion layer, 16,35,37,56 ... Insulating film, 17a, 17b, 38a, 38b, 57a, 57b
...... n ⁺ diffusion layer, 18,39,58 …… Tungsten film, 19,40…
… Insulating film, 20a, 20b, 20c, 41a, 41b …… Contact hole, 21a, 21b, 42a, 42b …… Wiring.

Claims (3)

[Claims] 1. When forming a contact in a contact region on one surface of a semiconductor substrate, a first region in which a region adjacent to the contact region is covered with an insulating film.
And an insulating film forming step, wherein a refractory metal film is selectively grown in the contact region by a selective CVD method under growth conditions such that the surface of the contact region climbs up to the insulating film around the contact region. A selective growth step; a step of covering an upper surface of the refractory metal surface with a second insulating film so as to selectively expose a part of the refractory metal surface; and a connection to the contact region via the refractory metal film. And a wiring layer forming step of forming a wiring layer and obtaining a contact. 2. A first insulating film for covering the gate electrode with an insulating film when forming a contact on the source / drain region after forming the gate electrode and the source / drain region on one surface of the substrate. A high-melting-point metal film is selectively grown on the source / drain regions by a selective CVD method under a forming step and growth conditions such that the insulating film around the surface of the source / drain regions crawls. Selective growth step, second insulating film forming step of forming an insulating film on the entire surface, contact holes are formed in the refractory metal film and the gate electrode, and source / drain and gate wiring layers are formed. The method for manufacturing a semiconductor device according to claim 1, further comprising a wiring layer forming step. 3. The selective growth step uses a first selective CVD step using a reaction gas containing WF ₆ as a main component, and a reaction gas containing a mixed gas of WF ₆ and H ₂ as a main component. A second selective CVD step, which is a step for selectively growing a W film.
A method of manufacturing a semiconductor device according to the item.