JPS62177969A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To highly integrate and accelerate a semiconductor device without deterioration of junction characteristic by forming an insulating film to cover a gate electrode before forming a high melting point metal film. CONSTITUTION:An insulating film 12, a gate oxide film 13, a gate electrode 14 and N<-> type diffused layers 15a, 15b are formed on a P-type silicon substrate 11. Then, an oxide film 16 is formed. Thereafter, after the film 16 is etched, N<+> type diffused layers 17a, 17b are formed. Subsequently, a tungsten film 18 is grown to creep on the layers 17a, 17b and 12, 16. After an insulation film 19 is deposited, contact holes 20a-20c are opened. Then, an aluminum film is deposited on the upper layer, and patterned to form source, drain wirings 21a, 21b and gate wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO8 type semiconductor device.

[Prior art and its problems]

Since the 1970s, there has been a growing trend toward higher integration, especially in conductor devices, and superhuman-scale integrated circuits (Mi/LS)
I), and one semiconductor chip L has several million or more 1
- has come to be accumulated.

Incidentally, high integration of integrated circuits is achieved by miniaturization of elements4. Refinement of elementary ■′, 1 deterioration, 14-1 for withering
＋Yes, the wiring should be thin. 11.The wiring should be long.
There is a tendency to become tired. - Horns, I)N Even if they are at the depth of -), they are formed shallowly.Also, electrical connections between the S-1-electrode, the saw diffusion layer, the T-twin diffusion layer, etc., and the metal wiring layer. The area required for making physical connections is also becoming smaller, and the wiring resistance is becoming higher.

This increase in wiring and wire resistance is a serious obstacle to increasing the speed of integrated circuits.

Therefore, recently, a low-resistance film was selectively formed on the gate electrode 1- and the source 1-1 twin diffusion layer 1 by a vapor-phase epitaxy method to lower the wiring resistance. is being attempted.

This example and [, te, for example, tungsten hexafluoride (WF6
) Awareness 1 growth using Nojs/,! An attempt has been made to selectively form a tungsten (W) film on the source train and the gate electrode 1.

In this case, for example, as shown in FIG.
- [7 High concentration of phosphorus! A gate electrode 54 is formed by forming and buttering a polycrystalline silicon film, and using the gate electrode and field oxide film as a mask, phosphorus ions ( P+) ions are implanted to form shallow n- diffusion layers 55a and 55b in the source/drain regions.

Next, as shown in FIG. 3(b), a silicon oxide film (insulating film) with a thickness Q of 3 um is formed over the entire surface of the substrate by the CVD method.
Deposit 56.

Furthermore, by reactive ion etching using Freon gas, etching is performed anisotropically only in the vertical direction to form the gate electrode 5.
Only the silicon oxide film 56 on the sidewalls of 4 remains.

Subsequently, as shown in Fig. 3(c), an acceleration voltage of 50 keV was applied.
Arsenic ion (As+
) is ion-implanted to form deep n main scattering layers 57a and 57b in the source/drain regions.

Thereafter, as shown in FIG. 3(d), the S-1 electrode was A tungsten film 58 is grown in the source, L, and in regions.At this time, tungsten connects the silicon oxide film constituting the field oxide film or gate oxide film, the gate 1, and the source train. It grows along the interface with the constituent layer (S i02 /S i interface), increasing the leakage current of the PN junction between the diffusion layer and the substrate, and in extreme cases. There were problems such as reducing the number of 1t1 circuits, and the problem was that it was not possible to adapt to miniaturization of elements.

In addition, in order to prevent the deterioration of bonding properties due to tungsten biting into the 5i02/Si world,
When the vapor phase growth conditions for tungsten are set, Fig. 3 (e
As shown in ), tungsten grows on 5i02 rather than SiO2/Sl, causing problems such as shorting between the source train and gate. 5 had a problem that could not be solved.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide an MO8 type semiconductor device that can achieve high integration and high speed without deteriorating the junction characteristics, and is highly reliable. .

[Summary of the invention]

Therefore, in an MO5 type semiconductor device, the present invention forms an insulating film to cover the gate electrode prior to forming a high melting point metal film for reducing contact resistance to the source/drain region. The melting point metal film or the insulating film that covers the side walls of the gate electrode is formed so as to creep up.After this, an insulating film is further formed, a contact hole is formed in this insulating film, and the contact hole is ,
-1- Wiring to the gate electrode and source/drain regions is formed.

(a) First, element isolation is performed to form a predetermined element formation region, and then a gate oxide film and a gate electrode are formed.

Next, an insulating film is formed to cover the gate electrode, and then diffusion windows for forming source/drain regions are opened in the insulating film, and the source/drain regions are formed by diffusion of impurities.

Thereafter, a high melting point metal film is formed in the source/drain region -1- by, for example, selective CVD so as to extend onto the surrounding insulating film.

Further, an insulating film is formed on this -L layer, contact holes are bored, and wirings are formed so as to contact the gate electrode and the high melting point metal film, that is, the source/drain regions, respectively.

In this method, when forming a high melting point metal film, the gate electrode is coated with an insulating film in advance, so the growth conditions are such that it prevents penetration under the insulating film, that is, into the 5i02/S1 field. By setting , a short circuit between the source/drain and the gate will not occur even if the high melting point metal film is formed in such a form on the insulating film. Therefore, wiring resistance can be reduced without deteriorating bonding characteristics.

In addition, since the high melting point metal film is formed in and around the source/drain regions, that is, up to the side walls of the gate electrode, this acts as an etching stopper when forming contact holes during wiring layer formation, preventing over-etching of the source/drain regions. Furthermore, it is possible to prevent bonding defects due to over-etching of the field oxide film caused by misalignment.

Furthermore, by drilling the contact holes to the source/drain regions so as to be shifted inward, that is, to the side walls of the gate electrode, the source ψ drain region can be made smaller, and the device area can be reduced. Also in this case, when the contact hole is drilled, the high melting point metal film extending to the side wall of the gate electrode acts as an etching stopper, so over-etching does not occur.

〔Effect of the invention〕

As described above, according to the manufacturing method of the present invention, even in the case of high integration, it is possible to prevent short circuits between the source/drain and the gate, reduce the wiring layer resistance of the source/drain, and achieve high-speed and reliable production. This makes it possible to provide an MO8 type semiconductor device with high performance.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to 1(f) show the MOSFE of the embodiment of the present invention.
It is a figure showing the manufacturing process of T.

First, a field oxide film (insulating film) 12 for element isolation is formed on a P-type silicon substrate 11 to form an element formation region, and then a thin gate oxide film 13 is formed in this region. A gate electrode 14 made of a phosphorus-doped polycrystalline silicon layer is formed. Then, using the gate electrode 14 and field oxide film 12 as a mask, ion implantation was performed at an acceleration voltage of 40 k e V and an implantation jil.
Phosphorus (P+) ions are implanted at X10''/c- to form shallow n- diffusion layers 15a in the source/drain regions.

15b is formed. (FIG. 1(a)) After that, as shown in FIG. 1(b), heating is performed to 750°C to perform hydrogen combustion oxidation, and the electrode 14 and the source
Oxide film (insulating film) 1 on the surface of the shallow diffusion layer in the train region
form 6. Here, by performing hydrogen combustion oxidation at a low temperature of 750°C, it is possible to increase the dependence of the oxidation rate on impurity concentration, and a thicker oxide film is formed on the note electrode than on the source/train region. . (The thickness of the oxide film was 600 mm on the gate electrode and 100 mm on the source/drain region 1-.) Next, as shown in Figure 1(c), this surface was treated with Freon gas. The oxide film 16 is etched by reactive ion etching or wet etching using a diluted hydrofluoric acid solution until the source/drain regions are exposed.
Arsenic (in As) ions are implanted at an implantation dose of 1×1'016/crl to form a deep n main scattering layer 17a in the source/train region.

17b is formed.

Next, as shown in FIG. 1(d), by low pressure CVD method,
The deep n-dominant wave dispersion in the source train region -11 layer 17a, 17bl and the surrounding insulating film 12°16
A tungsten film 18 is selectively grown as shown in step 1. 3 Here, the reduction IICV for forming this tungsten film is
For D i, WF6 gas and A r ) gas are used as reaction gas and 11, substrate l! i is 550°C and the degree of vacuum is 0. 21'
(,) r r % W F 6 partial pressure to 0. 01 T
(,) r r, fil product opening time 3 minutes n] Diffusion layer 1
7a, 17b, l and the surrounding insulating films 12, 161
- forming a thin tungsten film of about 20 OA on the first 1. In history, WF6 gas and H2 gas (molar ratio H2/
WF6°~20) was used as the reaction gas, λ (plate temperature was 300°
~6()0°C1 reactor pressure Olo 1~5 To
r r, the thin tungsten film and the second step of reducing the film thickness to a predetermined thickness are about 2F.

By the way, when the tungsten film is grown in the maroon color of the first step, the reaction product of tungsten and silicon is produced in the insulating films 12, 161 around the n main scattering layers 17a, 17b.
- Also adsorbed and adsorbed silicon fluoride (SiF')
A ringsten film is formed by the reaction between the phosphor and WF6. As a result, the tungsten film 18
Insulating film 12.a and 17b periphery. 16-1''.

Furthermore, as shown in FIGS. 1(e) and 1(f), a silicon oxide film (S 1
After depositing an insulating film 19 consisting of 02), contact holes 20a are formed by reactive ion etching using Freon gas using a resist pattern (not shown) formed by photolithography as a mask.

Drill holes 20b and 20c. The gate electrode-L is the source
The oxide film is thicker than in the drain region (n+ diffusion layers 17a, 17b) -L. For this reason, when forming a contact to the gate electrode, the source/drain regions are over-etched in a normal process, but since a tungsten film is formed, the tungsten film 18 acts as an etching stopper in this etching process. , n main scattering layer-13-, .

17a, 17b and the insulating film 16 on the side wall of the note electrode
will not be etched. Here, Fig. 1(e)
corresponds to the AA cross section in FIG. 1(f).

Subsequently, as shown in FIG. 1(g), an aluminum (A1) film with a thickness of 0.8 μIl+ is deposited on this -1 layer by sputtering, and this is patterned to form the source train wiring 21a. , 21b and gate 1 wiring (not for the national army).

The MOSFET formed in this way has no deterioration in the junction characteristics between the source and drain, no short circuit between the source train and the gate, and a tungsten film is interposed on the surface of the shallow diffusion layer in the source and drain regions. As a result, wiring resistance and contact resistance are low, and circuit operation is fast.

In addition, when forming contact holes, the presence of the tungsten film prevents over-etching of the field oxide film caused by over-etching to the source/drain region and misalignment, which leads to deterioration of junction characteristics even when devices are miniaturized. A highly reliable MOSFET can be obtained without any problems.

Furthermore, since the contact to the source train diffusion layer can be routed to the gate electrode or even onto the field oxide film, the source train region can be made smaller and higher integration is possible.

Next, a manufacturing process of a MOSFET according to another embodiment of the present invention will be described.

First, a P-type silicon substrate 3 shown in FIG.
1, a field oxide film 32 for element isolation is formed to form an element formation region, and then a gate oxide film 33, a polycrystalline silicon film 34' highly doped with phosphorus, and a silicon oxide layer formed by CVD method are sequentially formed. An insulating film 35 is formed.

Subsequently, the silicon oxide film 35 is patterned by photolithography as shown in FIG. 2(b).

Then, using this silicon oxide film 35 as an etching mask, the gate oxide film 33 and the polycrystalline silicon film 34' are selectively removed by reactive ion etching using Freon gas to form a gate electrode 34.

After this, as shown in FIG. 2(c), ion implantation was performed at an acceleration voltage of 40 k e V and an implantation amount of 1×10"/c♂
Then, phosphorus ions (P) are implanted to form a shallow n- diffusion layer 36a in the source/train region.

36b.

Historically, as shown in Figure 2(d), CV
An insulating film 37 made of a silicon oxide film having a thickness of 0.3 μI11 is deposited by the D method.

Subsequently, this surface is etched by a reactive ion etching method using Freon gas to leave the insulating film 35.degree. 37 in a shape that covers the gate electrode. In this reactive ion etching method, since etching proceeds only in the vertical direction, the insulating film 37 remains on the side walls of the gate electrode 34. On the other hand, since an insulating film 37 is laminated on the insulating film 35 formed in the previous step on the gate electrode, the insulating film 37 in the source/drain region 3
Even if 7 is removed, the insulating film 35 remains.

In this way, as shown in FIG. 2(e), by the ion implantation method, the implantation m1×1016/
In step C, arsenic ions (As+) are implanted to form the deep n main wave dispersion layer 38a at the source and drain.

38b.

After that, the same steps as in the above embodiment may be followed.

That is, the tungsten film 39 was selectively grown by low pressure CVD so as to creep up on the deep n main scattering layers 38a, 38b of the source/drain regions and on the insulating films 32, 37, 35 around them. After, plasma CVD
An insulating film 40 made of a silicon oxide film is deposited by a method,
Contact hole 41 is formed by reactive ion etching.
a.

41b etc. (FIG. 2(f)) Here, the contact hole is formed outside the source/drain region, that is, to the field oxide film. In this case, the tungsten film 39 also acts as an etching stopper. n main scattering layer 38a, 38
b and field oxide film 32 are not etched.

Thereafter, as shown in FIG. 2(g), a wiring layer made of an aluminum film is formed by sputtering, and this is patterned to form source/drain wirings 42a, 42b and gate wiring (not shown). Form.

Although this process differs from the previous example in the step of forming the insulating film covering the gate electrode, the MOSFET formed in this way has extremely high reliability as in the previous example. There is.

In the example, a tungsten film was selectively formed on the source/drain region and the insulating film around it, but other materials such as molybdenum (Mo), tantalum (Ta), titanium (Ti), etc. , it goes without saying that other high melting point metal films may also be used. In this case, the reaction gas may be changed.

Furthermore, the method of the present invention is not limited to the manufacturing process of MOSFETs, but can be applied to other semiconductor devices including a 21-layer structure in which a low-resistance contact is formed in a predetermined region within an element region where an oxide film is mixed on the surface. It is also self-effective in the manufacturing method.

[Brief explanation of drawings]

FIG. 1(a) to ♀(g> are MOSFEs of the embodiments of the present invention.
2(a) to (g) are manufacturing ports for MOSFETs according to other embodiments of the present invention, and FIG. 3(
a) to (e) are manufacturing diagrams of conventional MOSFETs. 11.31.51-1 type silicon substrate, 12°32.
52...Field oxide film, 13,33°53...
Ge-1・Oxide film, 14, 34.54... Gate electrode,
15a, 15b, 36a, 36b, 55a. 55 b-... Shallow n-diffusion layer, 16, 35, 37.56
...Insulating film, 17a, 171), 38a, 38b. 57 a, 57 b-n+diffusion layer, 18, 39.5
8...Tungsten film, 19.40...Insulating film, 20
a. 201), 20c, 41a, 41b-=r contact hole, 21a, 21b, 42a, 42b=--wiring. = 19- Figure 1 (G) Figure 1 (b) 1 to 16 Figure 1 (C) Figure 1 (d) Figure 2 (Q) Figure 2 (b) Figure 2 (C) 2 (d) Figure 2 (e) Figure 2 (f) Figure 2 (9) Figure 3 (CI) Figure 3 (b) Figure 3 (C) Figure 3 (d) Figure 3 (e)

Claims (4)

[Claims] (1) When forming contact electrodes for each region formed on one surface of the substrate and built into the element formation region where an oxide film is mixed on the surface, the first step is to cover the adjacent region with an insulating film. a high melting point metal film forming step of selectively growing a high melting point metal film from the surface of a predetermined region where the contact electrode is to be formed to the surrounding insulating film; a second insulating film forming step of depositing an insulating film over the entire surface; and after drilling a contact hole corresponding to the high melting point metal film, a wiring layer connected to the predetermined region via the high melting point metal film. 1. A method of manufacturing a semiconductor device, comprising: a step of forming a wiring layer. (2) After forming a gate electrode and a source/drain region in a semiconductor region of one conductivity type formed on one surface of the substrate, when forming a contact to the source/drain region, the gate electrode is covered with an insulating film. a first step of forming an insulating film to cover the source and drain regions; a step of forming a high-melting point metal film to selectively grow a high-melting point metal film so as to extend from the surface of the source and drain regions to the insulating film around the source and drain regions; a second insulating film formation step of forming an insulating film over the entire surface; and a wiring layer formation step of forming a source/drain and gate wiring layer by drilling contact holes corresponding to the high melting point metal film and the gate electrode. A method of manufacturing a semiconductor device according to claim (1), comprising the steps of: (3) The method for manufacturing a semiconductor device according to claim (1) or (2), wherein the high melting point metal film forming step is a chemical vapor deposition (CVD) step. (4) The method for manufacturing a semiconductor device according to claim (3), wherein the high melting point metal film forming step is a low pressure CVD step.