JP2000269488A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To substantially remove the influence of the facet occurring in the silicon epitaxial growth film which is the sacrificial layer of a metal silicon film made on a source/drain region. SOLUTION: This manufacturing method makes the sidewall insulating film provided at the flank of a polysilicon gate electrode 23 provided on a semiconductor substrate 21 into a laminated structure of a silicon oxide film 25 and a silicon nitride film 24 from the top, and causes a silicon epitaxial growth film 28 to selectively grow on the exposed semiconductor substrate, and causes a polysilicon film 29 to grow on the silicon nitride film 24, and causes a silicon epitaxial growth film to grow selectively on the semiconductor substrate exposed on such growth condition so as not to cause a silicon film to grow on the silicon oxide film 25. By this method, the polyslicon film 29 joins the facet face made at the flank of the growth film, and the facet form of the growth film substantially ceases to appear.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for manufacturing a semiconductor device having a MOS transistor in which a diffusion region and a gate electrode are reduced in resistance using a selective epitaxial growth technique.

[0002]

2. Description of the Related Art Conventionally, low diffusion layer resistance and shallow junction are incompatible conditions. Therefore, it is known to attach metal or silicide on the diffusion layer in order to approach this condition. This method includes a method in which a metal is formed on the entire surface, only a metal on silicon is silicidized, and a metal on a silicon oxide film is removed by etching with an acid, and a method in which a metal is formed only on silicon by a CVD method. . In the former method, a metal film such as molybdenum is formed by a CVD method on the entire surface of a semiconductor substrate on which a gate electrode made of polysilicon is formed, and this is heat-treated to silicide the silicon surface. However, in this method, since the source / drain regions themselves are silicided, this region becomes thin,
At this portion, a junction leak with the semiconductor substrate occurs. As a method for avoiding this, a method has been proposed in which a silicon epitaxial growth film is formed as a sacrificial layer on source / drain regions and this portion is silicided.

[0003]

A conventional method for silicidizing the surface of a source / drain region using a selective epitaxial growth film as a sacrificial layer will be described with reference to FIGS. Each of the drawings is a cross-sectional view of a manufacturing process of a semiconductor device showing a silicidation method. First, a gate oxide film (SiO ₂ ) 2 is formed on an n-type silicon semiconductor substrate 1 on which an element isolation structure (not shown) is formed. And CVD (Chemical Vepour Deposition) method,
Ion implantation, PEP (Photo Engraving Process), R
A polysilicon film is deposited by an IE (Reactive Ion Etching) method and etched to form a gate electrode 3 (FIG. 11A). Next, the silicon nitride film (SiN) is
D is deposited by the D method, and this film is etched in a different direction by the RIE method to form a sidewall insulating film (S) on the side surface of the gate electrode 3.
iN) 4 is formed. Using the gate electrode 3 as a mask, an impurity such as phosphorus is ion-implanted to form a source region 5 and a drain region 6 near the surface of the silicon semiconductor substrate.
Is formed (FIG. 11B). Next, the gate oxide film 2 on the surface of the source / drain regions 5 and 6 is removed, and an epitaxial growth film 7 is selectively formed only on the silicon surface.
At this time, a facet (a) is formed in the selective epitaxial growth film 7 formed on the source / drain regions 5 and 6.

At this time, a polysilicon layer 8 is simultaneously formed on the gate electrode 3 (FIG. 11C). Next, a metal film 9 of tungsten or the like having a thickness of about 30% of the selective epitaxial growth film is deposited and annealed to form a metal silicide film 10 only in a portion where the silicon and the metal film are in contact. I do. At this time, the thickness of the metal silicide is about 1
70%. The selective epitaxial growth film 7 is entirely made to be the metal silicide film 10. Side wall insulating film 4
The upper metal film 9 remains without being silicided (FIG. 12A). Next, only the metal film 9 is selectively removed from the metal silicide film 10 (FIG. 12).
(B)). Next, an interlayer insulating film 11 such as SiO ₂ is deposited by a CVD method or the like. The surface of the interlayer insulating film 11 is flattened, and then an electrode lead-out opening is formed by RIE. Then, a connection wiring layer 12 of aluminum or the like is formed in the opening. On the flattened interlayer insulating film 11, a metal film such as aluminum is formed. The metal film is patterned to form the connection wiring layer 12.
Wiring layers 13a, 13b, 13 electrically connected to
c is formed. Through the subsequent processing steps, the MOS transistor is completed (FIG. 12C).

When this conventional method is used, a facet is formed in a selective epitaxial growth film formed on a source / drain region. The angle depends on the crystal orientation (1
00) is about 45 degrees. Therefore, when a selective epitaxial growth film is silicided by laminating a metal film on this portion, the facet portion at the tip of the selective epitaxial growth film is silicided as shown by a portion b in FIG. This extends to the inside of the source / drain region inside the semiconductor substrate. As a result, a junction leak with the semiconductor substrate occurs at this portion. This tendency becomes more remarkable as the miniaturization of the semiconductor device progresses, and as a result, the source / drain regions and the like become shallower. The present invention has been made in view of such circumstances, and a semiconductor device capable of substantially eliminating the influence of facets generated in a silicon epitaxial growth film that is a sacrificial layer of a metal silicide film formed on a source / drain region. And a method for producing the same.

[0006]

According to the present invention, a side wall insulating film formed on a side surface of a polysilicon gate electrode provided on an exposed semiconductor substrate made of silicon single crystal is formed from a silicon oxide film (SiO ₂ ). , Silicon nitride film (Si
N), a silicon epitaxial growth film is selectively grown on the exposed semiconductor substrate, a polysilicon film is grown on the silicon nitride film, and a silicon film is not grown on the silicon oxide film. A silicon epitaxial growth film is selectively grown on the exposed semiconductor substrate. According to this method, the polysilicon film is bonded to the facet surface formed on the side surface of the silicon epitaxial growth film, and the facet shape of the silicon epitaxial growth film does not substantially appear. Such a silicon epitaxial growth film is formed on a source / drain region of a MOS transistor, and is used as a sacrificial layer of the metal silicide film. It can be prevented from being formed inside.

That is, a method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate insulating film on a semiconductor substrate and forming a polysilicon gate electrode on the gate insulating film;
Forming a first sidewall insulating film on the gate electrode side surface and the gate insulating film in contact with the side surface;
A first side wall formed on the side wall of the gate electrode in the side wall insulating film
Forming a second sidewall insulating film on the second region formed on the gate insulating film in a region continuous with the region, and forming the gate electrode, the first and second sidewall insulating films on the second region. Implanting an impurity into the semiconductor substrate as a mask, forming source / drain regions opposed to each other across the region below the gate electrode in the semiconductor substrate, and forming a region in the semiconductor substrate where the source / drain regions are formed A silicon epitaxial growth film is selectively formed on the upper side and the upper surface of the gate electrode, and a silicon epitaxial growth film is formed on an exposed region of the first sidewall insulating film and a side surface of the silicon epitaxial growth film on a region where the source / drain regions are formed. Growing a polysilicon film in contact with the formed facet portion and contacting the both, the silicon epitaxial growth film and the polysilicon film The method of manufacturing a semiconductor device which metal film is formed, characterized in that it comprises the step of changing both by annealing them to the metal silicide film. The first
The sidewall insulating film may be made of a silicon nitride film, and the second sidewall insulating film may be made of a silicon oxide film.

In the step of forming the metal silicide film, the source / drain regions of the semiconductor substrate may not be silicided. Forming a polysilicon film on the first sidewall insulating film in the step of forming the silicon epitaxial growth film;
The epitaxial growth conditions may be set so that a silicon film is not grown on the sidewall insulating film. The thickness of the silicon epitaxial growth film may be equal to the sum of the thickness of the gate insulating film and the thickness of the first sidewall insulating film. When these are made equal, when the polysilicon film is formed in the facet portion, that portion can be made to have substantially the same thickness as the other portions of the silicon epitaxial growth film.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIGS. 1 to 10, a MOS in which a selective epitaxial growth film is used as a sacrificial layer when forming a metal silicide film on source / drain regions.
A method for manufacturing a transistor will be described. 1 to 3
FIG. 4 is a sectional view and a plan view of a manufacturing process of a MOS transistor,
8 are cross-sectional views of a manufacturing process of a MOS transistor, FIG. 9 is a characteristic diagram showing the temperature dependence of the total number of critical gases (molecules), and FIG. 10 is a plan view of a silicon semiconductor substrate.

The main surface of the semiconductor substrate 21 has an STI (Shallow
An element isolation structure 35 such as Trench Isolation is formed, which defines an element region. Semiconductor substrate 21
Is made of, for example, an n-type silicon semiconductor (FIG. 10).
Next, a gate oxide film (SiO ₂ ) 22 having a thickness of about 20 Å (2 nm) is formed on the main surface of the semiconductor substrate 21. Then, a polysilicon film is deposited by CVD, impurities are introduced by ion implantation, and PEP, RIE
This is patterned to form a gate electrode 23. In this patterning, the final dimensions are set only in the direction in which the source / drain regions are formed (FIG. 1).
(A), FIG. 1 (b)). Next, a silicon nitride film (Si
N) is applied to the entire surface of the semiconductor substrate 21 by CVD to a thickness of 48 nm.
This film is etched in a different direction by RIE, and is patterned so as to extend on the gate oxide film 22 to a position separated by a predetermined distance from the side surface of the gate electrode 23 and the end of the side surface. First sidewall insulating film (Si
N) 24 are formed (FIGS. 2A and 2B). Next, a silicon oxide film (SiO ₂ ) is deposited by CVD, and the second silicon oxide film is left by RIE so that only the side wall of the portion protruded by the gate polysilicon electrode is left.
Is formed.

Further, the silicon nitride film 24 is etched using the second side wall insulating film 25 as a mask to form the gate electrode 2.
Unnecessary portions including the portion deposited on 3 are removed. Further, using the gate electrode 23 as a mask, a source region 26 and a drain region 27 are formed in the surface region of the semiconductor substrate 21 by ion implantation. Thereafter, the gate oxide film 22 is formed.
Is also etched to expose the silicon of the source / drain regions 26 and 27 (FIGS. 3A and 3B). Next, on the source / drain regions 26 and 27, for example, 5
A 0 nm-thick selective epitaxial growth film 28 of silicon is formed. At this time, the second side wall insulating film (SiO ₂ ) 2
5 without depositing anything on the first sidewall insulating film (SiN)
The growth conditions are set so that polysilicon is deposited on 24. FIG. 9 shows the relationship between the total number of critical gas molecules capable of performing selective epitaxial growth and the growth temperature of the silicon oxide film (SiO ₂ ) and the silicon nitride film (SiN). This is made possible by using conditions in the range of In FIG. 9, the vertical axis represents the total number of critical gases (molecules) (atom ratio), and the horizontal axis represents the growth temperature. By depositing silicon under these conditions, a polysilicon film 29 is simultaneously grown from an exposed portion of the first sidewall insulating film (SiN) 24 formed on the sidewall of the gate electrode 23, and a selective epitaxial growth film is formed. 28
This is joined to the facet part of.

That is, since the polysilicon film 29 fills the space created by the facet of the selective epitaxial growth film 28, the facet is substantially suppressed as shown in the region c. At this time, a polysilicon film 30 also grows on the polysilicon gate electrode 23 at the same time (FIG. 4). It is appropriate that the thickness of the selective epitaxial growth film 28 is substantially equal to the sum of the thicknesses of the gate oxide film 22 and the first sidewall insulating film. By doing so, the portion lacking the facet portion can be compensated for by the polysilicon film 29 without any excess and deficiency, and this portion can maintain substantially the same thickness as the other portions. Next, at a thickness of about 30% of the selective epitaxial growth film, for example, tungsten, molybdenum, tantalum,
A metal film 31 selected from titanium or the like is selectively epitaxially grown 28, polysilicon film 29, polysilicon film 3
0, deposited on the second sidewall insulating film 25 (FIG. 5).

Next, by annealing the laminated film of silicon and metal, the metal silicide film 32 is formed only at the portions where the silicon films 28, 29 and 30 are in contact with the metal film.
Is formed. At this time, the thickness of the metal silicide film 32 serving as a source / drain or gate electrode is about 170% of the selective epitaxial growth film, and the entire selective epitaxial growth film is a metal silicide film. Since the metal film 31 on the second side wall insulating film 25 is not silicided, it is left as a metal film (FIG. 6). Next, leaving the metal silicide film 32 as it is, only the metal film on the second sidewall insulating film 25 is selectively removed by etching (FIG. 7). Next, an interlayer insulating film 33 such as SiO ₂ is deposited by a CVD method or the like. The surface of the interlayer insulating film 33 is, for example, a CMP (Chemical Mechanical Polishing).
After that, an electrode lead-out opening is formed by RIE. An electrode lead-out opening formed in the interlayer insulating film 33 is formed on each region (source / drain region and gate) of the MOS transistor.
Each area is exposed inside. A metal film such as aluminum is deposited on the interlayer insulating film 33 so as to be embedded in the opening.

Then, the metal film is polished by a CMP method or the like to remove the metal other than the opening, and the M
Connection wiring layer 3 electrically connected to gate electrode 23, source / drain regions 26, 27, etc. of the OS transistor
4 is buried. On the planarized interlayer insulating film 33, a metal film such as aluminum is formed. This metal film is patterned to form metal wiring layers 36a, 36b and 36c electrically connected to the connection wiring layer 34. Through the subsequent processing steps, the MOS transistor is completed (FIG. 8). By using this method, even if a facet is formed in the selective epitaxial growth film formed on the source / drain region, the polysilicon film growing from the exposed portion of the first sidewall insulating film makes up for the thickness of the facet portion. Make it even. Therefore, when a selective epitaxial growth film is silicided by laminating a metal film on this portion, even if there is a facet at the tip of the selective epitaxial growth film, silicidation does not extend to the source / drain regions inside the semiconductor substrate. Absent. As a result, this tendency is remarkably reduced, although a junction leak with the semiconductor substrate tends to occur in this portion in the past.

The following effects are recognized in the present invention.
The side wall insulating film on the side surface of the gate electrode formed on the exposed main surface of the silicon semiconductor substrate is a silicon nitride film (SiN) as a first side wall insulating film and a second side wall insulating film thereover from the bottom. When the epitaxial growth is performed by forming a laminated structure composed of a silicon oxide film (SiO ₂ ), a condition is used in which the silicon epitaxial film is grown selectively on the silicon substrate and the silicon film without growing on the silicon oxide film. As a result, the polysilicon film grown from the surface of the silicon nitride film is joined to the facet surface formed on the side surface of the silicon epitaxial growth film, and the facet portion of the silicon epitaxial growth film is complemented to offset the effect of the facet. Become. In this manner, the formation of the metal silicide film in the source / drain regions when the silicon epitaxial growth film is silicided can be prevented, so that the junction leak with the semiconductor substrate is suppressed.

[0016]

As described above, according to the present invention, the polysilicon film is bonded to the facet surface formed on the side surface of the epitaxial Si growth film, and the influence of the facet shape of the silicon epitaxial growth film is cancelled. As a result, the silicon epitaxial growth film is formed on the source / drain region of the MOS transistor and is used as a sacrificial film of the metal silicide. When the growth film is subsequently silicided, the metal silicide film is formed on the source / drain region of the semiconductor substrate. It can be prevented from being formed. It is possible to suppress junction leak with the semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device of the present invention.

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 3 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.
Area view.

FIG. 4 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a cross-sectional view showing a manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a plan view of a semiconductor substrate used for a semiconductor device of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of a conventional semiconductor device.

FIG. 12 is a sectional view showing a manufacturing process of a conventional semiconductor device.

[Explanation of symbols]

1, 21,... Silicon semiconductor substrate, 2, 22,.
· Gate oxide film, 3, 23 ··· polysilicon gate electrode, 4 ··· sidewall insulating film, 5, 26 ··· source region, 6, 27 ··· drain region, 7, 28 ···
Selective epitaxial growth film, 8, 29, 30 ... polysilicon film, 9, 31 ... metal film, 10, 32
..Metal silicide films, 11, 33 ... interlayer insulating films, 12, 34 ... connection wiring layers, 13a, 13b, 1
3c, 36a, 36b, 36c... Metal wiring layer, 24
... First sidewall insulating film (SiN film), 25.
Sidewall insulating film (SiO ₂ film).

Claims (5)

[Claims] A gate insulating film formed on a semiconductor substrate;
Forming a polysilicon gate electrode on the gate insulating film, forming a first side wall insulating film on the side surface of the gate electrode and the gate insulating film in contact with the side surface, and forming the first side wall insulating film Forming a second side wall insulating film on a first region formed on a side wall of the gate electrode and a second region formed on the gate insulating film contiguous to the first region; Implanting impurities into the semiconductor substrate using the electrodes, the first and second sidewall insulating films as masks, and forming opposing source / drain regions on the semiconductor substrate with the region under the gate electrode interposed therebetween; A silicon epitaxial growth film is selectively formed on the region of the semiconductor substrate where the source / drain regions are formed and on the upper surface of the gate electrode, and a region where the first sidewall insulating film is exposed and Growing a polysilicon film in contact with a facet portion formed on a side surface of the silicon epitaxial growth film on a region where the source / drain region is formed; and forming a polysilicon film on the silicon epitaxial growth film and the polysilicon film. Forming a metal film on the substrate and annealing the film to convert the film to a metal silicide film. 2. The method according to claim 1, wherein the first sidewall insulating film is made of a silicon nitride film, and the second sidewall insulating film is made of a silicon oxide film. . 3. The method according to claim 1, wherein in the step of forming the metal silicide film, the source / drain regions of the semiconductor substrate are not silicided.
A method of manufacturing a semiconductor device according to claim 2. 4. In the step of forming the silicon epitaxial growth film, the polysilicon film is grown on the first sidewall insulating film, and the silicon film is not grown on the second sidewall insulating film. 4. An epitaxial growth condition is set.
The method for manufacturing a semiconductor device according to any one of the above. 5. The semiconductor device according to claim 1, wherein a thickness of the silicon epitaxial growth film is equal to a sum of a thickness of the gate insulating film and a thickness of the first sidewall insulating film. 13. A method for manufacturing a semiconductor device according to