JPH09162392A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the stress at the time of forming a silicide layer by preventing a buried element separating insulation film from making direct contact with the silicide later. SOLUTION: Insulator 9 is formed on the side wall of a buried insulation film 2 prior to forming a silicide layer 7. The silicide layer 7 is formed from the exposed part not covered with an insulation films 6 and 9 on a diffusion layer 5. The silicide layer 7 is prevented from making contact with the buried insulation film 2 by suitably setting the width (w) of the insulator 9. The depth (s) of the silicide layer 7 in the horizontal direction can be set smaller than the width (w) of the insulator 9, by setting the width (w) of the insulator 9 thicker than the depth (t) of the silicide layer 7 in the vertical direction, and the silicide layer 7 is prevented from making contact with the buried insulation film 2. Thus, when high melting point metal reacts to silicon, the insulation layer 7 does not hinder the growth of the silicide layer 7, and the stress can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an element isolation region formed by embedding an insulating film, in which a silicide film is formed on the element region.

[0002]

2. Description of the Related Art With the high integration of semiconductor devices, miniaturization of element isolation regions cannot be avoided. A so-called embedded element isolation structure in which a groove is formed in a semiconductor substrate and an insulating film is embedded in the groove is promising as a next-generation element isolation technology because the isolation breakdown voltage between elements does not deteriorate even when miniaturized.

On the other hand, due to the miniaturization of semiconductor elements, the depth of the diffusion layer becomes shallower, so that the sheet resistance of the diffusion layer region tends to increase. Therefore, the parasitic resistance due to the diffusion layer resistance cannot be ignored, and there is a problem that the performance of the semiconductor element is significantly deteriorated.

As a method for solving this problem, for example, T
i Si _x, and a silicide film of high melting point metal such as WSi _x is formed on the diffusion layer, sheet of the diffusion layer region - there is a method of reducing the sheet resistance.

FIG. 11A is a sectional view of a conventional MOS transistor using a buried element isolation and a silicide diffusion layer. A semiconductor substrate 1 and an element isolation region 2 formed by embedding an insulating film in the semiconductor substrate 1.
, A gate insulating film 3, a gate electrode 4, and a diffusion layer 5 that constitutes a source and drain region form a MOS transistor, and a silicide layer 7 is formed on the diffusion layer 5. As a result, the resistance of the diffusion layer 5 is reduced. In this conventional example, the silicide layer 8 is further formed on the gate electrode 4 to reduce the resistance of the gate electrode 4. Also,
The silicide layer 7 and the silicide layer 8 are separated by the insulating film 6 formed on the side wall of the gate electrode 4.

FIG. 11 (b) is an enlarged view of a portion surrounded by a circle in FIG. 11 (a). As shown in this figure, in such a conventional semiconductor device, at point A in the figure, the silicide layer 7, the buried element isolation region 2, and the substrate 1 are in contact at the same time.

In general, the silicide layer 7 is formed by depositing a refractory metal film on a silicon substrate and then performing heat treatment to react the refractory metal with silicon. Therefore, as indicated by a point A in FIG. 11B, when the reaction proceeds along the edge of the buried element isolation region, the silicide layer 7 cannot grow in the direction of the insulating layer 2. A great deal of stress occurs in this area.
Further, since the side surface of the groove is damaged by etching when forming the groove, there is a problem that a defect is likely to occur in the substrate 1.

The refractory metal in the silicide layer 7 reacts with the silicon in the substrate 1 not only by the heat treatment for forming the silicide layer 7 but also by the heat treatment after the formation of the silicide film 7. Since a different silicide layer is formed, stress may occur at this time and defects may occur.

Such defects cause various leak currents from the diffusion layer 5 to the substrate 1, increase current consumption of the integrated circuit, destroy storage data of the semiconductor memory element, and so on. Induce problems.

[0010]

As described above, in the conventional semiconductor device, the buried element isolation insulating film 2, the refractory metal silicide film 7 and the silicon substrate 1 are in contact with each other at the interface between the element isolation regions. Therefore, there is a problem that crystal defects are likely to occur due to stress generated when the refractory metal and silicon react to form a silicide layer.

An object of the present invention is to provide a semiconductor device having a buried element isolation region and a silicide layer, which has a structure for suppressing the generation of crystal defects.

[0012]

In order to solve the above problems and achieve the object, the semiconductor device according to the present invention is characterized in that the buried element isolation insulating film and the silicide layer are not in direct contact with each other. .

That is, in a semiconductor device having an insulating layer embedded in a groove formed in a semiconductor substrate and a silicide layer formed in a part of the semiconductor substrate, the silicide layer is formed on the side surface of the groove. It is characterized in that it is formed so as not to come into direct contact with the insulating layer.

A semiconductor device according to the present invention is a semiconductor device having an insulating layer embedded in a groove formed in a semiconductor substrate and a silicide layer formed in a part of the semiconductor substrate, wherein the semiconductor substrate An insulating material is formed on the insulating layer so as to be adjacent to the insulating layer, thereby preventing the insulating layer and the silicide layer from directly contacting each other on the side surface of the groove.

Further, in the semiconductor device according to the present invention, an insulating layer embedded in a groove formed in a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film, and the semiconductor. A semiconductor device comprising: a MOSFET composed of a diffusion layer formed on a substrate; a sidewall insulating film formed on a side surface of the gate electrode; and a silicide layer formed on the diffusion layer. The semiconductor device further includes an insulator formed on the semiconductor substrate adjacent to the insulating layer, which prevents direct contact between the insulating layer and the silicide layer.

As described above, according to the semiconductor device of the present invention, since the insulating layer buried in the groove and the silicide layer are not in direct contact with each other on the side surface of the groove, the refractory metal in the silicide layer and the substrate It is possible to prevent stress from being generated on the side surface of the groove and crystal defects when the silicide is formed by the reaction with the silicon.

Further, the semiconductor device of the present invention utilizes the fact that the insulating layer is formed on the semiconductor substrate adjacent to the insulating layer so that the silicide layer is not formed on the insulating layer. It is possible to prevent direct contact between the insulating layer and the insulating layer.

Further, the semiconductor device of the present invention has a silicide layer on the diffusion layer, and an insulator is formed adjacent to the insulation layer of the MOSFET in which the element isolation region is constituted by the insulation layer buried in the groove. Since the insulating layer and the silicide layer embedded in the groove do not directly contact each other on the side surface of the groove, the silicide is formed by the reaction between the refractory metal in the silicide layer and the silicon in the substrate. At times, stress is prevented from occurring on the side surface of the groove, and crystal defects can be prevented from occurring.

When the side wall insulating film formed on the side surface of the gate electrode and the insulator formed adjacent to the insulating layer are made of the same material, the gate is formed. It is possible to prevent the formation of the silicide layer on the side surface of the electrode and at the same time prevent the formation of the silicide layer in contact with the insulating layer. Therefore, it is possible to prevent the silicide layer and the insulating layer from directly contacting each other, and to prevent the occurrence of crystal defects due to stress.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a sectional view showing the structure of a semiconductor device according to the present invention. As in the conventional case, the semiconductor substrate 1, the element isolation region 2 formed by embedding an insulating film in the semiconductor substrate 1, the gate insulating film 3, the gate electrode 4, the source and drain regions. , A silicide layer 7 formed on the diffusion layer 5, and a silicide layer 8 formed on the gate electrode 4.
And the insulating film 6 formed on the side wall of the gate electrode 4 causes M
An OS transistor is configured.

FIG. 1 (b) is an enlarged view of the portion B of FIG. 1 (a). As shown in this figure, in the present embodiment, unlike the conventional case, the insulator 9 is provided on the sidewall of the buried insulating film 2.
Is formed so that the silicide layer 7 and the buried insulating film 2 do not come into direct contact with each other.

In such a structure, the insulator 9 is formed on the side wall of the buried insulating film 2 before forming the silicide layer 7 by utilizing the fact that the silicide layer is not formed on the insulating film. Can be realized by

A method of manufacturing the above-described semiconductor device structure according to the present invention will be described below. 2 to 10
FIG. 7A is a process sectional view illustrating the manufacturing method of the semiconductor device according to the invention;

On the p-type silicon substrate 1, for example, by a hydrogen combustion oxidation method at a temperature of 950 ° C., for example, a thickness of 50 n is obtained.
An oxide film (SiO ₂ ) 11 having a thickness of m is formed, and then a polycrystalline silicon film 12 having a film thickness of, for example, 150 nm is deposited (FIG. 2).

Next, the usual lithography method and, for example, R
By using an etching technique such as an IE (Reactive Ion Etching) method, the polycrystalline silicon film 1 in the element isolation formation planned region 1
2, the oxide film 11 and a part of the silicon substrate 1 are removed (FIG. 3).

After that, an insulating film 2 for element isolation such as an oxide film (SiO ₂ ) is deposited (FIG. 4). Next, for example, after depositing the polycrystalline silicon film 13 to a thickness of 200 nm, the polycrystalline silicon film 13 is removed except for a wide element isolation region by using a normal lithography method and an etching technique such as an RIE method. (Fig. 5).

Further, for example, CMP (chemical mechanical polishing)
Method, the oxide film 2 is polished to remove the polycrystalline silicon film 12
The surface of the is exposed and the oxide film 2 is left in the element isolation region. At this time, polishing is performed under the condition that the polishing rates of the polycrystalline silicon films 12 and 13 are smaller than the polishing rate of the oxide film 2 to prevent the substrate 1 from being polished by overetching. (FIG. 6).

Next, the remaining polycrystalline silicon films 12 and 13 and the oxide film 11 on the device forming region are removed by using, for example, a chemical vapor etching technique to complete the buried device isolation (FIG. 7).

After that, a gate oxide film 3 having a film thickness of, for example, 10 nm is formed on the substrate 1 by, for example, a thermal oxidation method, and subsequently, a thickness of 200 is obtained by, for example, a chemical vapor deposition method.
nm polycrystal silicon film is deposited. Further, the gate electrode 4 is formed by removing the polycrystalline silicon film other than the gate electrode portion by using a usual lithography method and an etching technique such as RIE method (FIG. 8).

Next, for example, arsenic (As) is added to the acceleration voltage 60.
Impurities are added to the substrate 1 and the gate electrode 4 by ion implantation with keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . After forming the diffusion layer 5 in the substrate 1 in this way, for example, a nitride film (SiN) 14 is deposited (FIG. 9).

Next, the SiN film 14 is etched by using an anisotropic etching technique such as RIE to expose the surface of the gate electrode 4 and the substrate 1, and SiN is formed on the side wall of the gate electrode 4. The film 14 is left and the sidewall insulating film 6 is formed. At this time, unlike the prior art, by appropriately adjusting the etching time, the SiN film 1 is also formed on the sidewall portion of the buried insulating film 2.
4 is left and the side wall insulator 9 is formed (FIG. 10).

In this way, by leaving the SiN film 14 on the sidewall portion of the buried insulating film 2, the buried insulating film 2 is formed in order to form the sidewall insulator 9 in a self-aligned manner with respect to the buried insulating film 2. It is necessary to project it from the surface of the substrate 1.

After that, a refractory metal film such as titanium (Ti) is deposited by, for example, a sputtering technique. Further, by using, for example, RTA (Rappid Thermal Anneal) technology, heat treatment is performed at a temperature of 950 ° C. for 30 seconds to react Si in the diffusion layer region 5 with Ti deposited on the diffusion layer region 5. , Depth of 0.05 to 0.
Forming a 2μm about silicide (TiSi _x) layer 7. At this time, by exposing the upper surface of the gate electrode 4 in advance, the Si of the gate electrode 4 and the Ti deposited on the gate electrode 4 are caused to react with each other so that the silicide layer 8 becomes a silicide layer. Formed at the same time as 7.

Here, since the insulating film does not react with Ti,
The formation of the silicide layer 7 proceeds from the exposed portion of the diffusion layer 5 which is not covered with the insulating films 6 and 9. Therefore, by appropriately setting the width w of the insulator 9, it is possible to prevent the silicide layer 7 and the buried insulating film 2 from coming into contact with each other.

However, as shown in FIG. 1B, the formation of the silicide layer 7 not only advances in the depth direction in a region not covered with the insulating film but also penetrates below the insulating film. It also progresses laterally. It is generally known that the depth of travel s in the horizontal direction is smaller than the depth of t in the vertical direction, but the depth ratio (s / t) depends on the heat treatment time and other conditions for forming the silicide layer 7. Depends on and is not uniquely determined.

Therefore, by setting the width w of the insulator 9 to be thicker than the depth t of the silicide layer 7 in the vertical direction, the depth s of the silicide layer 7 in the horizontal direction is set to be larger than the width w of the insulator 9. Since it can be made smaller, it is possible to prevent the silicide layer 7 and the buried insulating film 2 from coming into contact with each other. The width w of the insulator 9 can be adjusted by, for example, the deposited film thickness of SiN 14 and its etching conditions.

Also, the height h of the insulator 9 after etching
Is not particularly limited as long as the insulator 9 always exists adjacent to the buried insulating film 2. However, when the sidewall forming technique by the anisotropic etching method as described above is used, the height h of the remaining sidewall is generally larger than the width w. After the etching progresses and the height h becomes equal to the width w, the width w is reduced at the same time as the height h is reduced by further etching. In this way, the height h is formed to be, for example, the width w or more.

The height h of the side wall insulator 9 is the height h 2 of the protruding embedded insulating film 2 from the substrate surface and the height h ₂ of the insulator 9.
The height h ₂ of the buried insulating film 2 is generally smaller than the height h ₂ of the buried insulating film 2 due to over etching or the like. Therefore, the upper limit of the height h of the insulator 9 is buried height h ₂ next to the insulating film 2, the height h of the buried insulating film 2
₂ is limited, for example, by the depth of focus of the lithography method when processing the gate electrode 4, or the etching residue. Therefore, the height h of the sidewall insulator 9 is
For example, the height is approximately the same as the height of the gate electrode 4.

Next, for example using sulfuric acid and pressurized hydrogen peroxide water, to remove the unreacted Ti film, is left only TiSi _x film, the silicide layer 7 and the gate of the diffusion layer 5 - gate electrode 4 above To form a silicide layer 8 (FIG. 1).

After that, an interlayer insulating film is formed, a connection hole is opened, and a metal wiring film of, for example, an alloy of Al, Si, and Cu is processed to form a wiring by using a normal technique. As described above, in the present embodiment, the silicide layer 7 and the buried insulating film 2 are directly connected to each other by the insulator 9 formed on the side surface of the buried insulating film 2 by utilizing the fact that the silicide layer is not formed on the insulating film. Since the structure does not contact, the growth of the silicide layer 7 is not disturbed by the insulating layer 2 when the refractory metal reacts with silicon, so that the stress can be reduced. Also, since the side surface of the groove is damaged by etching, defects are likely to occur,
By preventing the silicide film 7 from being formed in such a region, it is possible to suppress the generation of stress, prevent the generation of defects, and reduce the leak current.

In the method of manufacturing the semiconductor device according to the present embodiment, the embedded insulating film 2 is formed so as to project from the surface of the substrate, so that the projected embedded insulating film 2 is formed.
The side wall insulator 9 can be formed on the side surface of the self-alignment.

Therefore, since the lithography process for forming the insulator 9 is not required, a fine semiconductor element can be formed without being affected by the alignment accuracy of the lithography method.

Further, since the width w of the sidewall insulator 9 can be set by the deposited film thickness of the insulating film and does not require the processing using the lithography method, it is not affected by the processing size of the lithography method. In addition, a fine semiconductor element can be formed.

Further, as in the present embodiment, the embedded insulating film 2 is projected from the surface of the substrate, so that the sidewall insulating film 9 is formed at the same time as the step of forming the sidewall insulating film 6 on the side surface of the gate electrode 4. Therefore, it is possible to easily realize the structure of the present invention without adding any steps as compared with the related art.

However, the method of forming the insulator 9 is not limited to the above embodiment. For example, in the above-described embodiment, the buried insulating film 2 is formed so as to project from the surface of the substrate 1, but the buried insulating film 2 is buried only at the same height as the surface of the substrate 1 or at a position lower than the surface of the substrate 1. It is also possible to

Further, in the above embodiment, only the insulating film is buried in the groove, but a semiconductor film such as a polycrystalline silicon film or a conductive film is buried through the insulating film formed on the side surface of the groove. The present invention can be applied even in the case where it is provided. Further, in the above-described embodiment, the insulating film embedded in the groove constitutes the element isolation region, but the present invention is also applicable to the case where the conductive film embedded via the insulating film constitutes the electrode, for example. Is possible.

In either case, the insulator 9 is formed on the semiconductor substrate 1 so as to be adjacent to the insulating layer 2 formed on the side surface of the groove, and the silicide layer 7 and the insulating layer are formed by the insulator 9. Any structure may be used as long as it is prevented from directly contacting with the side surface of the groove.

[0048] In the above embodiment has formed the sidewall insulator 9 by SiN, for example, an oxide film such as SiO ₂ containing oxide film or impurities such as PSG, such as SiO _2, yet another insulating film Can be used.

Although TiSi _x is used as the silicide layers 7 and 8 in the above embodiment, MoSi _x and WS are used.
i _x, CoSi _x, it is also possible to use other silicide material such as NiSi _x.

In the above-described embodiment, the Ti film 14 is deposited and the silicide layer 7 is formed by the reaction between silicon and Ti in the diffusion layer 5. However, the selective CVD method is used to form the silicide layer 7 on the diffusion layer 5. it is also possible to deposit a silicide such as selectively e.g. TiSi _x to. In this case, at the time of forming the silicide layer 7, since the reaction between Ti and Si as described above does not occur, crystal defects are less likely to occur,
The refractory metal in the silicide layer 7 reacts with the silicon in the substrate in the subsequent heat step, so that a crystal defect occurs. Therefore, by using the structure according to the present invention so that the silicide layer 7 and the buried insulating film 2 do not come into direct contact with each other, the same effect as that of the above-described embodiment can be obtained.

[0051]

As described above, the semiconductor device according to the present invention includes the buried element isolation and the silicide layer, and can suppress the generation of crystal defects.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to the present invention.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to the present invention.

3A to 3D are process cross-sectional views showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 6 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 7 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 10 is a process cross-sectional view showing the method of manufacturing a semiconductor device according to the present invention.

FIG. 11 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Embedded insulating film, 3 ... Gate insulating film, 4 ... Gate electrode, 5 ... Diffusion layer, 6, 9 ... Side wall insulating film, 7, 8 ... Silicide layer, 11 ... Oxide film , 12, 13
... Polycrystalline silicon film, 14 ... Ti

Claims (7)

[Claims] 1. A semiconductor device having an insulating layer embedded in a groove formed in a semiconductor substrate and a silicide layer formed in a part of the semiconductor substrate, wherein the silicide layer is formed on the side surface of the groove. A semiconductor device, which is formed so as not to come into direct contact with an insulating layer. 2. A semiconductor device having an insulating layer buried in a groove formed in a semiconductor substrate and a silicide layer formed in a part of the semiconductor substrate, the insulating layer being adjacent to the insulating layer on the semiconductor substrate. A semiconductor device comprising an insulator formed as described above, which prevents the insulating layer and the silicide layer from directly contacting each other on the side surface of the groove. 3. An insulating layer embedded in a groove formed in a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film, and a diffusion layer formed on the semiconductor substrate. A semiconductor device having a side wall insulating film formed on a side surface of the gate electrode and a silicide layer formed on the diffusion layer. A semiconductor device comprising an insulator formed adjacent to a layer, which prevents direct contact between the insulating layer and the silicide layer. 4. The sidewall insulating film formed on the side surface of the gate electrode and the insulator formed adjacent to the insulating layer are made of the same material. Semiconductor device. 5. The semiconductor device according to claim 1, wherein the insulator is SiN. Wherein said insulator is a semiconductor device of claims 1 to 4, wherein the SiO ₂ containing SiO ₂ or impurities. 7. The silicide layer is made of TiSi _x , Mo.
_{Si x, WSi x, CoSi x} , consisting of NiSi _x Group - claims 1 to 5 is formed by any one of up
13. The semiconductor device according to claim 1.