JP3387518B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device, and more particularly to a MOS type semiconductor device in which a refractory metal silicide is selectively formed on a part of a gate electrode and a source / drain region (hereinafter referred to as salicide structure). The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventional semiconductor devices, especially static R
In semiconductor memory devices such as AM, a structure as shown in FIG. 3A has been used to reduce the area of memory cells. That is, the first transistor formed on the P-type semiconductor substrate 301 containing silicon as its main component is separated from the adjacent second transistor by the element isolation oxide film 302. In the first transistor, 303 is a gate oxide film, 304 (a) is a gate electrode wiring material, 305
Is a low-concentration N-type impurity diffusion layer, 306 is an insulating film (hereinafter referred to as a sidewall) formed on the side wall of the gate electrode wiring material, 308 is a high-concentration N-type impurity diffusion layer, that is, source / drain, 311 is It is a refractory metal silicide. The gate electrode wiring material 304 (b) of the adjacent second transistor is in contact with the semiconductor substrate 301 without the gate oxide film 303 interposed therebetween and via the N-type impurity diffusion layer 312 and the low-concentration N-type impurity diffusion layer 305. It is connected to the source / drain 308 of the first transistor. The N-type impurity diffusion layer 312 is usually the second gate electrode wiring material 3
It is formed by the N-type impurities that have come out from 04 (b).

[0003]

However, in the above-mentioned conventional technique, the gate electrode wiring material of the second transistor is connected to the source / drain region of the first transistor through the impurity diffusion layer. In such a case, there is a problem in that the contact resistance between the gate electrode wiring material of the second transistor and the impurity diffusion layer is large, which reduces the current driving capability of the transistor. Further, in the above-mentioned conventional technique, the gate electrode wiring material is formed by partially etching the gate oxide film 303, depositing polycrystalline silicon as a gate electrode wiring material on the entire surface, and performing photoetching. When etching the gate electrode wiring material, normally, when the etching of the gate electrode wiring material is completed, the gate oxide film and the element isolation oxide film with a slow etching rate are exposed and overetching is performed. Then, since the semiconductor substrate containing silicon as a main component having a high etching rate is exposed, the semiconductor substrate is scraped to form a groove as shown in FIG. 3B during overetching. As a result, the resistance of the impurity diffusion layer that connects the gate electrode wiring material of the second transistor and the source / drain of the first transistor increases, and the current driving capability decreases, and sometimes the connection cannot be established. Had. Also,
This groove has a problem that it causes a short circuit or a disconnection of a semiconductor wiring material in a later process.

The present invention solves such a problem, and the object thereof is to minimize the resistance involved in the connection between the gate electrode wiring material of the adjacent second transistor and the source / drain of the first transistor. Providing a structure of a semiconductor device having an excellent current driving capability, and at the same time, providing an excellent structure and manufacturing method of a semiconductor device capable of reducing a step which causes a short circuit or a disconnection of a semiconductor wiring material in a subsequent process. To do.

[0005]

(1) A semiconductor device according to the present invention comprises a device isolation insulating film formed on a semiconductor substrate and a source or drain formed in a region surrounded by the device isolation insulating film. Having a first impurity diffusion layer that becomes
A first type transistor and an electrode wiring formed on the semiconductor substrate via an insulating film, the film including a refractory metal silicide in a region surrounded by the element isolation insulating film, An electrode wiring that is electrically connected to the impurity diffusion layer, and below the electrode wiring, and
A second impurity diffusion layer formed in a region close to the first impurity diffusion layer and having an impurity concentration lower than that of the first impurity diffusion layer; The containing film is provided on at least a part of the surfaces of the electrode wiring, the first impurity diffusion layer, and the second impurity diffusion layer, and the electrode wiring is electrically connected to at least the first impurity diffusion layer. The sidewall insulating film is removed in the portion where the selective connection is made.

(2) The semiconductor device of the present invention is the semiconductor device according to (1), further including a MIS transistor having the electrode wiring as a gate electrode, and the electrode wiring being a gate electrode. And the MIS transistor formed in the region surrounded by the element isolation insulating film are separated by the element isolation insulating film.

(3) The semiconductor device of the present invention is the semiconductor device according to (1) or (2), in which the film containing the first refractory metal silicide and the second refractory metal silicide are included. A semiconductor device characterized in that the refractory metal silicide contained in the film containing is a silicide of titanium, tungsten, molybdenum or cobalt.

[0008]

[0009]

[0010]

[0011]

[0012]

[0013]

1 is a sectional view of a semiconductor device of the present invention.
The first transistor formed over the semiconductor substrate 101 containing P-type impurities is isolated from the adjacent second transistor by the element isolation oxide film 102. In the first transistor, 103 is a gate insulating film formed of an insulating film such as an oxide film or a nitride film, 104 (a) is a gate electrode wiring material, 105 is a low concentration N-type impurity diffusion layer, and 106 (a )
Is a sidewall formed of an insulating film such as a silicon oxide film or a silicon nitride film, 108 is a high-concentration N-type impurity diffusion layer, that is, source / drain, and 111 is a refractory metal silicide. In FIG. 1, since there is no sidewall formed of an insulating film on the side wall of the gate electrode wiring material 104 of the second transistor, the gate electrode wiring material 104 (b) of the second transistor and the side wall of the second transistor are not formed. The source / drain 108 of the first transistor is the same as the gate electrode wiring material 104 (b) of the second transistor and the first transistor.
Are connected by a refractory metal silicide 111 selectively formed on and near the source / drain 108 of the transistor.

Next, a method of manufacturing the semiconductor device shown in the embodiment of FIG. 1 will be described in detail with reference to FIGS. 2 (a) to 2 (c).

First, an element isolation oxide film 202 is formed on a semiconductor substrate 201 containing P-type impurities by a LOCOS method, and then wet oxidation at 850 ° C. is performed to form a gate oxide film 203 with a thickness of about 20 nm. Then, polycrystalline silicon is deposited on the polycrystalline silicon to diffuse impurities, and the polycrystalline silicon is dry-etched using a resist pattern to form gate electrode wiring materials 204 (a) and 204 (b) containing N-type impurities. ) Is formed. At this time, a gate oxide film 203 is formed under the gate electrode wiring material.
Alternatively, since the element isolation oxide film 202 is always formed, the groove is not formed by cutting the semiconductor substrate during the etching. Next, ion implantation of an N-type impurity such as phosphorus was performed to prepare for forming a low-concentration N-type impurity diffusion layer 205, and then an insulating film such as a silicon oxide film or a silicon nitride film was deposited by a CVD method. Then, anisotropic etching is performed by dry etching to form sidewalls 206 (a) and 206 (b) on the sidewalls of the gate electrode wiring materials 204 (a) and 204 (b).
Next, a silicon oxide film is formed to a thickness of about 20 nm on the entire surface of the wafer by a CVD method to protect the surface of the semiconductor substrate, and then N-type impurities such as arsenic are ion-implanted and annealed to perform high-concentration N-type impurity diffusion layer. Simultaneously with forming 208, a low concentration N-type impurity diffusion layer 205 in which impurities have been ion-implanted is formed. (End of Figure 2
(A)) Next, using the resist pattern 209,
Gate electrode wiring material 204 of the second transistor formed in the source / drain region of the second transistor
Side wall 206 (b) formed on the side wall of (b)
Are removed using an etching solution such as hydrofluoric acid. (End of Figure 2
(B)) Next, the resist pattern is removed, and the semiconductor substrate 2
Silicon oxide film 2 formed to protect the surface of 01
After removing 07, a refractory metal such as titanium, tungsten, molybdenum, or cobalt is formed in a thickness of 20 to 100 nm on the entire surface of the wafer by a sputtering method. Then, a heat treatment is performed at 650 ° C. to 760 ° C. for a short time by a lamp annealing method to form the surface of the gate electrode wiring materials 204 (a) and 204 (b) or the source / drain region 2
The refractory metal forms a refractory metal silicide 211 in a portion where the semiconductor substrate such as 08 is exposed on the surface, a portion where the refractory metal is in direct contact with and in the vicinity thereof. At this time, the sidewall 20 of the first transistor
The refractory metal on 6 (a) or on the element isolation oxide film remains unreacted and does not form refractory metal silicide.
On the other hand, the gate electrode wiring material 2 of the second transistor
04 (b) and the source / drain 208 of the first transistor are formed via the gate oxide film 203. However, since the gate oxide film is sufficiently thin, the refractory metal formed on the gate oxide film is A refractory metal silicide 211 is formed. (The above FIG. 2C) Next, the unreacted refractory metal is removed using a selective etching solution such as a mixed solution of water, hydrogen peroxide and ammonia, and the second heat treatment is performed at 800 ° C. by a lamp annealing method. Perform at 900 ° C for a short time.

As a result, the gate electrode wiring material 204 (b) of the second transistor and the source / drain 208 of the first transistor are connected by the refractory metal silicide selectively formed on each surface. It Also,
In the first transistor, the refractory metal silicide on the gate electrode wiring material 204 (a) and the source / drain 208 are separated by the sidewall 206 (a).

It is needless to say that the present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the gist of the invention. For example, in the above-described embodiment, the silicon oxide film 207 formed to protect the surface of the semiconductor substrate is removed before the refractory metal is formed by the sputtering method. However, the refractory metal is not removed but the refractory metal is sputtered. However, the refractory metal is formed on the semiconductor substrate and the gate electrode wiring material through a thin oxide film to some extent by facilitating formation of the refractory metal silicide by increasing the temperature of the first heat treatment. In this case, the refractory metal silicide can be formed on the semiconductor substrate and the gate electrode wiring material.

As described above, since the source / drain of the first transistor is connected to the gate electrode wiring material of the adjacent second transistor by the refractory metal silicide, the resistance involved in the connection is different from the conventional one. Then, since the size becomes negligible, it is possible to miniaturize the memory cell by reducing the area required for connection, and it is possible to provide an excellent semiconductor device in which the current driving capability of the transistor is less deteriorated. Become. In addition, since the groove is not formed in the semiconductor substrate when the gate electrode wiring material is etched, it is possible to reduce the step difference that causes a short circuit or disconnection of the semiconductor wiring material in the subsequent process.

[0019]

As described above, according to the structure of the semiconductor device of the present invention and the method of manufacturing the same, the source / drain of the first transistor is adjacent to the gate electrode of the second transistor by the refractory metal silicide. Since it is connected to the wiring material, the resistance involved in the connection becomes negligibly small compared to the conventional one, so it is possible to miniaturize the memory cell by reducing the area required for the connection, and the current of the transistor It is possible to provide an excellent semiconductor device in which the driving capability is less deteriorated. Further, according to the structure of the semiconductor device of the present invention and the method for manufacturing the same, since the groove of the semiconductor substrate is not formed when the gate electrode wiring material is etched, there is no short circuit or disconnection of the semiconductor wiring material in the subsequent process. It is possible to reduce the step difference that causes it. In addition, since impurities such as arsenic and boron tend to hinder the formation of low-resistance refractory metal silicide, "a semiconductor in a region below the electrode wiring and close to the first impurity diffusion layer" A second impurity diffusion layer formed on the substrate and having an impurity concentration lower than that of the first impurity diffusion layer "
A refractory metal silicide having a low resistance is formed thicker on the upper surface than on the first impurity diffusion layer. Therefore, according to the configuration of the present invention, a thicker refractory metal silicide is formed around the contact between the sidewall of the electrode wiring and the semiconductor substrate (impurity diffusion layer), so that the electrode wiring and the impurity diffusion layer are formed. The connection can be made more stable and have a low resistance.
That is, the present invention has a remarkable effect that a semiconductor device having a salicide structure capable of more reliable electrical connection can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device of the present invention.

2A to 2C are cross-sectional views illustrating main steps of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

101, 201, 301 ... Semiconductor substrates 102, 202, 302 ... Element isolation oxide films 103, 203, 303 ... Gate oxide films 104 (a), 204 (a), 304 (a) ...・ First
Gate electrode wiring material 104 (b), 204 (b), 304 (b) ...
Of the gate electrode wiring material 105, 205, 305 ... Low concentration N-type impurity diffusion layers 106 (a), 206 (a), 306 (a) ...
Side walls 206 (b), 306 (b) of the second transistor ... Side walls 207, 307 of the second transistor ... Silicon oxide films 108, 208, 308 ... High-concentration N type Impurity diffusion layer 209 ... Resist pattern 210 ... Refractory metal 111, 211, 311 ... Refractory metal silicide

Claims (3)

(57) [Claims] 1. An MI having an element isolation insulating film formed on a semiconductor substrate and a first impurity diffusion layer formed in a region surrounded by the element isolation insulating film and serving as a source or a drain.
An S-type transistor and an electrode wiring formed on the semiconductor substrate via an insulating film, wherein a film containing a refractory metal silicide is used in a region surrounded by the element isolation insulating film. An electrode wiring that is electrically connected to the impurity diffusion layer, and an electrode wiring that is formed in a region below the electrode wiring and close to the first impurity diffusion layer. And a second impurity diffusion layer having a low impurity concentration, wherein the film containing the refractory metal silicide includes the electrode wiring, the first impurity diffusion layer, and the second impurity diffusion layer. And a side wall insulating film is removed at least in a portion where the electrode wiring is electrically connected to the first impurity diffusion layer. Semiconductor device. 2. The semiconductor device according to claim 1, further comprising a MIS transistor having the electrode wiring as a gate electrode, the MIS transistor having the electrode wiring as a gate electrode, and the element isolation insulating film. A semiconductor device characterized in that it is separated from the MIS type transistor formed in a region surrounded by by the element isolation insulating film. 3. The semiconductor device according to claim 1, wherein the high melting point contained in the film containing the first refractory metal silicide and the film containing the second refractory metal silicide. A semiconductor device, wherein the metal silicide is a silicide of titanium, tungsten, molybdenum, or cobalt.