JPH08340106A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent generation of rugged surface of a silicide film and disconnection of wirings by a method wherein an orientation (111) is exposed to silicon surface by etching, a high melting point metal film is formed, and an alloy of a semiconductor and a high melting point metal is formed by heat treatment. CONSTITUTION: A field oxide film 2 is formed on a substrate 1, and an orientation (111) face 8 is exposed to the surface of the substrate 1 using anisotropic etching. Subsequently, a high melting point titanium film 9 is formed on the whole surface of the substrate 1. Then, silicification is generated on the part which comes in contact with the silicon of the titanate film 9 by conducting heat treatment on the substrate 1 in a nitride atmosphere, and a titanium silicide film 10 is selectively formed on the part which comes in contact with silicon. The titanium film 9, which is left by making no reaction, is removed by oxidizing treatment. Consequently, as the substrate 1 is processed on the preferential orientation (111) face in advance in conformity with the progress of silicification on the orientation (111) face of a silicide fine wire, a low resistance value can be obtained to the region where wire width is narrow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device formed by integrating insulated gate field effect transistors (hereinafter referred to as MOS transistors).

[0002]

2. Description of the Related Art In recent years, the integration density of integrated circuits has been increasing year by year. In order to increase the degree of integration of integrated circuits, it is necessary to reduce the size of the elements that form the circuits. MO
In the case of the S transistor, the problem of the short channel effect occurs when the size is reduced, and there is a method of making the diffusion layer shallow in order to suppress the problem. However, if such a method is used, the resistance of the diffusion layer becomes large and the circuit operation becomes slow.

As a method for solving the above problems, there is known a technique of selectively forming a metal silicide film on the surface of a source, a drain and other diffusion layers and the surface of a gate electrode formed of a polycrystalline silicon film to lower the resistance. . This is because a refractory metal film such as titanium is deposited on the entire surface of the substrate with the necessary silicon surface exposed, and heat treatment is performed to react the metal in contact with the silicon surface with silicon to form a silicide film. The metal film that has not reacted with silicon on the insulating film is removed. In this case, the metal silicide film formed on the gate electrode and the source / drain region of the MOS transistor is automatically formed separately.
Before depositing the metal film, an insulating film is selectively formed on the side wall of the gate electrode in advance. As a result, the metal silicide film can be formed in a self-aligned manner on the source, drain and other diffusion layers and the gate electrode, and the resistance of the diffusion layer in those regions can be reduced.

[0004]

However, in the above-mentioned structure, the miniaturization of the LSI progresses, the metal film and the diffusion layer become thin, and the metal silicide region becomes thin. There has been a problem that the reaction is affected and unevenness is generated on the surface of the metal silicide, resulting in an increase in resistance, and a break in the thin wire. This is because the substrate used for the LSI has a plane other than the 111 plane, for example, 100 plane, in order to improve the transistor performance, and the silicidation reaction preferentially proceeds to the plane orientation 111 plane. . Therefore, in view of the above problems, it is an object of the present invention to provide a silicide film which has no surface unevenness even when the silicide film thickness is thin and which does not cause disconnection even in a thin wire and has good uniformity.

[0005]

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a plane orientation 111 on a silicon surface by anisotropic etching of the entire surface of the substrate, and a method of forming the entire surface of the substrate. A step of forming a refractory metal film,
A step of performing a heat treatment to react the metal film on the source / drain region and the gate electrode with silicon to form a metal silicide film on the source / drain region and the gate electrode; In addition, it has a configuration including a step of removing the metal film.

[0006]

According to the present invention, the silicidation reaction proceeds uniformly and smoothly by setting the silicon surface which causes silicidation to the plane orientation 111 which is the orientation in which the silicidation reaction generally proceeds stably.

[0007]

【Example】

(Embodiment 1) A method for manufacturing a semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1D show a method of manufacturing a silicide in the first embodiment of the present invention. First, as shown in FIG. 1A, a field oxide film 2 is formed on a p-type silicon substrate 1, and then, as shown in FIG. Expose. Thereafter, as shown in FIG. 1C, a titanium film 9 is deposited to a thickness of about 50 nm on the entire surface of the substrate by using a refractory metal such as titanium by a sputtering method. Then, this substrate is heat-treated, for example, in a nitrogen atmosphere at 600 ° C. to cause a silicidation reaction in the portion 5 of the titanium film 9 in contact with silicon. As a result, as shown in FIG. 1D, the titanium silicide film 10 is selectively formed in the portion in contact with silicon.
To form. In the case of this embodiment, these silicide films have a thickness of about 80 nm. The titanium film 9 left unreacted in the silicidation reaction step is removed by acid treatment.

In the thin silicide wire obtained by the above embodiment, since the substrate is processed in advance to the 111 surface in accordance with the preferential silicidation in the 111 azimuth plane, the line width is narrower than in the conventional case. A low resistance value can be obtained. The present invention is not limited to the above-described embodiment, and similar effects can be obtained by using, for example, titanium, cobalt, tungsten, molybdenum, nickel, platinum or the like as the metal film for forming silicide. .

(Second Embodiment) A semiconductor device manufacturing method according to a second embodiment of the present invention will be described below with reference to the drawings.

FIGS. 2A to 2F show a manufacturing process of a MOS transistor according to the second embodiment of the present invention. First, as shown in FIG. 2A, a field insulating film 2 is formed on a p-type silicon substrate 1 according to a normal process,
Subsequently, a gate electrode 4 made of a phosphorus-doped polycrystalline silicon film is formed via the gate oxide film 3. Then, using the gate electrode 4 as a mask, for example, arsenic is ion-implanted to n.
+ Type source and drain regions 5 and 6 are formed. After that, as shown in FIG. 2B, a 200 nm silicon oxide film 7 is deposited as an insulating film on the entire surface of the substrate by, for example, a CVD method, and then an anisotropic dry etching method, for example, reactive in etching or sputter etching is performed. Etching of the oxide film is performed by the above method to leave the oxide film 7 only on the side wall of the gate electrode 4 as shown in FIG.
Thus, the source, drain regions 5 and 6 and the gate electrode 4 are formed.
The surface of is exposed.

Next, as shown in FIG. 2D, the 111 plane 8 is exposed on the surfaces of the source and drain regions 5 and 6 by using, for example, anisotropic wet etching. After that, as shown in FIG. 2E, a titanium film 9 is formed to a thickness of about 50 nm on the entire surface of the substrate by using a refractory metal such as titanium by a sputtering method.
accumulate. Then, this substrate is heat-treated in, for example, a nitrogen atmosphere at 600 ° C. to cause a silicidation reaction in the portions of the titanium film 9 in contact with silicon, that is, the polysilicon on the source / drain regions 5 and 6 and the gate electrode 4. Let As a result, as shown in FIG.
The titanium silicide film 10 is selectively formed only on the drain and drain regions 5 and 6 and the gate electrode 4. In this case, the silicide film of this embodiment has a thickness of about 80 nm. Note that the titanium film 9 that remains without reacting in the above steps is removed by acid treatment.

As in the first embodiment, the silicide thin wires obtained by the above-described embodiments are prepared by preliminarily removing the substrate 11 in accordance with the preferential silicidation in the 111 azimuth plane.
Since it is processed on one surface, a low resistance value can be obtained even in a region where the line width is narrower than in the conventional case. The present invention is not limited to the above-described embodiment, and similar effects can be obtained by using, for example, titanium, cobalt, tungsten, molybdenum, nickel, platinum or the like as the metal film for forming silicide. .

[0014]

As described above, according to the present invention, by providing the step of anisotropically etching the entire surface of the substrate so that the surface has a silicon plane orientation of 111 planes, even if the silicide film thickness is thin, there is no surface irregularity In this case, it is possible to provide a silicide film with good uniformity in which disconnection does not occur.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

 1 p-type silicon substrate 2 field insulating film 3 gate oxide film 4 gate electrode 5 source region 6 drain region 7 side wall 8 silicon 111 face 9 titanium film 10 titanium silicide film

Claims (3)

[Claims] 1. A step of forming an element isolation region in a semiconductor substrate, and etching the element formation region of the semiconductor substrate to 1
11 exposing the azimuth plane, forming a metal film on the surface of the semiconductor substrate after the etching, and reacting the metal film with the semiconductor substrate in the element region by heat treatment to form an alloy of semiconductor and metal And a method of manufacturing a semiconductor device. 2. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of doping an impurity with the gate electrode as a mask to form source and drain regions, and a sidewall portion of the gate electrode. A step of selectively forming an insulating film, a step of etching a portion of the source and drain regions where the insulating film is not formed to expose a 111-oriented surface, and a metal film is formed on the entire surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of reacting the metal film on the source, drain region and the gate electrode with the semiconductor substrate by heat treatment to form a metal silicide film on the source, drain region and the gate electrode. . 3. The method of manufacturing a semiconductor device according to claim 1, wherein anisotropic etching is used for etching.