JPH05206407A - Mos transistor and its manufacture - Google Patents

Abstract

PURPOSE:To make the formation area of a MOS transistor small and to make the integration of the MOS transistor high by a method wherein a gate with reference to the surface of a substrate (or a base body) is formed in the depth direction. CONSTITUTION:A first gate 18 is formed, via a first gate insulating film 17, on the sidewall 15 on one side and on the bottom face 16 of a groove 14 formed in a semiconductor substrate 11; a second gate 23 is formed, via a second gate insulating film 22, on the sidewall 20 on the other side and on the bottom face 21 of said groove 14. A first source-drain region 19 and a second source-drain region 24 are formed on the upper layer of the semiconductor substrate 11 excluding the inside of the groove 14; a third source-drain region 25 is formed on the upper layer of the semiconductor substrate 11 on the bottom face side of the groove 14. Alternatively, source-drain regions are formed on the upper layer and the lower layer of a semiconductor part formed on the upper layer of an insulating base body; gates (not indicated in the figure) are formed, via a gate insulating film (not indicated in the figure), on both sidewall sides of the semiconductor part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and its manufacturing method.

[0002]

2. Description of the Related Art As memory devices have larger capacities and higher integration, the devices are becoming finer. Most of the above memory devices are MOS type memory devices. A typical example is shown in Figure 1.
8 will be described. As shown in the figure, the semiconductor substrate 111
A gate 113 is formed on the gate insulating film 112. Gate sidewall insulating films 114 are formed on both side walls of the gate 113. In addition, on the upper layer of the semiconductor substrate 111 on both sides of the gate 113,
Source / drain regions 115 and 116 having an LDD structure are formed. As described above, the MOS transistor 11
0 is formed. Further, the MOS transistor 110
An interlayer insulating film 117 is formed so as to cover the. The interlayer insulating film 117 on the source / drain regions 116.
A contact hole 118 is provided in the. A wiring 119 connected to the source / drain region 116 is formed through the contact hole 118. The wiring 119 is composed of, for example, a barrier metal layer and an aluminum alloy layer.

Next, a method of manufacturing the MOS transistor 110 will be described with reference to the manufacturing process chart of FIG. As shown in (1) of FIG. 19, the element isolation region 121 is formed in the upper layer of the semiconductor substrate (for example, a single crystal silicon substrate) 111 by, for example, the LOCOS method. Then, a silicon oxide film (122) is formed by a thermal oxidation method, and then a polycrystalline silicon film (123) is formed by a chemical vapor deposition method. Subsequently, the gate 113 is formed of the polycrystalline silicon film (123) by photolithography and etching. Further, the gate insulating film 112 is formed from the silicon oxide film (122). Then, the semiconductor substrate 111 on both sides of the gate 113 is formed by ion implantation.
The low-concentration diffusion layers 124 and 125 are formed on the upper layer.

Thereafter, as shown in (2) of FIG. 19, a silicon oxide film (126) is formed by chemical vapor deposition and then etched back to form a silicon oxide film (126) on the side wall of the gate 113. A gate sidewall insulating film 114 is formed. Then, using the gate sidewall insulating film 114 and the gate 113 as an ion implantation mask, high-concentration diffusion layers 127 and 128 are formed in a state deeper than the low-concentration diffusion layers 124 and 125. Thus, the low concentration diffusion layer 124 and the high concentration diffusion layer 127 form the source / drain regions 115, and the low concentration diffusion layer 125 and the high concentration diffusion layer 128 form the source / drain regions 116. Form. The MOS transistor 110 is formed as described above.

Subsequently, as shown in FIG. 19C, the MOS transistor 110 is formed by chemical vapor deposition.
And the interlayer insulating film 11 made of a silicon oxide film.
Form 7. After that, a contact hole 118 is formed in the interlayer insulating film 117 on the source / drain region 116 by photolithography and etching. Further, the contact hole 118 is formed by a sputtering method.
Of the wiring layer (1
After the film 29) is formed, the wiring 119 is formed by removing the portion indicated by the chain double-dashed line of the wiring layer (129) by photolithography and etching.

In order to form a fine device structure by the above manufacturing process, a photolithography technique for forming a resist pattern of deep submicron or less is required.

[0007]

However, it is very difficult to form a resist pattern of deep submicron or smaller. In the case of forming a fine contact hole, for example, with a g-line exposure wavelength using a conventional photomask, the limit is to form a contact hole having a diameter of about 0.5 μm. Therefore, a so-called phase shift method has been proposed in which a resist pattern is formed by combining different phase amplitudes in the exposure step of forming the resist pattern.

However, in the phase shift method, when the photomask is manufactured, it is necessary to perform a computer simulation on the phase of the exposure light passing through the mask, which makes the mask design very complicated. Also on the photomask substrate,
It is difficult to form a shifter that shifts the phase uniformly. In particular, it is difficult to make the film thickness of the shifter uniform when the shifter is formed on the step portion of the light shielding pattern of the photomask. Therefore, it is difficult to obtain the phase shift as designed. Further, since the shape of the base is easily affected during exposure, the effect of the phase shift may not be sufficiently exhibited due to reflection due to unevenness of the base, for example. As a result, the resolution of the formed resist pattern is lowered and it becomes difficult to form a fine pattern.
In this way, it is very difficult to form a fine pattern of deep submicron level or less,
In particular, it is very difficult to form an integrated circuit in which the gates of transistors are highly integrated and laterally mounted on a mass production level.

An object of the present invention is to provide a deep sub-micron or smaller MOS transistor manufactured by a stable processing technique and a manufacturing method thereof.

[0010]

SUMMARY OF THE INVENTION The present invention is a MOS transistor and a method for manufacturing the same made to achieve the above object. That is, as a MOS transistor,
A groove formed on a semiconductor substrate, a side wall on one side of the groove and a bottom surface of the groove on the side wall on the one side;
Gate insulating film, the first gate provided on the surface of the first gate insulating film, and the first source / drain region formed in the upper layer of the semiconductor substrate on the side of the first gate insulating film with respect to the groove. A second gate insulating film provided on the other side wall of the groove and a bottom surface of the groove on the other side wall side; and a second gate provided on the surface of the second gate insulating film. A second source / drain region formed in the upper layer of the semiconductor substrate on the side of the second gate insulating film with respect to the groove, and a third layer formed in the upper layer of the semiconductor substrate between the first gate and the second gate.
Source / drain regions.

As a method of manufacturing the MOS transistor, a groove is formed in the semiconductor substrate in the first step. Next, in a second step, an insulating film and a film for forming a gate are formed on at least the inner wall of the groove. Then, by etching back, for example, the first and second gates are formed on the sidewall side of the groove with a film that forms the gate via the insulating film, and the insulating film is formed on the back surface side of the first and second gates. Then, the first and second gate insulating films are formed. Then, in a third step, conductive impurities are introduced into the upper layer of the semiconductor substrate to form first, second and third source / drain regions.

As another MOS transistor,
First and second source / drain regions are formed in an upper layer and a lower layer of the semiconductor portion provided in the upper layer of the insulating substrate,
The first and second gates are formed on both side walls of the semiconductor portion via the first and second gate insulating films, respectively.

As another method of manufacturing a MOS transistor, in the first step, a semiconductor portion is provided on a substrate. Second
In the step of, after forming a film for forming an insulating film and a gate on at least the entire surface of the side wall of the semiconductor portion, for example, by etching back, on both side walls of the semiconductor portion, through the insulating film,
First and second gates are formed of a film forming the gate.
Further, first and second gate insulating films are formed of an insulating film on the semiconductor portion side of the first and second gates. Then, in a third step, conductive impurities are introduced into the upper layer of the semiconductor portion to provide first source / drain regions. Then in the fourth step,
After forming the insulating substrate on the side of the first source / drain region, the substrate is removed. Then, in a fifth step, conductive impurities are introduced into the lower layer of the first semiconductor portion to provide second source / drain regions.

Further, in the above-mentioned another MOS transistor, an interlayer insulating film is provided on the second source / drain region side of the MOS transistor, and the second insulating film is formed through the interlayer insulating film.
Form the surface wiring to connect to the source / drain region of
Further, a back surface wiring connected to the first source / drain region of the MOS transistor is formed via an insulating substrate provided on the back surface side of the MOS transistor.

[0015]

In the above MOS transistor, since the gate of the MOS transistor is formed on the sidewall of the groove formed in the semiconductor substrate, the depth of the groove and the film thickness of the gate cause M
The channel length of the OS transistor is determined. Therefore, the formation area of the MOS transistor on the semiconductor substrate surface becomes small. In this method of manufacturing a MOS transistor, the gate and the gate insulating film formed in the groove provided in the semiconductor substrate are formed in a so-called self-alignment manner. Therefore, the channel length is determined by the thickness of the film forming the gate and the amount of etch back.

In another MOS transistor, the semiconductor portion is formed on the upper layer of the insulating base and the gate of the MOS transistor is provided on the side wall of the insulating base. Therefore, the gate of the MOS transistor extends in the depth direction with respect to the surface of the insulating base. It is formed. Therefore, the formation area of the MOS transistor on the surface of the insulating substrate is reduced. The channel length of the MOS transistor is determined by the height of the semiconductor portion, for example. In this MOS transistor manufacturing method, the gate and the gate insulating film formed in the semiconductor portion on the substrate are formed in a so-called self-aligned manner. For this reason, it is not necessary to consider the mask alignment margin and the like in the design, so that the area where the gate is formed on the surface of the insulating base becomes small.

Further, a backside wiring connecting to the first source / drain region of the MOS transistor provided with the semiconductor portion is provided on the insulating substrate surface, and a front surface wiring connecting to the second source / drain region is provided on the interlayer insulating film surface. By providing the above-mentioned structure, it becomes easy to flatten another interlayer insulating film formed on the surface wiring, for example.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the figure, a semiconductor substrate (for example, a single crystal silicon substrate) 11 has an element isolation region 12, 1
3 is formed. A groove 14 is formed on the upper layer side of the semiconductor substrate 11 between the element isolation regions 12 and 13.
A first gate insulating film 17 is formed on the side wall 15 on one side of the groove 14 and on the bottom surface 16 of the groove 14 on the side wall 15 side. The first gate insulating film 17 is made of, for example, silicon oxide. A first gate 18 is formed on the surface of the first gate insulating film 17 so as not to contact the semiconductor substrate 11. This first gate 18
For example, it is made of polycrystalline silicon.

A first source / drain region 19 is formed in the upper layer of the semiconductor substrate 11 on the side of the first gate insulating film 17 with respect to the groove 14. This first source
In the drain region 19, the MOS transistor 1 has a PMO
In the case of the S transistor, for example, boron (B ⁺ ) is introduced as a conductive impurity. Alternatively, when the MOS transistor 1 is an NMOS transistor, phosphorus (P ⁺ ) is introduced as a conductive impurity, for example.

On the other hand, a second gate insulating film 22 is formed on the side wall 20 on the other side of the groove 14 and on the bottom surface 21 of the groove 14 on the side wall 20 side. This second gate insulating film 22
Is made of, for example, silicon oxide. A second gate 23 is formed on the surface of the second gate insulating film 22 so as not to contact the semiconductor substrate 11. The second gate 23 is made of, for example, polycrystalline silicon.

A second source / drain region 24 is formed in the upper layer of the semiconductor substrate 11 on the side of the second gate insulating film 22 with respect to the groove 14. Further, a third source / drain region 25 is formed in the upper layer of the semiconductor substrate 11 between the first gate 18 and the second gate 23. Each of the second and third source / drain regions 24, 2
In the case where the MOS transistors 1 and 2 are PMOS, for example, 5 has boron (B ⁺ ) introduced as a conductive impurity. Alternatively, the MOS transistors 1 and 2 are NMOS
In this case, phosphorus (P ⁺ ) is introduced as a conductive impurity, for example.

As described above, the dual gate type MO
S transistors 1 and 2 are formed. That is, the above M
The OS transistor 1 includes the first gate insulating film 17 and the first gate insulating film 17.
Gate 18, first source / drain region 19 and third
Source / drain regions 25 of Also MOS
The transistor 2 includes a second gate insulating film 22, a second gate 23, a second source / drain region 24, and a third source / drain region 25. Therefore, the third source / drain region 25 is shared by the MOS transistors 1 and 2.

In the MOS transistors 1 and 2, the first and second gates 18 and 23 are formed on the sidewalls 15 and 20 of the groove 14 formed in the semiconductor substrate 11, respectively. , And the film thicknesses of the second gates 18 and 23 determine the channel lengths L of the MOS transistors 1 and 2. That is, the MOS transistor 1
Has a total channel length L from the source / drain region 19 to the third source / drain region 25 along the side wall 15 and the bottom surface 16 of the groove 14. Also, the total channel length L of the MOS transistor 2 is determined similarly to the MOS transistor 1. Thus, the first and
Since the second gates 18 and 23 are formed, when the plurality of first and second gates 18 and 23 are laterally arranged, the formation area of the MOS transistors 1 and 2 becomes small.

On the first, second and third source / drain regions 19, 24, 25, for example, SALICI
It is also possible to provide a low resistance layer (not shown) of DE. In the above case, as compared with the case where the low resistance layer is not formed, the first, second and third source / drain regions 1 are formed.
Since the resistance values of 9, 24 and 25 are about 1/10 or less, the operating speed of the MOS transistors 1 and 2 is particularly high.

Next, a method of manufacturing the MOS transistor of the first embodiment will be described with reference to the manufacturing process diagram shown in FIG. As shown in (1) of FIG. 2, for example, a normal LOCO
Element isolation regions 12 and 13 are formed in a part of the upper layer of the semiconductor substrate (for example, a single crystal silicon substrate) 11 by the S oxidation method. Next, as a first step, a groove 14 is formed in the upper layer of the semiconductor substrate 11 between the element isolation regions 12 and 13 by the existing photolithography and dry etching. The etching is performed by microwave plasma etching, for example. As an etching condition at this time, for example, a mixed gas of trichlorotrifluoroethane (C ₂ Cl ₃ F ₃ ) having a flow rate of 60 sccm and sulfur hexafluoride (SF ₆ ) having a flow rate of 10 sccm is used as an etching gas, and a micro gas is used. The wave power is set to 850 W, the RF power is set to 150 W, and the pressure of the etching atmosphere is set to 1.33 Pa.

Next, surface oxidation for removing a damaged layer (not shown) generated on the semiconductor substrate 11 by the above dry etching is performed. The surface oxidation conditions are:
For example, the temperature atmosphere is 850 ° C and the flow rate is 1.5 SLM.
Of hydrogen (H ₂ ) and oxygen (O ₂ ) having a flow rate of 6 SLM. Then, for example, the surface oxidation is performed until a silicon oxide film (not shown) having a thickness of 30 nm is formed on the surface layer of the semiconductor substrate 11. After that, the silicon oxide film is removed by immersing it in diluted hydrofluoric acid for about 1 minute, for example.

Next, the second step is performed. In this process,
First, as shown in FIG. 2B, a silicon oxide film, for example, having a thickness of 16 nm is formed as the insulating film 31 on the surface of the semiconductor substrate 11 by, for example, a normal thermal oxidation method. The thermal oxidation condition at this time is, for example, a temperature atmosphere of 85.
Hydrogen (H ₂ ) with a flow rate of 6 sccm and a flow rate of 4 s at 0 ° C.
It is left in a mixed gas with ccm of oxygen (O ₂ ). Then, thermal oxidation is performed until a silicon oxide film having a thickness of 16 nm is formed on the surface layer of the semiconductor substrate 11.

Then, a film 32 for forming a gate is formed on the entire surface of the insulating film 31 side. The film 32 forming this gate is, for example, a polycrystalline silicon film having a thickness of 200 nm and a tungsten silicide (WS) having a thickness of 100 nm.
i ₂ ) film. The polycrystalline silicon film is formed by, for example, a chemical vapor deposition method. The film forming conditions at this time are, for example, a reaction gas flow rate of 500.
Sccm of silane (SiH ₄ ) and flow rate of 0.35 scc
A mixed gas of phosphine (PH ₃ ) of m and hydrogen (H ₂ ) having a flow rate of 50 sccm is used, the film forming temperature is set to 580 ° C., and the pressure of the film forming atmosphere is set to 79.8 Pa. The tungsten silicide film is formed by, for example, a chemical vapor deposition method. The film forming conditions are, for example, tungsten hexafluoride (W
F ₆ ) and silane (SiH ₄ ) with a flow rate of 1000 sccm
And a mixed gas of helium (He) with a flow rate of 360 sccm, a film forming temperature of 360 ° C., and a film forming atmosphere pressure of 2
Set to 6.6 Pa.

Thereafter, as shown in FIG. 2C, the film 3 for forming the gate is formed by, for example, dry etching.
2 and the insulating film 31 are etched back to remove the part of the film 32 forming the gate indicated by the two-dot chain line and the part of the insulating film 31 indicated by the one-dot chain line. Then, on the side wall 15 on one side of the groove 14 and the bottom surface 16 on the side wall 15 side, the first gate 18 is formed with the film 32 forming a gate via the insulating film 31. At the same time, the other side wall 20 of the groove 14 is formed.
A second gate 23 is formed on the bottom surface 21 on the side wall 20 side by the film 32 forming a gate with the insulating film 31 interposed therebetween. As the etching conditions for the film 32 forming the gate, for example, the flow rate of the etching gas is 65 sccc.
m trichlorotrifluoroethane (C ₂ Cl ₃ F ₃ ).
And a mixed gas of sulfur hexafluoride (SF ₆ ) with a flow rate of 5 sccm and an etching atmosphere pressure of 1.33 P
a, microwave power 100W, RF power 100
Set to W.

Further, a first gate insulating film 17 is formed of an insulating film 31 on the back surface side of the first gate 18. At the same time, the second gate insulating film 22 is formed of the insulating film 31 on the back surface side of the second gate 23. The etching conditions for the insulating film 31 are, for example, an etching gas flow rate of 50 sc.
cm octafluorocyclobutane (C ₄ F ₈ ) is used, the pressure of the etching atmosphere is set to 2 Pa, and the RF power is set to 1.2 kW.

Next, as a third step, as shown in FIG. 2D, the element isolation region 1 is formed by a normal ion implantation method.
2, 13 and first and second gates 18, 23 and first and second gates
Using the gate insulating films 17 and 22 of 1 as an ion implantation mask, conductive impurities are ion-implanted into the upper layer of the semiconductor substrate 11. Then, the first source / drain region 1 is formed in the upper layer of the semiconductor substrate 11 on the first gate insulating film 17 side with respect to the groove 14.
9 is formed, and second source / drain regions 24 are formed in the upper layer of the semiconductor substrate 11 on the second gate insulating film 22 side with respect to the trench 14. At the same time, the first gate 1
A third source / drain region 25 is formed in the upper layer of the semiconductor substrate 11 between the gate electrode 8 and the second gate 23.

As an ion implantation condition, when an NMOS transistor is formed, for example, arsenic (As ⁺ ) is used as a conductive impurity and the ion implantation energy is 50.
KeV and dose amount are set to 5 × 10 ¹⁵ / cm ² . Alternatively, when forming a PMOS transistor, for example, boron difluoride (BF ₂ ⁺ ) is used as a conductive impurity, the ion implantation energy is 20 keV, and the dose amount is 3 ×.
It is set to 10 ¹⁵ / cm ² . The MOS transistors 1 and 2 are formed as described above.

In the manufacturing method described with reference to FIG. 2 above, the film 32 forming the gate is etched back to form the first and second gates 18 and 23. Therefore, by controlling the etching amount, each MOS transistor is controlled. It is possible to determine the total channel length L of 1,2.

Next, a method of controlling the total channel length L of each of the MOS transistors 1 and 2 will be described with reference to FIGS. In FIG. 3, the MOS transistor 1 will be described as a representative example. As shown in FIG. 3, the total channel length L is
Side wall 15 of trench 14 from first source / drain region 19
And a third source / drain region 25 along the bottom surface 16
Up to the length. That is, the total channel length L is equal to the groove 1
4 is the sum of the channel length La on the side wall 15 side and the channel length Lb on the bottom surface 16 side of the groove 14. One of the methods of determining the total channel length L is a method of controlling the channel length Lb. That is, the channel length Lb is controlled by the film thickness of the film (32) forming the gate and the etch back amount thereof. The channel length L of the MOS transistor 2 can be controlled in the same manner as in the case of the MOS transistor 1 described above.

Next, an example of a control method of the channel length Lb will be described.
It will be described with reference to the relationship diagram between the channel length Lb and the film thickness of the film forming the gate in FIG. The vertical axis of FIG. 4 indicates the channel length Lb
The horizontal axis in the figure represents the film thickness of the film forming the gate. As shown in the figure, the channel length Lb becomes longer as the film 32 (see FIG. 2) forming the gate becomes thicker. At this time, the etching rate of the film (32) forming the gate is 300 nm / min. Therefore, when the film (32) forming the gate has a film thickness of 400 nm, the channel length Lb is formed to about 230 nm by etching back.

Further, in order to precisely control the channel length Lb, the film (32) forming the gate may be over-etched. An example of the relationship between the channel length Lb and the overetching time in this case will be described with reference to FIG. The vertical axis of FIG. 5 represents the channel length Lb, and the horizontal axis of the same figure represents the over-etching time of the film (32) forming the gate. The over-etching was performed after removing all the portions formed on the plane of the film (32) forming the gate having a thickness of 400 nm. As shown in the figure, as the over-etching time becomes longer, the channel length Lb becomes shorter. Therefore, for example, in order to form the channel length Lb to 180 nm, overetching may be performed for 10 seconds.

As described above, the film (3
The channel length Lb can be controlled by the film thickness of 2). Further, the channel length Lb can be accurately controlled by overetching the film (32) forming the gate.

The total channel length L can also be controlled by changing the channel length La. That is, the first and second source / drain regions (19),
By changing the depth of (24), the channel length La
It becomes possible to control. The channel length La is also determined by the depth of the groove (14). By controlling the channel length L as described above, it becomes possible to form the MOS transistors 1 and 2 having the channel length L of a dimension of deep submicron or less.

Next, the wiring of the MOS transistors 1 and 2 described in the first embodiment will be described with reference to the schematic sectional view of FIG. As shown in the figure, an interlayer insulating film 33 is formed so as to cover the MOS transistors 1 and 2. First, second,
Contact holes 34, 35, 36 are provided in the interlayer insulating film 33 on the third source / drain regions 19, 24, 25. Electrodes 37, 3 connected to the first to third source / drain regions 19, 24, 25 on the interlayer insulating film 33 via the contact holes 34-36, respectively.
8, 39 are formed.

A method of forming the electrodes 37 to 39 will be described. For example, the chemical vapor deposition method is used to cover the MOS transistors 1 and 2 with the interlayer insulating film 33, for example, 5
A film is formed to a thickness of 00 nm. As the film forming conditions at this time, for example, a mixed gas of silane (SiH ₄ ) having a flow rate of 250 sccm, oxygen (O ₂ ) having a flow rate of 250 sccm, and nitrogen (N ₂ ) having a flow rate of 100 sccm is used as a reaction gas, The film forming temperature is 420 ° C., and the pressure is 13.3 in the film forming atmosphere.
Set to Pa.

Then, contact holes 34, 35 and 36 are formed in the interlayer insulating film 33 on the first, second and third source / drain regions 19, 24 and 25 by ordinary photolithography and etching. Then, an electrode forming layer (not shown) is formed by, for example, a sputtering method.
This electrode forming layer is made of, for example, titanium (T
i) Film and titanium nitride oxide (TiO 2) with a thickness of 100 nm
N) a barrier metal layer consisting of a film and a thickness of 800 nm
% Aluminum (Al) layer containing silicon (Si).

As the sputtering conditions for the titanium film, for example, the sputtering gas is argon (A) with a flow rate of 40 sccm.
Using r), the pressure of the sputtering atmosphere is set to 0.4 Pa, the DC sputtering power is set to 1 kW, and the sputtering rate is set to 90 nm / min. As the sputtering conditions for the titanium oxynitride film, for example, a mixed gas of nitrogen (N ₂ ) having a flow rate of 47 sccm and oxygen (O ₂ ) having a flow rate of 3 sccm is used as the sputtering gas, the DC sputtering power is 3 kW, and the sputtering rate is Is set to 60 nm / min. 1% silicon (Si)
As the sputtering conditions for the aluminum (Al) layer containing, for example, argon (Ar) with a flow rate of 40 sccm is used as the sputtering gas, the DC sputtering power is set to 6 kW, and the sputtering rate is set to 800 nm / min.

After that, the contact holes 34, 35, 3 are formed by ordinary photolithography and etching.
Via the first to third source / drain regions 1
Electrodes 37 to 39 connected to 9, 24 and 25 are formed of the electrode forming layer. As an apparatus for etching the electrode forming layer, for example, an RF application type ECR etching apparatus is used. The etching conditions are, for example, boron trichloride (BCl ₃ ) with an etching gas flow rate of 60 sccm.
And chlorine (Cl ₂ ) with a flow rate of 90 sccm, microwave power of 1 kW and RF power of 50
W and the pressure of the etching atmosphere are set to 2.13 Pa.

In the method of manufacturing the MOS transistors 1 and 2, each source / drain is formed by forming a low resistance layer on the first, second and third source / drain regions 19, 24, 25. The sheet resistance of the regions 19, 24 and 25 can be set to 5Ω / □ or less. At the same time, the contact resistance between the source / drain regions 19, 24, 25 and the electrodes 37 to 39 can be set to 10Ω or less.

A method of forming a low resistance layer in the first to third source / drain regions 19, 24 and 25 will be described below.
This will be described with reference to manufacturing process diagrams (No. 1) and (No. 2) of FIGS. After forming the film 32 for forming the gate as described in (2) of FIG. 2 above, as shown in (1) of FIG. 7, for example, a film for forming a gate by a normal chemical vapor deposition method. An insulating film 41 is formed on the surface of 32, for example, 300 n
The film is formed to a thickness of m. The insulating film 41 is made of, for example, silicon oxide. The film forming conditions at this time are, for example, silane (SiH
₄ ) and oxygen (O ₂ ) with a flow rate of 250 sccm and a flow rate of 1
A mixed gas containing 00 sccm of nitrogen (N ₂ ) was used, the film forming temperature was 420 ° C., and the pressure of the film forming atmosphere was 13.3.
Set to Pa.

Then, as shown in FIG. 7B, the insulating film 41, the gate forming film 32, and the insulating film 31 are etched back by, for example, dry etching, which is shown by a chain double-dashed line of the insulating film 41. Film 32 forming part and gate
The portion indicated by the alternate long and short dash line and the portion indicated by the broken line of the insulating film 31 are removed. The first gate 18 made of a film 32 forming a gate is formed on the side wall 15 on one side of the groove 14 and the bottom surface 16 on the side wall 15 side with the insulating film 31 interposed therebetween.
To form. At the same time, on the other side wall 20 of the groove 14 and the bottom surface 21 on the side wall 20 side, the second gate 23 made of a film 32 forming a gate is provided with the insulating film 31 interposed therebetween.
To form. At this time, each of the first and second gates 18 and 2
Gate sidewalls 42 and 43 made of an insulating film 41 are formed on the front surface side of 3. Further, the first gate insulating film 17 is formed of the insulating film 31 on the back surface side of the first gate 18. At the same time, the second gate insulating film 22 is formed of the insulating film 31 on the back surface side of the second gate 23.

As the etching conditions for the insulating film 41 and the insulating film 31, for example, the flow rate of the etching gas is 50 s.
Using octafluorocyclobutane (C ₄ F ₈ ) of ccm, the pressure of the etching atmosphere is set to 2 Pa and the RF power is set to 1 kW. The etching conditions for the film 32 forming the gate are, for example, trichlorotrifluoroethane (C
₂ Cl ₃ F ₃₎ and flow rate using a mixed gas of sulfur hexafluoride (SF ₆₎ of 5 sccm, 1.33 Pa pressure of the etching atmosphere, the microwave power 100W, RF
Set the power to 100W.

Then, as described in (4) of FIG. 2 above, as shown in (3) of FIG. 7, conductive impurities are ion-implanted into the upper layer of the semiconductor substrate 11 by a normal ion implantation method. .. Then, the first source / drain regions 19 are formed in the upper layer of the semiconductor substrate 11 on the side of the first gate insulating film 17 with respect to the groove 14, and the semiconductor substrate on the side of the second gate insulating film 22 with respect to the groove 14 is formed. Second source / drain regions 24 are formed in the upper layer of 11. At the same time, the semiconductor substrate 11 between the first gate 18 and the second gate 23 is
A third source / drain region 25 is formed in the upper layer.

Then, as shown in FIG. 8 (4), each of the first and second gates 18, 18 is formed by, for example, a chemical vapor deposition method.
A silicon nitride (SiN) film 44 is formed to a thickness of, for example, 30 nm on the entire surface on the 23 side. The film forming conditions at this time are, for example, dichlorosilane (SiH ₂ Cl ₂ ) having a flow rate of 50 sccm and 200 sccm for the reaction gas.
Of ammonia (NH ₃ ) and nitrogen (N ₂ ) with a flow rate of 200 sccm are used, the film forming temperature is set to 760 ° C., and the pressure of the film forming atmosphere is set to 70 Pa. Instead of the silicon nitride film 44, for example, an insulating film such as a silicon nitride oxide (SiOxN) film containing a large amount of hydrogen can be used.

Subsequently, the portions indicated by the chain double-dashed line of the silicon nitride film 44 are removed by ordinary photolithography and etching to remove the first and second gates 18, 23.
Mask patterns 45 and 46 made of the silicon nitride film 44 are formed on the upper surface. The etching conditions include
For example, trifluoromethane (CHF ₃ ) with a flow rate of 50 sccm is used as the etching gas, and the RF power is set to 300.
W and the pressure of the etching atmosphere are set to 2 Pa.

Thereafter, as shown in FIG. 8 (5), a titanium (Ti) film 47 is formed to a thickness of, for example, 30 nm on the entire surface on the mask pattern 45, 46 side by, for example, a sputtering method. As the sputtering conditions at this time, for example, argon (Ar) is used as the sputtering gas, the RF bias is −50 V, the DC sputtering power is 1 kW, the flow rate of argon is 40 sccm, and the pressure of the sputtering atmosphere is 0.
The film formation temperature is set to 4 Pa, the film formation temperature is set to 200 ° C., and the film formation rate is set to 60 nm / min.

Then, as shown in FIG. 8 (6), RTA (Rapid Thermal Annealing) treatment is performed in an inert gas to form titanium in the titanium film 47 and the first to third source / drain regions 19, 24 ,. 25 silicon is reacted with silicidation to form the first to third source / drain regions 1
Titanium silicide (TiSi) is formed on each of the upper layers of 9, 24, and 25.
₂ ) The low resistance layers 48, 49, 50 made of ₂ ) are formed. As the condition of the RTA, for example, a temperature atmosphere of 650 is used.
C., RTA time set to 30 seconds.

Subsequently, the unreacted titanium film 47 (the portion indicated by the chain double-dashed line) is removed by wet etching by immersing it in ammonia-hydrogen peroxide mixture. Next, RTA is performed for 30 seconds in an inert gas [for example, nitrogen (N ₂ )] at 900 ° C. to stabilize the low resistance layers 48, 49 and 50. In this manner, the low resistance layers 48 to 50 are formed on the upper layers of the first to third source / drain regions 19, 24 and 25, respectively.

Although the low resistance layers 48 to 50 are formed of titanium silicide, other silicides such as cobalt silicide (CoSi ₂ ), tungsten silicide (WSi ₂ ), molybdenum silicide (MoSi ₂ ).
Etc.] or a metal film of selective tungsten (W) or the like. The method of forming electrodes in each of the first to third source / drain regions 19, 24 and 25 of the MOS transistors 1 and 2 in which the low resistance layers 48 to 50 are formed is the same as that described with reference to FIG. According to the method.

Next, a second embodiment of the present invention will be described with reference to the schematic cross-sectional view of FIG. As shown in the figure, a semiconductor portion 52 is provided on the upper layer of an insulating substrate (for example, a substrate made of silicon oxide) 51 so that its surface is exposed. The semiconductor section 52 is made of, for example, single crystal silicon. A first gate insulating film 54 is formed on the sidewall 53 on one side of the semiconductor portion 52. This first gate insulating film 54
Is made of, for example, silicon oxide. Further, the semiconductor section 52
On the surface of the first gate insulating film 54 opposite to the first side, the first
Gate 55 is formed. This first gate 55
Is made of, for example, polycrystalline silicon.

The side wall 56 on the other side of the semiconductor section 52 is also provided.
A second gate insulating film 57 is formed on the. The second gate insulating film 57 is made of, for example, silicon oxide. Further, a second gate 58 is formed on the surface of the second gate insulating film 57 opposite to the semiconductor portion 52 side. The second gate 58 is made of, for example, polycrystalline silicon.

Further, first source / drain regions 59 are formed in the lower layer of the semiconductor section 52. This first
In the source / drain region 59, when the MOS transistors 3 and 4 are PMOS transistors, for example, boron (B ⁺ ) is introduced as a conductive impurity. Alternatively, when the MOS transistors 3 and 4 are NMOS transistors, phosphorus (P ⁺ ) is introduced as a conductive impurity, for example. Second source / drain regions 60 are formed in the upper layer of the semiconductor section 52. This second
When the MOS transistors 3 and 4 are PMOS transistors, for example, boron (B ⁺ ) is introduced into the source / drain region 60 as a conductive impurity. Alternatively, when the MOS transistors 3 and 4 are NMOS transistors, phosphorus (P ⁺ ) is introduced as a conductive impurity, for example.

As described above, the MOS transistors 3,
4 is formed. That is, the MOS transistor 3
Is the first gate insulating film 54, the first gate 55, and the first gate insulating film 54.
And a second source / drain region 60. Further, the MOS transistor 4 includes a second gate insulating film 57, a second gate 58, a first source / drain region 59, and a second source / drain region 6.
It consists of 0. Therefore, the first and second source / drain regions 59 and 60 are shared by the MOS transistors 3 and 4. In this way, the MOS transistors 3 and 4
Has a MOS transistor structure having a dual gate, so that the drive capability of transistor characteristics is high.

Further, in the MOS transistors 3 and 4, the first and second gates 55 and 58 are formed on the side walls 53 and 56 of the semiconductor portion 52 via the first and second gate insulating films 54 and 57, respectively, and Since the first and second source / drain regions 59 and 60 are formed in the upper layer and the lower layer of the portion 52, the thickness of the semiconductor portion 52 and the first and second source / drain regions 59 and 60 of the semiconductor portion 52 are reduced. The channel length L of each of the MOS transistors 3 and 4 is determined by the depth. Therefore, the channels of the MOS transistors 3 and 4 are formed in the depth direction of the semiconductor portion 52.

Therefore, as shown in FIG. 10, it is possible to laterally dispose a plurality of the MOS transistors 3 and 4 above the insulating substrate 51. By arranging in this way, it becomes possible to mount the MOS transistors 3 and 4 in a highly integrated manner.

On the first and second source / drain regions 59 and 60 (see FIG. 9), for example, SALICI
It is also possible to provide a low resistance layer (not shown) made of DE. In this case, the resistance values of the first and second source / drain regions 59 and 60 are about 1/10 or less as compared with the case where the low resistance layer is not formed. The operation speed becomes faster.

Next, an example of a method of manufacturing the MOS transistor of the second embodiment will be described with reference to manufacturing process diagrams (1) and (2) of FIGS. Note that the drawing shows the manufacturing process when the MOS transistors are laterally arranged. Further, in the figure, the same numbers are given to the same components. As shown in (1) of FIG. 11, in the first step, the grooves 62, 63, 64 are formed in the upper layer of the substrate (for example, a single crystal silicon substrate) 61 by ordinary photolithography and etching, and the grooves are formed. The semiconductor portion 52 is formed between 62 and 63, and the semiconductor portion 52 similar to the above is formed between the grooves 63 and 64. The etching is performed by microwave plasma etching, for example. Since the etching conditions at this time are the same as those described in (1) of FIG. 2 in the first embodiment, the description thereof is omitted here.

Next, surface oxidation is performed to remove a damaged layer (not shown) generated on the substrate 61 by the dry etching. The conditions of this surface oxidation are the same as those described in (1) of FIG. 2 in the first embodiment, and therefore the description is omitted here. Then, it is immersed in diluted hydrofluoric acid for about 1 minute to remove the silicon oxide film formed by the surface oxidation.

Then, as shown in FIG. 11B, the second step is performed. In this step, first, an insulating film 65 of silicon oxide is formed on the entire surface of the semiconductor portion 52 side by a normal thermal oxidation method.
Is formed to have a thickness of 16 nm, for example. Since the thermal oxidation conditions at this time are the same as those described in (2) of FIG. 2 in the first embodiment, the description thereof is omitted here.

Then, a film 66 for forming a gate is formed on the entire surface of the insulating film 65 side. The film 66 for forming the gate is, for example, a polycrystalline silicon film having a thickness of 200 nm and a tungsten silicide (WS) having a thickness of 100 nm.
i ₂ ) film. The polycrystalline silicon film is formed by, for example, a chemical vapor deposition method. Since the film forming conditions at this time are the same as those described in (2) of FIG. 2 in the first embodiment, the description thereof is omitted here. The tungsten silicide film is formed by, for example, a chemical vapor deposition method. Since the film forming conditions are the same as those described in (2) of FIG. 2 in the first embodiment, the description is omitted here.

Thereafter, as shown in (3) of FIG. 11, the film 66 for forming the gate and the insulating film 65 are etched back by, for example, dry etching, and is indicated by a chain double-dashed line of the film 66 for forming the gate. The portion and the portion of the insulating film 65 indicated by the alternate long and short dash line are removed. Then, the first gate 55 is formed on the side wall 53 on one side of the semiconductor portion 52 with the film 66 forming a gate with the insulating film 65 interposed therebetween. At the same time, a second gate 58 is formed on the other side wall 56 of the semiconductor portion 52 with a film 66 that forms a gate, with an insulating film 65 interposed therebetween. Further, the insulating film 6 is formed on the back surface side of the first gate 55.
At 5, the first gate insulating film 54 is formed. At the same time, the second
A second gate insulating film 57 is formed of an insulating film 65 on the back surface side of the gate 58 of FIG. The above etching conditions are the same as those described in (3) of FIG. 2 in the first embodiment, and therefore the description thereof is omitted here.

Then, as a third step, as shown in FIG. 11 (4), the first and second gates 55 and 58 and the first and second gate insulating films 54 and 5 are formed by a normal ion implantation method.
7 is used as an ion implantation mask to ion-implant conductive impurities into the upper layer of the semiconductor portion 52. Then, the first source / drain regions 59 are formed in the upper layer of the semiconductor portion 52. At the same time, conductive impurities are ion-implanted into the upper layer of the substrate 61 between the semiconductor parts 52, 52. The ion implantation conditions are the same as those described with reference to (4) of FIG. 2 in the first embodiment, and therefore the description thereof is omitted here.

Then, as shown in (5) of FIG.
In the step of, the silicon oxide film 67 is formed on the entire surface of the semiconductor portion 52 side by, for example, 500 by a normal chemical vapor deposition method.
The film is formed to a thickness of nm. Then, the silicon oxide film 6 is formed.
A resist is applied to the upper surface of 7 to form a resist film (not shown) having a flat surface.

Next, the resist is removed by etching back, and the upper layer of the silicon oxide film 67 is removed to flatten the surface of the silicon oxide film 67. The etch back at this time is, for example, ECR of bias application.
It is performed by an etching device. As an etching condition, for example, a mixed gas of silane (SiH ₄ ) having a flow rate of 14 sccm, nitrous oxide (N ₂ O) having a flow rate of 35 sccm, and argon (Ar) having a flow rate of 72 sccm is used as an etching gas. Wave power 1kW,
The RF power is set to 450 W, the etching temperature is set to 400 ° C., and the etching atmosphere pressure is set to 0.133 Pa. The silicon oxide film 67 whose surface is flattened is the insulating substrate 5.
Becomes 1. Therefore, hereinafter, the silicon oxide film 67 is referred to as the insulating base 51.

Next, a polycrystalline silicon film 68 is formed on the upper surface of the insulating substrate 51 by, for example, low pressure chemical vapor deposition.
For example, the film is formed to a thickness of 200 nm. The film forming conditions at this time are, for example, a reaction gas flow rate of 500 sccm.
Silane (SiH ₄ ) and phosphine (PH ₃ ) with a flow rate of 0.35 sccm and helium (H
e) using a mixed gas consisting of
The pressure of the film forming atmosphere is set to 79.8 Pa.

Subsequently, the surface of the polycrystalline silicon film 68 is flattened by polishing (for example, polishing), and then the single crystal silicon substrate 69 is bonded. Single crystal silicon substrate 6
To bond 9 together, a normal heat treatment (for example, 1000
Bonding by heating to ℃).

Thereafter, as shown in (6) of FIG. 12, the semiconductor portion 52 is exposed in a so-called island shape on the surface layer of the insulating substrate 51, for example, by grinding and polishing to remove the 2 of the substrate 61.
The part indicated by the dotted chain line is removed. In addition, in FIG.
The drawings (6) and (7) are shown in a state where the state shown in (5) of FIG. 12 is reversed.

Next, as shown in (7) of FIG. 12, as a fifth step, conductive impurities are ion-implanted into the upper layer of the semiconductor section 52 by, for example, a normal ion implantation method, and the second step is performed.
Source / drain regions 60 are formed. Since the ion implantation conditions at this time are the same as those described in (4) of FIG. 2 in the first embodiment, the description thereof is omitted here.

As described above, the first gate insulating film 54
And the first gate 55 and the source / drain regions 60 and 59
And form a MOS transistor 3. In addition, the second gate insulating film 57, the second gate 58, the source,
The drain regions 60 and 59 form the MOS transistor 4.

In the manufacturing method of the second embodiment, a bonding type SOI substrate is used. For this reason, no junction leak occurs in each of the MOS transistors 3 and 4, so that the MOS transistors 3 and 4 have excellent electrical characteristics and reliability is improved.

The channel dimensions of the MOS transistors 3 and 4 can be controlled by the height of the semiconductor portion 52 and the depths of the first and second source / drain regions 59 and 60. That is, as shown in (1) of FIG. 11, the semiconductor portion 52 has the grooves 62 to 6 formed in the substrate 61.
Determined by a depth of 4. In addition, (4) in FIG.
As shown in FIG. 7, the depth of the first source / drain region 59 is determined by the implantation depth of the conductive impurities at the time of ion implantation and the subsequent heat step (for example, heat treatment at the time of bonding the single crystal silicon substrate 69). It Further, as shown in (7) of FIG. 12, the depth of the second source / drain regions 60 is determined by the implantation depth of the conductive impurities at the time of ion implantation and the subsequent heat step (for example, sintering of aluminum wiring in the wiring step). Processing).

Next, a wiring example of the MOS transistors 3 and 4 will be described with reference to the schematic sectional view of FIG. As shown in the figure, an interlayer insulating film 71 is formed so as to cover the MOS transistors 3 and 4. A contact hole 72 is provided in the interlayer insulating film 71 on the second source / drain region 60. An electrode 73 connected to the second source / drain region 60 is formed on the interlayer insulating film 71 via the contact hole 72.

A method of forming the electrode 73 will be described. First, for example, by chemical vapor deposition, the interlayer insulating film 71 is formed in a state of covering the MOS transistors 3 and 4 by, for example, 500.
The film is formed to a thickness of nm. Since the film forming conditions at this time are the same as those described with reference to FIG. 6, the description thereof is omitted here.

Then, a contact hole 72 is formed in the interlayer insulating film 71 on the second source / drain region 60 by ordinary photolithography and etching. Then, an electrode forming layer (not shown) is formed by, for example, a sputtering method. This electrode forming layer has a thickness of 50, for example.
nm titanium (Ti) film, 100 nm thick titanium nitride oxide (TiON) film as a barrier metal layer, and 800 nm thick aluminum (Al) layer containing 1% silicon (Si) are formed in a laminated state. It was done. The sputtering conditions for the titanium film, the titanium nitride oxide film, the aluminum (Al) layer containing 1% silicon (Si), etc. are the same as those described with reference to FIG.

After that, an electrode 73 connected to the second source / drain region 60 through the contact hole 72 is formed in the electrode forming layer by the usual photolithography and etching. As an apparatus for etching the electrode forming layer, for example, an RF application type ECR etching apparatus is used. Since the etching conditions are the same as those described with reference to FIG. 6, the description thereof is omitted here.

Next, as a third embodiment, an example of the wiring structure in which the MOS transistors 3 and 4 described in FIG. 9 are laterally arranged will be described with reference to FIG. As shown in the figure, MOS transistors 3 and 4 and MOS transistors 5 and 6 having the same structure are provided on the upper layer of the insulating substrate 51.
And are formed. Therefore, the same numbers are given to similar components. An interlayer insulating film 81 is formed on the entire surface of each of the MOS transistors 3, 4, 5, 6 on the side of the second source / drain region 60. This interlayer insulating film 81 is
For example, it is made of silicon oxide.

Insulating substrate 51 below the first source / drain regions 59 of the MOS transistors 3 and 4.
A contact hole 82 is provided in the. A back surface wiring 83 is formed in a state of being connected to the first source / drain region 59 through the contact hole 82. A contact hole 84 is provided in the interlayer insulating film 81 above the second source / drain regions 60 of the MOS transistors 5 and 6. A surface wiring 85 is formed in a state of being connected to the second source / drain region 60 through the contact hole 84.

As described above, by forming the back surface wiring 83 connected to the first source / drain region 59,
It is possible to reduce the number of wirings formed on the surface.
Therefore, when the multilayer wiring is formed, the step difference due to the wiring is reduced, and the reliability of the wiring is improved. Although not shown in the drawing, the same surface wiring (8) as described above is also applied to the second source / drain regions 60 of the MOS transistors 3 and 4.
5) can be formed. Further, it is possible to form the back wiring (83) similar to the above also in the first source / drain regions 59 of the MOS transistors 5 and 6.
On the back wiring 83 side, a polycrystalline silicon film (not shown) whose surface is flattened is formed via an insulating film (not shown), and a silicon substrate (not shown) is formed on the polycrystalline silicon film. It is also possible to bond so that a so-called SOI structure is formed.

Next, a method of manufacturing the above wiring structure will be described with reference to FIG.
Manufacturing process drawing of the wiring structure of FIG. 16 (Part 1), (Part 2)
Will be described. In this manufacturing method, a case where a low resistance layer is formed in the second source / drain regions will be described as an example. As shown in (1) of FIG. 15, in the same manner as described in (4) of FIG.
After the first source / drain regions 59 are formed on the first source / drain regions 59, the first silicon oxide film 91 is formed on the entire surface on the side of the first source / drain regions 59 by the same method as described in (5) of FIG. Is formed into a film having a thickness of, for example, 500 nm.
Subsequently, a resist is applied on the upper surface of the first silicon oxide film 91 to form a resist film (not shown) having a flat surface.

Then, the resist is removed by etching back, and the upper layer of the first silicon oxide film 91 is removed to planarize the surface of the first silicon oxide film 91. The etch-back conditions at this time are the same as those described with reference to (5) of FIG. 12, and thus description thereof will be omitted here. The first silicon oxide film 91 whose surface is flattened becomes a part of the insulating base 51. The surface of the first silicon oxide film 91 does not necessarily have to be flattened.

Then, a contact hole 82 is formed in the silicon oxide film 91 on one of the first source / drain regions 59, for example, by ordinary photolithography and etching. As the etching conditions at this time, for example, octafluorocyclobutane (C ₄ F ₈ ) having a flow rate of 50 sccm is used as the etching gas, the RF power is set to 1.2 kW, and the etching atmosphere pressure is set to 2 Pa.

Then, the inside of the contact hole 82 and the first silicon oxide film 91 are formed by a normal sputtering method.
A titanium nitride (TiN) film 92 is formed on the upper surface of the
It is formed to a thickness of 0 nm. Then, a tungsten (W) film 93 is formed on the upper surface of the titanium nitride film to a thickness of, for example, 300 nm by a normal chemical vapor deposition method.
The titanium nitride film 92 and the tungsten film 93 become the backside wiring forming layer 94. The titanium nitride (TiN) film is formed under the conditions, for example, that the sputtering gas is nitrogen (N).
₂ ) is used, the pressure of the sputtering atmosphere is set to 0.5 Pa, the DC sputtering power is set to 3 kW, and the sputtering rate is set to 60 nm / min. As the film forming conditions for the tungsten (W) film, for example, a mixed gas of tungsten hexafluoride (WF ₆ ) having a flow rate of 95 sccm and helium (He) having a flow rate of 550 sccm is used as a reaction gas. 45
The pressure of the film forming atmosphere is set to 0 ° C. and 10.64 kPa.

Thereafter, the portions indicated by the two-dot chain line and the portion indicated by the one-dot chain line of the back surface wiring forming layer 94 are removed by ordinary photolithography and etching, and the back surface wiring 83 is formed.
To form. As the etching conditions at this time, for example, sulfur hexafluoride (SF ₆ ) having a flow rate of 50 sccm is used, the microwave power is 850 W, and the RF power is 10
Set to 0W.

Then, as shown in (2) of FIG. 15, a second silicon oxide film 95 having a thickness of, for example, 500 nm is formed on the entire surface on the back wiring 83 side by the same method as described in (5) of FIG. The film is formed to a thickness. Subsequently, a resist is applied on the upper surface of the second silicon oxide film 95 to form a resist film (not shown) having a flat surface. Then, the resist is removed by etching back, and the upper layer of the second silicon oxide film 95 is further removed to flatten the surface of the second silicon oxide film 95. The etch-back conditions at this time are the same as those described with reference to (5) of FIG. 12, and thus description thereof will be omitted here. The second silicon oxide film 95 whose surface is flattened and the first silicon oxide film 91 form the insulating base 51.

Then, the polycrystalline silicon film 6 is formed on the upper surface of the insulating substrate 51 in the same manner as described with reference to FIG.
8 is deposited to a thickness of 200 nm, for example. Subsequently, the surface of the polycrystalline silicon film 68 is flattened by polishing (for example, polishing), and then a single crystal silicon substrate 69 is attached.

Thereafter, as shown in (3) of FIG.
In the same manner as described in (6) above, the substrate 61 is removed by, for example, grinding and polishing so that the semiconductor portion 52 is exposed on the upper layer of the insulating substrate 51 in a so-called island shape. Note that in FIG. 16, the drawing of (3) corresponds to the above-mentioned FIG.
The state shown in (2) of 5 is shown in an inverted state. Further, the illustration of the polycrystalline silicon film 68 and the single crystal silicon substrate 69 described in (2) of FIG. 15 is omitted.

Next, as shown in (4) of FIG. 16, a titanium (Ti) film 96 is formed to a thickness of, for example, 30 nm on the entire surface of the semiconductor section 52 side by a normal sputtering method.
As the sputtering conditions at this time, for example, argon (Ar) having a flow rate of 40 sccm is used as the sputtering gas, and R
F bias -50V, DC sputter power 1kW,
Sputtering atmosphere pressure is 0.4 Pa, film formation temperature is 200
C. and sputter rate are set to 60 nm / min. Note that FIG.
(4) of FIG. 17 and (5) and (6) of FIG. 17 described below.
In the above, the illustration of the polycrystalline silicon film 68 and the single crystal silicon substrate 69 is omitted.

Then, as shown in (5) of FIG.
Then, the titanium of the titanium film 96 and the silicon of each of the semiconductor portions 52 are silicidized to form a low resistance layer 97 of titanium silicide (TiSi ₂ ). Then, the unreacted titanium film 96 (portion indicated by a chain double-dashed line) is removed by immersing in an ammonia-hydrogen peroxide mixture. Then 900
The low resistance layers 97 are stabilized by leaving them in an inert gas (for example, nitrogen (N ₂ )) at 30 ° C. for 30 seconds. The low resistance layer 9
7 is formed of titanium silicide, other silicides such as cobalt silicide (CoSi ₂ ), tungsten (WSi ₂ ), molybdenum silicide (MoSi) are used.
₂ ) etc.] or a metal film of selective tungsten (W) or the like.

Then, in the same manner as described in (7) of FIG. 12, each semiconductor portion 5 is formed by the normal ion implantation method.
A second source / drain region 60 is formed by ion-implanting a conductive impurity into the upper layer of 2 through the low resistance layer 97. Since the ion implantation conditions at this time are the same as those described in (4) of FIG. 2 in the first embodiment, the description thereof is omitted here.

Next, as shown in (6) of FIG. 17, an interlayer insulating film 81 made of a silicon oxide film is formed on the entire surface where the low resistance layer 97 is formed by, for example, a chemical vapor deposition method.
Is formed to have a thickness of, for example, 500 nm. Since the film forming conditions at this time are the same as those described with reference to FIG. 6, the description thereof is omitted here. Then, the MOS transistors 5 and 6 are formed by ordinary photolithography and etching.
A contact hole 84 is formed in the interlayer insulating film 81 on the low resistance layer 97. Since the etching conditions at this time are the same as those described with reference to FIG. 6, the description thereof is omitted here.

Next, a surface wiring forming film 98 is formed inside the contact hole 84 and on the interlayer insulating film 81.
The surface wiring forming film 98 is formed of, for example, a titanium (Ti) film having a thickness of 50 nm, a barrier metal layer made of titanium nitride oxide (TiOxN) having a thickness of 100 nm, and an aluminum layer containing 1% of silicon. After that, the portion indicated by the chain double-dashed line of the surface wiring forming layer 98 is removed by ordinary photolithography and etching.
The surface wiring 85 is formed. Since the etching conditions at this time are the same as those described with reference to FIG. 6, the description thereof is omitted here.

Although not shown in FIGS. 15 to 17,
It is possible to form the surface wiring (85) similar to the above in the second source / drain regions 60 of the MOS transistors 3 and 4. Also, in the first source / drain regions 59 of the MOS transistors 5 and 6, the same rear surface wiring (8
It is possible to form 3).

As described above, the back wiring 83 and the front wiring 8
By forming 5 and 5, it is not necessary to form a region for drawing out the first source / drain region 59 for each individual MOS transistor, so that the wiring area can be reduced. Further, since the number of wirings on the front surface side can be reduced, the flattening treatment on the front surface side becomes easy.

[0099]

As described above, according to the invention of claim 1, since the gate of the MOS transistor is formed on the side wall of the groove formed in the semiconductor substrate, the depth of the groove and the film thickness of the gate are changed. The channel length of the MOS transistor is determined. Therefore, the MOS for the semiconductor substrate surface
The formation area of the transistor can be reduced.
According to the invention of claim 2, the gate and the gate insulating film formed in the trench formed in the semiconductor substrate are formed in a so-called self-alignment manner. Therefore, the channel length can be determined by the thickness of the film forming the gate and the amount of the etch back thereof. According to the invention of claim 3, the semiconductor portion is formed on the insulating base, and the gate of the MOS transistor is formed on the side wall of the insulating base, so that the gate of the MOS transistor is formed in the depth direction with respect to the insulating base. Therefore, the formation area of the MOS transistor can be reduced. According to the invention of claim 4, the gate and the gate insulating film formed in the semiconductor portion are formed in a so-called self-alignment manner. For this reason, it is not necessary to consider the mask alignment margin and the like in the design, so that the formation area of the gate can be reduced. According to the invention of claim 5, since the back surface wiring connecting to the first source / drain region of the MOS transistor provided in the semiconductor portion is provided on the insulating substrate surface, the number of wirings on the front surface wiring side can be reduced. Therefore, it becomes easy to flatten the interlayer insulating film formed on the surface wiring. Therefore, the reliability of the wiring can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of a first embodiment.

FIG. 2 is a manufacturing process diagram of the first embodiment.

FIG. 3 is an explanatory diagram of a channel length.

FIG. 4 is a relationship diagram between a channel length Lb and a film thickness of a film forming a gate.

FIG. 5 is a relationship diagram between a channel length Lb and overetching time.

FIG. 6 is a schematic cross-sectional view of the wiring of the first embodiment.

FIG. 7 is a manufacturing process diagram (1) of the low resistance layer.

FIG. 8 is a manufacturing process diagram (2) of the low resistance layer.

FIG. 9 is a schematic configuration sectional view of a second embodiment.

FIG. 10 is a schematic cross-sectional view in which the MOS transistors of the second embodiment are laterally arranged.

FIG. 11 is a manufacturing process diagram (1) of the second embodiment.

FIG. 12 is a manufacturing process diagram (2) of the second embodiment.

FIG. 13 is a schematic cross-sectional view of the wiring of the second embodiment.

FIG. 14 is a schematic sectional view of a third embodiment.

FIG. 15 is a manufacturing process diagram (1) of a wiring structure.

FIG. 16 is a manufacturing process diagram (2) of the wiring structure.

FIG. 17 is a manufacturing process diagram (3) of the wiring structure.

FIG. 18 is a schematic configuration sectional view of a conventional example.

FIG. 19 is a manufacturing process diagram of a conventional example.

[Explanation of symbols]

1 MOS Transistor 2 MOS Transistor 3 MOS Transistor 4 MOS Transistor 5 MOS Transistor 6 MOS Transistor 11 Semiconductor Substrate (eg Single Crystal Silicon Substrate) 14 Groove 15 Sidewall 16 Bottom 17 First Gate Insulating Film 18 First Gate 19 First Source / drain region 20 Side wall 21 Bottom face 22 Second gate insulating film 23 Second gate 24 Second source / drain region 25 Third source / drain region 31 Insulating film 32 Gate forming film 51 Insulating substrate 52 Semiconductor part 53 Side wall 54 First gate insulating film 55 First gate 56 Side wall 57 Second gate insulating film 58 Second gate 59 First source / drain region 60 Second source / drain region 61 Substrate 65 Insulation Membrane 66 Membrane forming gate 81 During insulating film 83 backside interconnect 85 surface wiring

Claims (5)

[Claims] 1. A trench formed in a semiconductor substrate, a first gate insulating film provided on a side wall of the trench on one side and a bottom surface of the trench on the side wall of the one side, and the first gate insulating film. A first gate provided on the surface of the film, a first source / drain region formed in an upper layer of the semiconductor substrate on the first gate insulating film side with respect to the groove, and a sidewall on the other side of the groove And a second gate insulating film provided on the bottom surface of the groove on the other side wall side, a second gate provided on the surface of the second gate insulating film, and the second gate insulating film with respect to the groove. Second source / drain region formed in the upper layer of the semiconductor substrate on the side of the gate insulating film, and a third source formed in the upper layer of the semiconductor substrate between the first gate and the second gate. .MOS transistor characterized by comprising a drain region Register. 2. A first step of forming a groove in a semiconductor substrate, and a step of forming an insulating film and a film for forming a gate on at least an inner wall of the groove so as to be stacked and then etching back the groove. A first gate is formed on the side wall on one side and the bottom surface of the groove on the side wall on the one side by the film forming the gate via the insulating film, and the side wall on the other side of the groove and the other side. A second gate is formed on the bottom surface of the groove on the side wall side of the first gate with a film forming the gate via the insulating film, and then on the back surface side of the first gate with the first insulating film. A second step of forming a gate insulating film and forming a second gate insulating film with the insulating film on the back surface side of the second gate; and a step of forming a second gate insulating film with respect to the groove on the first gate insulating film side. Introducing conductive impurities into the upper layer of the semiconductor substrate And forming a second source / drain region by introducing a conductive impurity into the upper layer of the semiconductor substrate on the side of the second gate insulating film with respect to the groove, and forming the second source / drain region. By introducing a conductive impurity into the upper layer of the semiconductor substrate between the first gate and the second gate, a third source
A method of manufacturing a MOS transistor, comprising a third step of forming a drain region. 3. A semiconductor portion provided in an upper layer of an insulating substrate, a first gate insulating film provided on one side wall of the semiconductor portion, and the first gate insulating material opposite to the semiconductor portion. A first gate provided on the film surface, a second gate insulating film provided on the other side wall of the semiconductor portion, and a second gate insulating film provided on the second gate insulating film surface opposite to the semiconductor portion. 2. A MOS transistor comprising a second gate, a first source / drain region provided in an upper layer of the semiconductor section, and a second source / drain region provided in a lower layer of the semiconductor section. 4. A first step of providing a semiconductor portion on a substrate, and after forming an insulating film and a film for forming a gate on a sidewall of the semiconductor portion in a stacked state, at least one side of the semiconductor portion A first gate is formed on the side wall of the semiconductor film through the insulating film, and a second gate is formed on the other side wall of the semiconductor portion via the insulating film. And then, using the insulating film, a first gate insulating film is formed on the semiconductor portion side of the first gate, and a second gate insulating film is formed on the semiconductor portion side of the second gate. A second step; a third step of introducing a conductive impurity into the upper layer of the semiconductor portion to form a first source / drain region; and an insulating substrate on the entire surface on the side of the first source / drain region. After forming, the fourth substrate is removed. And a fourth step of providing a second source / drain region by introducing a conductive impurity into the first semiconductor portion on the side opposite to the side on which the first source / drain region is formed. And a method for manufacturing a MOS transistor. 5. The MOS transistor according to claim 3, wherein the interlayer insulating film provided on the second source / drain region side of the MOS transistor and the second source / drain region via the interlayer insulating film. To the first source of the MOS transistor via a front surface wiring connected to the MOS transistor and an insulating substrate formed on the back surface side of the MOS transistor.
A MOS transistor having a backside wiring connected to a drain region.