JPH0837296A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0837296A JPH0837296A JP17391494A JP17391494A JPH0837296A JP H0837296 A JPH0837296 A JP H0837296A JP 17391494 A JP17391494 A JP 17391494A JP 17391494 A JP17391494 A JP 17391494A JP H0837296 A JPH0837296 A JP H0837296A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- film
- groove
- gate wiring
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910021332 silicide Inorganic materials 0.000 claims description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 16
- 239000000463 material Substances 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052710 silicon Inorganic materials 0.000 abstract description 7
- 239000010703 silicon Substances 0.000 abstract description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/66583—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、微細配線構造を有する
半導体装置の製造方法に係り、特に半導体集積回路基板
上に絶縁ゲート型電界効果トランジスタ（ＭＯＳ ＦＥ
Ｔ）を形成する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a fine wiring structure, and more particularly to an insulated gate field effect transistor (MOS FE) on a semiconductor integrated circuit substrate.
T).
【０００２】[0002]
【従来の技術】従来のＭＯＳ ＦＥＴの形成方法の一例
について、図３（ａ）乃至（ｅ）および図４（ａ）乃至
（ｄ）を参照しながら説明する。まず、ｐ型シリコン基
板３１上にゲート絶縁膜３２を熱酸化法により形成す
る。次に、ゲート絶縁膜３２上にゲート配線（電極兼
用）の多結晶シリコン３３とシリコン窒化膜３４を順次
堆積する。2. Description of the Related Art An example of a conventional method for forming a MOS FET will be described with reference to FIGS. 3 (a) to 3 (e) and FIGS. 4 (a) to 4 (d). First, the gate insulating film 32 is formed on the p-type silicon substrate 31 by a thermal oxidation method. Next, on the gate insulating film 32, a polycrystalline silicon 33 for a gate wiring (also serving as an electrode) and a silicon nitride film 34 are sequentially deposited.
【０００３】次に、シリコン窒化膜３４上にゲート配線
形成用のレジストパターン３５を形成する。次に、上記
レジストパターン３５をマスクとして、異方性エッチン
グ法によりシリコン窒化膜３４および多結晶シリコン３
３を加工した後、レジストパターン３５を除去すること
により、ゲート配線３６を形成する。Next, a resist pattern 35 for forming a gate wiring is formed on the silicon nitride film 34. Next, using the resist pattern 35 as a mask, the silicon nitride film 34 and the polycrystalline silicon 3 are formed by an anisotropic etching method.
After processing 3, the resist pattern 35 is removed to form the gate wiring 36.
【０００４】次に、上記ゲート配線３６をマスクとして
低濃度のＰ（リン）をイオン注入する。次に、全面にシ
リコン窒化膜３７を堆積する。次に、全面エッチバック
を行うことにより、ゲート配線３６の側壁にシリコン窒
化膜３７からなるスペーサー３７ａを形成する。次に、
高濃度のＰをイオン注入した後、注入した不純物をアニ
ール（熱処理）により活性化することにより、ＭＯＳ
ＦＥＴのソース・ドレイン領域３８を形成する。Next, low concentration P (phosphorus) is ion-implanted using the gate wiring 36 as a mask. Next, a silicon nitride film 37 is deposited on the entire surface. Next, the entire surface is etched back to form a spacer 37a made of the silicon nitride film 37 on the side wall of the gate wiring 36. next,
After ion-implanting high-concentration P, the implanted impurities are activated by annealing (heat treatment).
Source / drain regions 38 of the FET are formed.
【０００５】ところで、上記したようにゲート配線３６
を形成した後にゲート配線３６をイオン注入マスクとし
てイオン注入によりソース・ドレイン拡散層３８を形成
する場合、イオン注入した不純物を活性化させるため、
８００℃以上の高温での熱処理が必要となる。By the way, as described above, the gate wiring 36
When the source / drain diffusion layer 38 is formed by ion implantation using the gate wiring 36 as an ion implantation mask after the formation of, the ion implanted impurities are activated.
Heat treatment at a high temperature of 800 ° C. or higher is required.
【０００６】従って、ゲート配線３６の材料としては、
多結晶シリコン３３のように高温に耐えられる材料が用
いられるが、このようなゲート配線材料は、ゲート配線
幅の微細化に伴って高抵抗化が問題となってきている。Therefore, as the material of the gate wiring 36,
A material such as polycrystalline silicon 33 that can withstand high temperature is used, but such a gate wiring material has a problem of high resistance as the gate wiring width becomes finer.
【０００７】また、上記したようにゲート配線３６を形
成する際、下地となる半導体基板３１に素子分離膜やト
レンチキャパシタ等による段差が存在する場合であっ
て、このような段差箇所をゲート配線３６が通る場合に
は、段差箇所にゲート配線３６のエッチング残りが発生
し、ゲート配線３６間のショートを引き起こし易い。In addition, when the gate wiring 36 is formed as described above, there is a step due to an element isolation film, a trench capacitor, or the like on the underlying semiconductor substrate 31, and such a step portion is located at the gate wiring 36. When passing through, the etching residue of the gate wiring 36 is generated at the step portion, and it is easy to cause a short circuit between the gate wirings 36.
【０００８】[0008]
【発明が解決しようとする課題】上記したように従来の
ＭＯＳ ＦＥＴの形成方法は、ゲート配線形成後にソー
ス・ドレイン拡散層形成に伴うイオン注入不純物活性化
のための高温での熱処理を必要とするので、ゲート配線
材料として耐高温性が要求され、ゲート配線幅の微細化
に伴ってゲート配線の高抵抗化が問題となってきてい
る。As described above, the conventional method for forming a MOS FET requires heat treatment at a high temperature for activating the ion-implanted impurities accompanying the formation of the source / drain diffusion layers after forming the gate wiring. Therefore, high temperature resistance is required as the gate wiring material, and the increase in resistance of the gate wiring has become a problem with the miniaturization of the gate wiring width.
【０００９】本発明は上記の問題点を解決すべくなされ
たもので、ＭＯＳ ＦＥＴのソース・ドレイン拡散層形
成後にゲート配線を形成することにより、ゲート配線材
料に対する耐高温性の要求が緩和され、ゲート配線幅の
微細化に伴うゲート配線の高抵抗化を抑制し得る半導体
装置の製造方法を提供することを目的とする。The present invention has been made to solve the above problems. By forming the gate wiring after forming the source / drain diffusion layer of the MOS FET, the requirement for high temperature resistance of the gate wiring material is relaxed. An object of the present invention is to provide a method for manufacturing a semiconductor device, which can suppress the increase in resistance of the gate wiring due to the miniaturization of the gate wiring width.
【００１０】[0010]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に、上記半導体基板と異なる導
電型を持つ第１の不純物を含む第１の絶縁膜を堆積する
工程と、上記第１の絶縁膜を加工して前記半導体基板に
達する溝を形成する工程と、上記溝の底面の半導体基板
表面を酸化し、溝の底面に第２の絶縁膜を形成する工程
と、前記第１の絶縁膜中の第１の不純物を前記半導体基
板中に拡散させ、基板と異なる導電型の第１の拡散領域
を形成する工程と、前記第１の絶縁膜および第２の絶縁
膜の上に導電体層を堆積する工程と、前記溝内部の上記
導電体層を残し、前記第１の絶縁膜上の上記導電体層を
除去する工程とを具備することを特徴とする。A method of manufacturing a semiconductor device according to the present invention comprises a step of depositing, on a semiconductor substrate, a first insulating film containing a first impurity having a conductivity type different from that of the semiconductor substrate. A step of processing the first insulating film to form a groove reaching the semiconductor substrate; a step of oxidizing the bottom surface of the groove on the surface of the semiconductor substrate to form a second insulating film on the bottom surface of the groove; A step of diffusing a first impurity in a first insulating film into the semiconductor substrate to form a first diffusion region having a conductivity type different from that of the substrate; and a step of forming the first insulating film and the second insulating film. The method is characterized by comprising a step of depositing a conductor layer on the top and a step of leaving the conductor layer inside the groove and removing the conductor layer on the first insulating film.
【００１１】[0011]
【作用】本発明の半導体装置の製造方法によれば、ＭＯ
Ｓ ＦＥＴを形成する際に、不純物をドープした絶縁膜
にゲート配線埋込み用の溝を形成し、上記絶縁膜から半
導体基板へ不純物を拡散させることによりソース・ドレ
イン拡散層を形成した後に、ゲート配線を埋込み形成す
るので、ゲート配線材料に金属等の低抵抗の材料を用い
ることができる。また、ゲート配線間の絶縁膜を拡散源
としてソース・ドレイン拡散層をゲート配線と自己整合
した状態で形成することができる。According to the method of manufacturing a semiconductor device of the present invention, the MO
When forming an SFET, a trench for embedding a gate wiring is formed in an insulating film doped with an impurity, and a source / drain diffusion layer is formed by diffusing the impurity from the insulating film into a semiconductor substrate, and then a gate wiring is formed. Since it is embedded, a low resistance material such as metal can be used as the gate wiring material. Further, the source / drain diffusion layer can be formed in a state of being self-aligned with the gate wiring using the insulating film between the gate wirings as a diffusion source.
【００１２】[0012]
【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図１（ａ）乃至（ｅ）および図２（ａ）乃
至（ｄ）は、本発明の第１実施例に係るＭＯＳ ＦＥＴ
の形成方法の一例における主要工程でのウエハー断面を
示している。Embodiments of the present invention will be described below in detail with reference to the drawings. 1A to 1E and 2A to 2D are MOS FETs according to the first embodiment of the present invention.
3A to 3C are cross-sectional views of a wafer in the main process in one example of the forming method of FIG.
【００１３】まず、ｐ型Ｓｉ（シリコン）基板１０上に
基板と異なる導電型を持つ第１の不純物を含む第１の絶
縁膜を形成する。この第１の絶縁膜として、例えばＬＰ
−ＣＶＤ法（減圧気相成長法）により、ＰＳＧ膜（リン
・シリケートガラス膜）１２を４００ｎｍ程度堆積す
る。この場合、下地となるシリコン基板１０には、例え
ばフィールド酸化膜１１のような素子分離膜やトレンチ
キャパシタ等による段差が存在する場合を想定してい
る。First, a first insulating film containing a first impurity having a conductivity type different from that of the substrate is formed on a p-type Si (silicon) substrate 10. As the first insulating film, for example, LP
A PSG film (phosphorus / silicate glass film) 12 is deposited to a thickness of about 400 nm by the CVD method (pressure reduction vapor deposition method). In this case, it is assumed that the underlying silicon substrate 10 has a step due to an element isolation film such as the field oxide film 11 or a trench capacitor.
【００１４】次に、上記ＰＳＧ膜１２上にゲート配線形
成用のレジストパターン１３を形成する。次に、異方性
エッチング法、例えばＲＩＥ（反応性イオンエッチン
グ）法により前記ＰＳＧ膜１２をエッチングした後に前
記レジストパターン１３を除去することにより、ゲート
配線埋込み用の溝１４を形成する。Next, a resist pattern 13 for forming a gate wiring is formed on the PSG film 12. Next, the PSG film 12 is etched by an anisotropic etching method, for example, RIE (reactive ion etching) method, and then the resist pattern 13 is removed to form a groove 14 for burying the gate wiring.
【００１５】次に、ＬＰ−ＣＶＤ法により、基板上全面
に前記ＰＳＧ膜１２よりＰ（リン）濃度の薄いＰＳＧ膜
１５を１００ｎｍ程度堆積する。次に、上記ＰＳＧ膜１
５をエッチバックすることにより、前記溝１４の側壁に
スペーサー用ＰＳＧ膜１５ａを形成する（残存させ
る）。Then, a PSG film 15 having a P (phosphorus) concentration lower than that of the PSG film 12 is deposited to a thickness of about 100 nm on the entire surface of the substrate by the LP-CVD method. Next, the PSG film 1
By etching back 5, the spacer PSG film 15a is formed (remains) on the sidewall of the groove 14.
【００１６】次に、熱酸化法により、前記溝の底面のシ
リコン基板表面にゲート絶縁膜１７を形成する。次に、
熱拡散法により。前記ＰＳＧ膜１２からシリコン基板１
０中にＰを拡散させることにより、ソース・ドレイン領
域１８を形成する。この場合、前記ＰＳＧ膜１２からの
拡散によりｎ+ 層１８ａを、前記スペーサー用ＰＳＧ膜
１５ａからの拡散によりｎ- 層１８ｂを形成する。Next, a gate insulating film 17 is formed on the surface of the silicon substrate on the bottom surface of the groove by a thermal oxidation method. next,
By thermal diffusion method. Silicon substrate 1 from the PSG film 12
The source / drain regions 18 are formed by diffusing P into 0. In this case, an n + layer 18a is formed by diffusion from the PSG film 12, and an n- layer 18b is formed by diffusion from the spacer PSG film 15a.
【００１７】次に、基板上全面に金属等の低抵抗材料、
例えばＷ（タングステン）１９を６００ｎｍ程度堆積す
る。次に、ＣＭＰ（化学機械研磨）法により、前記Ｗ１
９、ＰＳＧ膜１２およびスペーサー用ＰＳＧ膜１５ａの
一部を研磨して除去することにより、Ｗの埋込みゲート
配線１９ａを形成する（残存させる）。Next, a low resistance material such as metal is formed on the entire surface of the substrate,
For example, W (tungsten) 19 is deposited to a thickness of about 600 nm. Next, by the CMP (chemical mechanical polishing) method, the W1
9, the PSG film 12 and a part of the PSG film 15a for spacers are polished and removed to form (remain) the buried gate wiring 19a of W.
【００１８】上記実施例のＭＯＳ ＦＥＴの形成方法に
よれば、ソース・ドレイン拡散層１８の形成後にゲート
配線１９ａを形成するので、ゲート配線材料に金属等の
低抵抗の材料を用いることができる。According to the method of forming a MOS FET of the above embodiment, since the gate wiring 19a is formed after the source / drain diffusion layer 18 is formed, a low resistance material such as metal can be used as the gate wiring material.
【００１９】また、ソース・ドレイン拡散層１８を形成
する１８ａ、１８ｂは、ゲート配線１９ａ間の絶縁膜１
２、１５ａを拡散源としているので、前記ゲート配線１
９ａと自己整合した状態で形成することができる。The source / drain diffusion layers 18 are formed by the insulating film 1 between the gate wirings 19a and 18b.
Since the diffusion sources 2 and 15a are used, the gate wiring 1
9a can be formed in a self-aligned state.
【００２０】さらに、前記ゲート配線１９ａが埋め込み
配線構造となっているので、ゲート配線１９ａ間のショ
ートを引き起こし難くなっている。なお、上記実施例で
は、溝１４の側壁にスペーサー用絶縁膜１５ａを形成す
るために基板上全面に絶縁膜１５を堆積する際、第１の
絶縁膜（本例ではＰＳＧ膜１２）より低い濃度の第１の
不純物（本例ではＰ）を含む絶縁膜（本例ではＰＳＧ膜
１５）を堆積したが、これに限らず、第１の不純物とは
異なる第２の不純物を含む絶縁膜を堆積するようにして
もよい。Further, since the gate wiring 19a has a buried wiring structure, it is difficult to cause a short circuit between the gate wirings 19a. In the above-described embodiment, when the insulating film 15 is deposited on the entire surface of the substrate in order to form the spacer insulating film 15a on the sidewall of the groove 14, the concentration lower than that of the first insulating film (PSG film 12 in this example) is used. The insulating film containing the first impurity (P in this example) (PSG film 15 in this example) was deposited, but not limited to this, an insulating film containing a second impurity different from the first impurity is deposited. You may do it.
【００２１】また、上記実施例では、ＰＳＧ膜１２、ス
ペーサー用ＰＳＧ膜１５ａ、ゲート絶縁膜１７の上に堆
積する導電体層として、Ｗを示したが、これに限らず、
他の金属（例えばアルミニウムＡｌ）膜、または、多結
晶シリコン膜と金属膜との積層膜、または、多結晶シリ
コン膜とシリサイド膜（ＷＳｉ、ＴｉＳｉなど）との積
層膜を用いてもよい。In the above embodiment, W is shown as the conductor layer deposited on the PSG film 12, the spacer PSG film 15a and the gate insulating film 17, but the present invention is not limited to this.
Another metal (for example, aluminum Al) film, a laminated film of a polycrystalline silicon film and a metal film, or a laminated film of a polycrystalline silicon film and a silicide film (WSi, TiSi, etc.) may be used.
【００２２】[0022]
【発明の効果】上述したように本発明の半導体装置の製
造方法によれば、ＭＯＳ ＦＥＴのソース・ドレイン拡
散層形成後にゲート配線を形成することにより、ゲート
配線材料に対する耐高温性の要求が緩和され、ゲート配
線幅の微細化に伴うゲート配線の高抵抗化を抑制するこ
とができる。As described above, according to the method for manufacturing a semiconductor device of the present invention, by forming the gate wiring after forming the source / drain diffusion layer of the MOS FET, the requirement for high temperature resistance to the gate wiring material is relaxed. Therefore, it is possible to suppress the increase in resistance of the gate wiring due to the miniaturization of the gate wiring width.
【図１】本発明の第１実施例に係るＭＯＳ ＦＥＴの形
成方法の一例における工程の一部を示すウエハーの断面
図。FIG. 1 is a sectional view of a wafer showing a part of the steps in an example of a method for forming a MOS FET according to a first embodiment of the present invention.
【図２】図１に続く工程を示す断面図。FIG. 2 is a cross-sectional view showing a step that follows FIG.
【図３】従来のＭＯＳ ＦＥＴの形成方法の一例におけ
る工程の一部を示すウエハーの断面図。FIG. 3 is a sectional view of a wafer showing a part of the steps in an example of a conventional method for forming a MOS FET.
【図４】図３に続く工程を示す断面図。FIG. 4 is a cross-sectional view showing a step that follows FIG.
１０…ｐ型Ｓｉ基板、１２…Ｐ濃度が高いＰＳＧ膜、１
３…レジストパターン、１４…ゲート配線用溝、１５…
Ｐ濃度が低いＰＳＧ膜、１５ａ…スペーサー用ＰＳＧ
膜、１７…ゲート絶縁膜、１８…ソース・ドレイン領
域、１８ａ…ｎ+ 拡散層、１８ｂ…ｎ- 拡散層、１９…
Ｗ、１９ａ…Ｗ埋め込みゲート配線。10 ... p-type Si substrate, 12 ... PSG film with high P concentration, 1
3 ... Resist pattern, 14 ... Gate wiring groove, 15 ...
PSG film with low P concentration, 15a ... PSG for spacer
Film, 17 ... Gate insulating film, 18 ... Source / drain region, 18a ... N + diffusion layer, 18b ... N- diffusion layer, 19 ...
W, 19a ... W embedded gate wiring.
Claims (4)
る導電型を持つ第１の不純物を含む第１の絶縁膜を堆積
する工程と、上記第１の絶縁膜を加工して前記半導体基
板に達する溝を形成する工程と、上記溝の底面の半導体
基板表面を酸化し、溝の底面に第２の絶縁膜を形成する
工程と、前記第１の絶縁膜中の第１の不純物を前記半導
体基板中に拡散させ、基板と異なる導電型の第１の拡散
領域を形成する工程と、前記第１の絶縁膜および第２の
絶縁膜の上に導電体層を堆積する工程と、前記溝内部の
上記導電体層を残し、前記第１の絶縁膜上の上記導電体
層を除去する工程とを具備することを特徴とする半導体
装置の製造方法。1. A step of depositing a first insulating film containing a first impurity having a conductivity type different from that of the semiconductor substrate on the semiconductor substrate, and processing the first insulating film to form the semiconductor substrate on the semiconductor substrate. Forming a reaching groove, oxidizing the bottom surface of the semiconductor substrate surface of the groove to form a second insulating film on the bottom surface of the groove, and removing the first impurity in the first insulating film from the semiconductor. Diffusing into the substrate to form a first diffusion region having a conductivity type different from that of the substrate, depositing a conductor layer on the first insulating film and the second insulating film, and inside the groove And removing the conductor layer on the first insulating film while leaving the conductor layer.
おいて、前記溝を形成する工程と前記第２の絶縁膜を形
成する工程との間で、さらに、前記第１の絶縁膜上およ
び溝の底部に第３の絶縁膜を堆積する工程と、上記溝の
側壁の第３の絶縁膜を残して、残りの第３の絶縁膜を除
去することにより溝の側壁にスペーサー用絶縁膜を形成
する工程とを具備することを特徴とする半導体装置の製
造方法。2. The method of manufacturing a semiconductor device according to claim 1, further comprising: between the step of forming the groove and the step of forming the second insulating film, further on the first insulating film and the groove. A step of depositing a third insulating film on the bottom of the groove, and the remaining third insulating film is removed by leaving the third insulating film on the side wall of the groove to form an insulating film for spacers on the side wall of the groove. A method of manufacturing a semiconductor device, comprising:
おいて、前記第３の絶縁膜を堆積する際、前記第１の絶
縁膜より低い濃度の第１の不純物を含む絶縁膜または第
１の不純物と異なる第２の不純物を含む絶縁膜を堆積
し、前記第１の絶縁膜中の第１の不純物を半導体基板中
に拡散させる際、スペーサー用絶縁膜から上記第１の不
純物または第２の不純物を半導体基板中に拡散させるこ
とにより、スペーサー用絶縁膜直下の半導体基板中に、
第１の拡散領域と同じ導電型で第１の拡散領域よりも導
電率の小さい第２の拡散領域を形成することを特徴とす
る半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein, when depositing the third insulating film, an insulating film or a first insulating film containing a first impurity having a lower concentration than that of the first insulating film. When depositing an insulating film containing a second impurity different from the impurity and diffusing the first impurity in the first insulating film into the semiconductor substrate, the first insulating film or the second impurity is removed from the spacer insulating film. By diffusing the impurities into the semiconductor substrate, the semiconductor substrate immediately below the insulating film for the spacer is
A method of manufacturing a semiconductor device, comprising forming a second diffusion region having the same conductivity type as that of the first diffusion region and a conductivity lower than that of the first diffusion region.
おいて、前記第１の絶縁膜上および第２の絶縁膜上に導
電体層を堆積する際、金属膜、または多結晶シリコン膜
と金属膜の積層膜、または、多結晶シリコン膜とシリサ
イド膜の積層膜を堆積することを特徴とする半導体装置
の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein when depositing a conductor layer on the first insulating film and the second insulating film, a metal film or a polycrystalline silicon film and a metal are used. A method of manufacturing a semiconductor device, comprising depositing a laminated film of films or a laminated film of a polycrystalline silicon film and a silicide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17391494A JPH0837296A (en) | 1994-07-26 | 1994-07-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17391494A JPH0837296A (en) | 1994-07-26 | 1994-07-26 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0837296A true JPH0837296A (en) | 1996-02-06 |
Family
ID=15969424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17391494A Pending JPH0837296A (en) | 1994-07-26 | 1994-07-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0837296A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100275115B1 (en) * | 1997-09-04 | 2000-12-15 | 김영환 | A method for forming storage dot and a method for fabricating single electron memory using the same |
| KR100296004B1 (en) * | 1996-12-26 | 2001-08-07 | 니시무로 타이죠 | Semiconductor device and method for manufacturing the same |
| KR100332125B1 (en) * | 1999-06-30 | 2002-04-10 | 박종섭 | Mothod of manufacturing a CMOS transistor |
| US6563178B2 (en) | 2000-03-29 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the device |
| US6661066B2 (en) | 1999-05-21 | 2003-12-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including inversely tapered gate electrode and manufacturing method thereof |
| US6713333B2 (en) | 2001-10-29 | 2004-03-30 | Nec Electronics Corporation | Method for fabricating a MOSFET |
| KR100453910B1 (en) * | 2003-01-30 | 2004-10-20 | 아남반도체 주식회사 | Fabrication method of MOS transistor |
| KR100613373B1 (en) * | 2004-08-03 | 2006-08-17 | 동부일렉트로닉스 주식회사 | Fabrication method of MOS transistor |
| JP2006352158A (en) * | 1996-07-12 | 2006-12-28 | Toshiba Corp | Method of manufacturing semiconductor device |
-
1994
- 1994-07-26 JP JP17391494A patent/JPH0837296A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006352158A (en) * | 1996-07-12 | 2006-12-28 | Toshiba Corp | Method of manufacturing semiconductor device |
| JP4580914B2 (en) * | 1996-07-12 | 2010-11-17 | 株式会社東芝 | Manufacturing method of semiconductor device |
| KR100296004B1 (en) * | 1996-12-26 | 2001-08-07 | 니시무로 타이죠 | Semiconductor device and method for manufacturing the same |
| KR100275115B1 (en) * | 1997-09-04 | 2000-12-15 | 김영환 | A method for forming storage dot and a method for fabricating single electron memory using the same |
| US6661066B2 (en) | 1999-05-21 | 2003-12-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including inversely tapered gate electrode and manufacturing method thereof |
| KR100332125B1 (en) * | 1999-06-30 | 2002-04-10 | 박종섭 | Mothod of manufacturing a CMOS transistor |
| US6563178B2 (en) | 2000-03-29 | 2003-05-13 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the device |
| US6713333B2 (en) | 2001-10-29 | 2004-03-30 | Nec Electronics Corporation | Method for fabricating a MOSFET |
| KR100453910B1 (en) * | 2003-01-30 | 2004-10-20 | 아남반도체 주식회사 | Fabrication method of MOS transistor |
| KR100613373B1 (en) * | 2004-08-03 | 2006-08-17 | 동부일렉트로닉스 주식회사 | Fabrication method of MOS transistor |
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