JP3608999B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device.SetIt relates to a manufacturing method.
[0002]
[Prior art]
Conventionally, as an element isolation method, a selective oxidation method represented by a LOCOS (Local Oxidation of Silicon) method and a STI (Shallow Trench Isolation) method are mainly used.
A plan view of a semiconductor device using these element isolation methods is shown in FIG. In the figure, 27 denotes a gate electrode, and 31 denotes a diffusion layer. The plan view is the same for both methods.
[0003]
FIG. 9A shows a cross-sectional view of the semiconductor device using the LOCOS method at the AA line position in FIG. 8, and FIG. 9B shows a cross-sectional view at the BB line position. In this semiconductor device, an element such as a transistor or a resistor including a gate oxide film 26, a gate electrode 27, and a diffusion layer 31 is formed on a silicon substrate 21, and a field oxide film 25 is formed to separate them. Further, the whole is covered with an interlayer insulating film 32.
[0004]
A method for manufacturing a semiconductor device using the LOCOS method will be described with reference to FIGS.
First, as shown in FIG. 10A, a silicon oxide film 22 and a silicon nitride film 23 are formed on a silicon substrate 21. Thereafter, after a photoresist film 24 is formed in a predetermined pattern by a photolithography technique, the silicon nitride film 23 is etched using this pattern as a mask.
[0005]
Next, as shown in FIG. 10B, after removing the photoresist film 24, thermal oxidation is performed to form a field oxide film 25. Next, as shown in FIG.
Next, as shown in FIG. 10C, a gate oxide film 26 is formed, and then a conductive film 27a made of a gate electrode material is deposited.
[0006]
As shown in FIGS. 10D and 10E, after a photoresist film 28 is applied and patterned into a predetermined shape, a gate electrode 27 is formed using this pattern as a mask.
Next, as shown in FIG. 10F, a photoresist film 29 is applied and patterned into a predetermined shape by a photolithography technique, and then impurities are ion-implanted 30 using this pattern and the gate electrode 27 as a mask. Then, the diffusion layer 31 is formed.
Thereafter, the photoresist film 29 is removed, and an interlayer insulating film 32 is formed as shown in FIG.
[0007]
Next, FIG. 11A shows a cross-sectional view of the semiconductor device using the STI method at the AA line position in FIG. 8, and FIG. 11B shows a cross-sectional view at the BB line position. In this semiconductor device, a trench is formed in the silicon substrate 21 in advance in order to isolate an element such as a transistor or a resistor composed of the gate oxide film 26, the gate electrode 27, and the diffusion layer 31 on the silicon substrate 21. It is embedded with an insulating film 35. Further, the whole is covered with an interlayer insulating film 32.
A method for manufacturing a semiconductor device using the STI method will be described with reference to FIGS.
[0008]
First, as shown in FIG. 12A, a silicon oxide film 22 is formed on a silicon substrate 21 by a thermal oxidation method, and a silicon nitride film 23 is further formed by a CVD method. Thereafter, a photoresist film 24 is formed in a predetermined pattern by photolithography, and then the silicon nitride film 23 is etched using this pattern as a mask.
[0009]
After removing the photoresist film 24, the silicon oxide film 22 and the silicon substrate 21 are etched in this order using the silicon nitride film 23 as a mask to form a trench 33 (see FIG. 12B). ).
Next, an oxide film 34 is formed on the inner wall of the trench 33 by thermal oxidation. Thereafter, an insulating film 35 is deposited by a CVD method (see FIG. 12C).
Next, the insulating film 35 is etched back by CMP (Chemical Mechanical Polishing) until the silicon nitride film 23 is exposed (see FIG. 12D).
[0010]
Thereafter, the insulating film 35 is etched to the surface of the silicon substrate 21 by isotropic etching, and the silicon nitride film 23 is further removed. Further, a gate electrode 27 is formed through the gate oxide film 26 (see FIG. 12E).
Next, as shown in FIG. 12F, a photoresist film 29 is formed in a predetermined pattern by photolithography, and impurities are ion-implanted 30 by using this pattern and the gate electrode 27 as a mask, thereby diffusing. Layer 31 is formed.
[0011]
After removing the photoresist film 29, as shown in FIG. 12G, an interlayer insulating film 32 is formed to form a semiconductor device.
A manufacturing example of a semiconductor device by the STI method is described in “Submicron Mechanical Planarized Salut Trench Isolation With Field Shells”, S. Lindenberger, et. al. 1991 Symposium of VLSI Technology Digest of Technical Papers, pp 89-90.
[0012]
[Problems to be solved by the invention]
However, the conventional element isolation method has the following problems.
A problem common to both methods is that if the gate oxide film is thin at the overlap between the source / drain region and the gate electrode, the gate-drain capacitance causes a delay time in the device, and as a result, the device speed can be increased. There is no problem.
When the LOCOS method is used, bird's beaks are formed when the field oxide film is formed, so that it is difficult to control the size of the element isolation region and to make the region finer. As a result, with the miniaturization, the short Chanel effect is likely to occur.
[0013]
Further, when the STI method is used, it is superior to the LOCOS method in terms of dimensional control and miniaturization, but there is a problem that the number of steps increases as described with reference to FIGS. Furthermore, although the oxide film in the element isolation region is etched to the same height as the gate region, it is difficult to make it completely the same height, resulting in a step. This step has a problem that an etching residue of the gate electrode material is easily generated when the gate electrode is formed. In addition, since an oxide film is buried in the trench formed in the element isolation region and then flattened by the CMP method, there is a problem that a leakage current is generated due to the stress due to the flattening and the insulator pressure is reduced. There is a fear.
[0015]
[Means for Solving the Problems]
ThusAccording to the present invention, a step of forming a diffusion layer to be a source / drain region on a surface layer of a semiconductor substrate;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
Forming a conductive film on the entire surface of the semiconductor substrate;
Etching the conductive film using a resist pattern to form a gate electrode on the gate region between the source / drain regions and on the end of the source / drain region;
Forming a gate insulating film made of an oxide film by removing the oxide film other than on the source / drain regions and the gate region to expose the semiconductor substrate;
Forming a groove in the semiconductor substrate using the resist pattern and an oxide film on the source / drain region as a mask;
A step of forming an element isolation region composed of an interlayer insulating film and an insulating film embedded in a groove by laminating an insulating film over the entire surface of the semiconductor substrate after removing the resist pattern; A manufacturing method is provided.
[0016]
According to the invention, a step of forming a gate electrode through a gate insulating film in a gate region on a semiconductor substrate;
Forming a diffusion layer to be a source / drain region on the surface layer of the semiconductor substrate using the gate electrode as a mask;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
Forming a gate insulating film made of an oxide film on the source / drain region by removing the oxide film other than on the source / drain region and the gate region to expose the semiconductor substrate;
Forming a groove in the semiconductor substrate using the resist pattern and an oxide film on the source / drain region as a mask;
A step of forming an element isolation region composed of an interlayer insulating film and an insulating film embedded in a groove by laminating an insulating film over the entire surface of the semiconductor substrate after removing the resist pattern; A manufacturing method is provided.
[0017]
Furthermore, according to the present invention, a step of forming a diffusion layer to be a source / drain region on a surface layer of a semiconductor substrate;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
Remove the oxide film except on the source / drain regions to expose the semiconductor substrateWorkAbout
Forming a groove in a semiconductor substrate around the source / drain region including the gate region using the oxide film on the source / drain region as a mask;
At least on the inner surface of the trench in the gate regionMade of oxide filmForming a conductive film over the entire surface of the semiconductor substrate after forming the gate insulating film;
Etching the conductive film using a resist pattern to form a gate electrode on the gate region between the source / drain regions and on the end of the source / drain region;
And a step of forming an element isolation region comprising an interlayer insulating film and an insulating film embedded in a trench other than the gate region by laminating an insulating film over the entire surface of the semiconductor substrate. Is provided.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the thickness of the oxide film on the diffusion layer is made thicker than the oxide film in other regions, and the semiconductor substrate in the element isolation region and the gate region is selectively etched using the difference in film thickness. This is one of the characteristics.
[0019]
According to the present invention, the oxide film on the diffusion layer is formed thicker than the oxide film on the element isolation region, and then the silicon substrate is selectively etched using the oxide film on the diffusion layer as a mask when forming the gate electrode. As a result, a trench is formed, and an element region is formed. Therefore, the number of steps can be greatly reduced as compared with the conventional STI method. In addition, since the gate-drain capacitance can be suppressed, the speed can be increased.
[0020]
Since an element isolation region is formed by etching using a pattern for forming a diffusion layer as a mask and then field oxidation is not performed, a bird's beak unlike the LOCOS method is not formed, and a finer semiconductor device can be provided.
Moreover, a groove | channel can be formed in areas other than a diffused layer by selectively etching a silicon substrate using a film thickness difference. If the gate electrode is formed so as to straddle the groove, the channel of the transistor is also formed on the sidewall of the groove, and the channel length can be made longer than the mask dimension. As a result, the short channel effect can be suppressed.
[0021]
Here, a general theory of accelerated oxidation capable of forming a thick oxide film on the diffusion layer will be described. Enhanced oxidation is a phenomenon in which the thickness of an oxide film on a semiconductor substrate doped with impurities at a high concentration becomes thicker than an undoped region in a region where an oxide film is formed. If the thickness of the target oxide film is Tox (t),
Tox²(T) + ATox (t) = B (t + t₀(1)
It is known that the following equation (1) holds. In this equation, A and B are rate constants, and A = Po₂× Kp / Kl, B = Po₂× Kp (Po₂Is the normalized oxidation partial pressure, Kl is the linear law oxidation coefficient, and Kp is the square law oxidation coefficient), t₀Is the correction time.
[0022]
In this formula (1), at low concentrations, Kp and Kl depend only on the oxidizing atmosphere and the crystal orientation of the substrate, so the thickness of the oxide film also depends on both. On the other hand, since Kp and Kl themselves increase at high concentrations, the thickness of the oxide film increases as the concentration increases. That is, when the oxide film is formed under the same conditions in the low concentration and high concentration regions, the latter film thickness can be increased.
The constituent members of the present invention will be described below.
[0023]
First, the semiconductor substrate that can be used in the present invention is not particularly limited, and a known substrate such as a silicon substrate can be used. This semiconductor substrate may have p-type and n-type conductivity types.
Next, a diffusion layer as a source / drain region is formed on the surface layer of the semiconductor substrate. The diffusion layer may have either p-type or n-type conductivity. Furthermore, the diffusion layer may be formed in the well. A region between the source / drain regions is referred to as a gate region. Further, a groove may be formed in the gate region.
[0024]
Next, a gate insulating film made of an oxide film is formed on the gate region and the end of the source / drain region on the gate region side. Here, as described above, it is preferable that a gate insulating film that is about 2 to 3 times thicker than the gate region is formed on the end of the source / drain region. Note that the gate insulating film on the source / drain region only needs to have at least an end portion thicker than the gate insulating film on the gate region, and the thickness of the portion other than the end portion is not particularly limited.
[0025]
Further, a gate electrode is formed on the gate insulating film in the gate region. The gate electrode is not particularly limited and can be formed using a known material. For example, metals such as aluminum and copper, polysilicon, silicide of polysilicon and a refractory metal (titanium, tungsten, etc.), and the like can be used as the gate electrode material. The gate electrode may be a laminate of these materials.
[0026]
Next, a trench as an element isolation region in which an insulating film is embedded is formed in the semiconductor substrate around the source / drain region and the gate region. The insulating film is made of a silicon oxide film, a silicon nitride film, or a laminate thereof.
Hereinafter, the present invention will be described in more detail with reference to embodiments. In the following embodiments, an n-channel transistor is described using a P-type substrate. However, a similar manufacturing method can be used with a p-channel transistor using an n-type substrate, and similar effects can be obtained.
[0027]
(Embodiment 1)
1 is a plan view of the semiconductor device of the present invention, FIG. 2 (a) is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 2 (b) is taken along the line BB in FIG. FIG. 2A and 2B show a configuration according to the first embodiment.
[0028]
2A and 2B, the main part of the semiconductor device has an n-type diffusion layer 5 formed on a p-type silicon substrate 1 as a source / drain region and a region such as a resistor. A gate electrode 7 is formed on the silicon substrate 1 via a gate oxide film 6. On the n-type diffusion layer 5, an oxide film 9 thickened by accelerated oxidation is formed. In a region other than the gate electrode 7 and the n-type diffusion layer 5, the silicon substrate 1 is dug to form a groove 10. The groove 10 is simultaneously filled with the element isolation region when the interlayer insulating film 11 is formed.
A method for manufacturing the semiconductor device will be described with reference to process cross-sectional views in FIGS.
[0029]
First, as shown in FIG. 3A, a silicon oxide film as an insulating film 2 is formed on a p-type silicon substrate 1 in a high temperature oxygen atmosphere with a thickness of about 100 to 200 mm. Thereafter, a photoresist film 3 is formed into a pattern of a source / drain region and a region to be a resistance by a photolithography technique. Using this pattern as a mask, an n-type impurity such as arsenic (As) is implanted at an energy of 10 to 80 KeV and a dose of 3 × 10.¹⁵cm^-2The diffusion layer 5 is formed by ion implantation 4 under the conditions of about.
[0030]
Next, as shown in FIG. 3B, after removing the photoresist film 3 and the insulating film 2, thermal oxidation is performed in a high-temperature oxygen atmosphere, so that a thickness of about 30 to 300 mm is obtained in a region other than the diffusion layer. A gate oxide film 6 is formed. At this time, a thick gate oxide film 6 is formed on the diffusion layer into which the impurity is implanted at a high concentration by accelerated oxidation as compared with a region other than the diffusion layer.
More specifically, for example, when oxidation is performed in an HCl atmosphere at 900 ° C., the film thickness D in a region other than the diffusion layer in FIG.₁Is formed on the diffusion layer 5 in which impurities are ion-implanted at a high concentration.₂Is formed.
[0031]
Next, as shown in FIG. 3C, as a gate electrode material for forming the gate electrode 7 on the gate oxide film 6, for example, a polysilicon film (conductive film) 7a is deposited by about 1000 to 2000 mm by a CVD method. To do. Further, an n-type impurity such as phosphorus is introduced into the conductive film 7a by thermal diffusion or ion implantation. In order to reduce the resistance of the gate electrode, a polycide layer may be formed by depositing about 1000 to 2,000 tungsten silicide film on the conductive film 7a.
[0032]
Thereafter, as shown in FIG. 3D, a photoresist film 8 patterned into a predetermined pattern is obtained by a photolithography technique.
Using the photoresist film 8 as a mask, the conductive film 7a on the gate oxide film 6 is etched by anisotropic etching to obtain the gate electrode 7 in the gate region (see FIG. 3E).
[0033]
Next, until there is no gate oxide film in the region other than the region above the diffusion layer and the gate electrode, that is, the thickness D₁Etch. As a result, as shown in FIG. 3 (f), D is not formed on the diffusion layer 5 without the gate electrode 7.₂-D₁The oxide film 9 having a thickness of 2 mm remains. For example, in the case of the above specific example, the oxide film 9 having a thickness of about 200 mm is formed on the diffusion layer 5, and the silicon substrate 1 is exposed in the region other than the region on the diffusion layer and the gate electrode.
[0034]
Next, as shown in FIG. 3G, an etchant having a high selectivity with respect to the oxide film, for example, HBr / O₂A trench 10 is formed by digging the silicon substrate 1 by anisotropic etching using a system gas and using the gate electrode 7 and the oxide film 9 as a mask. The depth of the groove 10 is preferably 1000 to 4000 mm, and more preferably deeper than the junction depth of the diffusion layer. By making it deeper than the junction depth, sufficient element isolation can be achieved.
The trench 10 is formed only in a region other than the diffusion layer 5 and a region where the gate electrode 7 is not formed, that is, an element isolation region.
[0035]
After removing the photoresist film 8, an interlayer insulating film 11 is formed as shown in FIG. Simultaneously with the formation of the interlayer insulating film 11, the trench 10 is also filled with an insulating material to form an element isolation region.
Through the above steps, the semiconductor device of the first embodiment shown in FIGS. 2A and 2B can be obtained.
The etching for forming the groove from the etching of the gate electrode can be performed in one sequence in the copper sink device. Therefore, the element isolation region can be formed in a self-aligning manner simultaneously with the etching for forming the gate electrode.
[0036]
(Embodiment 2)
4A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 4B is a cross-sectional view taken along the line BB in FIG. FIGS. 4A and 4B show a configuration according to the second embodiment.
[0037]
4A and 4B, the main part of the semiconductor device has an n-type diffusion layer 5 formed on a p-type silicon substrate 1 as a source / drain region and a region such as a resistor. On the n-type diffusion layer 5, an oxide film 9 thickened by accelerated oxidation is formed. In a region other than the n-type diffusion layer 5, the silicon substrate 1 is dug to form a groove 10 (a groove is formed in the gate region). The groove 10 is simultaneously filled with the element isolation region when the interlayer insulating film 11 is formed.
A method for manufacturing the semiconductor device will be described with reference to process cross-sectional views in FIGS.
[0038]
First, as shown in FIG. 5A, a silicon oxide film as an insulating film 2 is formed on a p-type silicon substrate 1 in a high temperature oxygen atmosphere with a thickness of about 100 to 200 mm. Thereafter, a photoresist film 3 is formed into a pattern of a source / drain region and a region to be a resistance by a photolithography technique. Using this pattern as a mask, an n-type impurity such as arsenic (As) is implanted at an energy of 10 to 80 KeV and a dose of 3 × 10.¹⁵cm^-2The diffusion layer 5 is formed by ion implantation 4 under the conditions of about.
[0039]
Next, as shown in FIG. 5B, after removing the photoresist film 3 and the insulating film 2, thermal oxidation is performed in a high-temperature oxygen atmosphere, so that a thickness of about 30 to 300 mm is obtained in a region other than the diffusion layer. A gate oxide film 6 is formed. At this time, a thick gate oxide film 6 is formed on the diffusion layer into which the impurity is implanted at a high concentration by accelerated oxidation as compared with a region other than the diffusion layer.
[0040]
More specifically, for example, when oxidation is performed in an HCl atmosphere at 900 ° C., the film thickness D in a region other than the diffusion layer in FIG.₁Is formed on the diffusion layer 5 in which impurities are ion-implanted at a high concentration.₂Is formed.
[0041]
Next, until there is no gate oxide film in the region other than on the diffusion layer, that is, the thickness D₁Etch. As a result, as shown in FIG.₂-D₁The oxide film 9 having a thickness of 2 mm remains. For example, in the case of the above specific example, the oxide film 9 having a thickness of about 200 mm is formed on the diffusion layer 5 and the silicon substrate 1 is exposed in the other regions.
[0042]
Next, as shown in FIG. 5D, an etchant having a high selectivity with respect to the oxide film, for example, HBr / O₂The groove 10 is formed by digging the silicon substrate 1 by anisotropic etching using a system gas and using the oxide film 9 as a mask. The depth of the groove 10 is preferably 1000 to 4000 mm, and more preferably deeper than the junction depth of the diffusion layer. By making it deeper than the junction depth, sufficient element isolation can be achieved.
[0043]
Next, as shown in FIG. 5E, a gate oxide film 6 of about 30 to 300 mm is formed on the surface of the trench 10 to be a gate region. Further, as a gate electrode material for forming the gate electrode 7 on the entire surface, for example, a polysilicon film (conductive film) 7a is deposited by about 1000 to 2000 mm by a CVD method. Further, an n-type impurity such as phosphorus is introduced into the conductive film 7a by thermal diffusion or ion implantation.
[0044]
Thereafter, as shown in FIG. 5F, a photoresist film 8 patterned into a predetermined pattern is obtained by a photolithography technique. Using this photoresist film 8 as a mask, gate electrode 7 is obtained by etching conductive film 7a on gate oxide film 6 by anisotropic etching.
After removing the photoresist film 8, an interlayer insulating film 11 is formed as shown in FIG. Simultaneously with the formation of the interlayer insulating film 11, the trench 10 is also filled with an insulating material to form an element isolation region.
[0045]
Through the above steps, the semiconductor device of the second embodiment shown in FIGS. 4A and 4B can be obtained.
In the above embodiment, since the gate electrode is formed along the inner wall of the trench, the channel of the transistor can be made longer than the pattern dimension of the mask. As a result, the short channel effect of the transistor can be suppressed.
[0046]
(Embodiment 3)
6A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 6B is a cross-sectional view taken along the line BB in FIG. FIGS. 6A and 6B show a configuration according to the third embodiment.
[0047]
6A and 6B, the main part of the semiconductor device has an n-type diffusion layer 5 formed on a p-type silicon substrate 1 as a source / drain region and a region such as a resistor. A gate electrode 7 is formed on the silicon substrate 1 via a gate oxide film 6. On the n-type diffusion layer 5, an oxide film 9 thickened by accelerated oxidation is formed. In a region other than the gate electrode 7 and the n-type diffusion layer 5, the silicon substrate 1 is dug to form a groove 10. The groove 10 is simultaneously filled with the element isolation region when the interlayer insulating film 11 is formed.
A method for manufacturing the semiconductor device will be described with reference to process cross-sectional views in FIGS.
[0048]
First, as shown in FIG. 7A, thermal oxidation is performed on a p-type silicon substrate 1 in a high-temperature oxygen atmosphere to form a gate oxide film 6 having a thickness of about 100 to 300 mm. Next, as a gate electrode material for forming the gate electrode 7 on the gate oxide film 6, for example, a polysilicon film (conductive film) 7 a is deposited by about 1000 to 2000 mm by CVD. Further, an n-type impurity such as phosphorus is introduced into the conductive film 7a by thermal diffusion or ion implantation.
[0049]
Thereafter, as shown in FIG. 7B, a photoresist film 8 patterned into a predetermined pattern is obtained by a photolithography technique. Using this photoresist film 8 as a mask, gate electrode 7 is obtained by etching conductive film 7a on gate oxide film 6 by anisotropic etching.
After removing the photoresist film 8, the photoresist film 3 is formed into a pattern of the source / drain region and the region to be a resistance by photolithography. Using this pattern as a mask, an n-type impurity such as arsenic (As) is implanted at an energy of 10 to 80 KeV and a dose of 3 × 10.¹⁵cm^-2Diffusion layer 5 is formed by ion implantation 4 under the conditions (see FIG. 7C).
[0050]
Next, as shown in FIG. 7 (d), after removing the photoresist film 3 and the insulating film 2, thermal oxidation is performed in a high-temperature oxygen atmosphere, thereby reducing the gate oxide film 6 on the diffusion layer to about 300 mm or less. Increase the thickness. At this time, the gate oxide film 6 becomes thicker on the diffusion layer into which the impurity is implanted at a high concentration by accelerated oxidation as compared with the region other than the diffusion layer. A thick oxide film 6 a is also formed on the surface of the gate electrode 7.
[0051]
More specifically, for example, when oxidation is performed in an HCl atmosphere at 900 ° C., the film thickness D in a region other than the diffusion layer in FIG.₁Is formed on the diffusion layer 5 in which impurities are ion-implanted at a high concentration.₂Is formed.
Next, until there is no gate oxide film in the region other than the region above the diffusion layer and the gate electrode, that is, the thickness D₁Etch. As a result, as shown in FIG. 7 (e), D is formed on the diffusion layer 5 without the gate electrode 7.₂-D₁The oxide film 9 having a thickness of 2 mm remains. For example, in the case of the above specific example, the oxide film 9 having a thickness of about 200 mm is formed on the diffusion layer 5, and the silicon substrate 1 is exposed in the region other than the region on the diffusion layer and the gate electrode. The thick oxide film 6a on the surface of the gate electrode 7 is also etched at the same time to become an oxide film 6b.
[0052]
Next, as shown in FIG. 7F, an etchant having a high selectivity with respect to the oxide film, for example, HBr / O₂A trench 10 is formed by digging the silicon substrate 1 by anisotropic etching using a system gas and using the gate electrode 7 and the oxide film 9 as a mask. The depth of the groove 10 is preferably 1000 to 4000 mm, and more preferably deeper than the junction depth of the diffusion layer. By making it deeper than the junction depth, sufficient element isolation can be achieved.
The trench 10 is formed only in a region other than the diffusion layer 5 and a region where the gate electrode 7 is not formed, that is, an element isolation region.
[0053]
After removing the photoresist film 8, an interlayer insulating film 11 is formed as shown in FIG. Simultaneously with the formation of the interlayer insulating film 11, the trench 10 is also filled with an insulating material to form an element isolation region.
Through the above steps, the semiconductor device of the first embodiment shown in FIGS. 6A and 6B can be obtained.
[0054]
【The invention's effect】
According to the present invention, the gate insulating film on the diffusion layer is made thicker than the gate insulating film in other regions by accelerated oxidation, so that only the formation region of the element isolation region can be selectively used by utilizing the film thickness difference. Alternatively, the groove can be formed by etching the semiconductor substrate in a region including the channel region of the semiconductor device. That is, an element isolation region can be formed and the short channel effect of the semiconductor device can be suppressed.
Further, since the gate-drain capacitance can be suppressed, the delay time can be improved and the speed can be increased. As a result, not only can the process be significantly reduced, but the channel length of the element isolation region and the semiconductor device can be reduced, and the semiconductor device can be miniaturized.
In addition, there is no etching residue of the gate electrode material when the gate electrode is formed, and it is possible to prevent problems such as generation of leakage current due to stress on the semiconductor substrate during CMP and reduction of breakdown voltage.
[Brief description of the drawings]
FIG. 1 is a schematic plan view of a semiconductor device of the present invention.
2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment of the present invention, in which (a) is a schematic cross-sectional view taken along the line AA in FIG. 1, and (b) is a BB line in FIG. It is a schematic sectional drawing in a position.
3 is a schematic process cross-sectional view of the semiconductor device according to the first embodiment of the present invention at the position of the AA line in FIG. 1; FIG.
4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention, (a) is a schematic cross-sectional view taken along the line AA in FIG. 1, and (b) is a BB line in FIG. It is a schematic sectional drawing in a position.
5 is a schematic process cross-sectional view of the semiconductor device according to the second embodiment of the present invention at the position of the AA line in FIG. 1; FIG.
6 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention, where (a) is a schematic cross-sectional view taken along the line AA in FIG. 1, and (b) is a BB line in FIG. It is a schematic sectional drawing in a position.
7 is a schematic process cross-sectional view of the semiconductor device according to the third embodiment of the present invention at the position of the AA line in FIG. 1; FIG.
FIG. 8 is a schematic plan view of a conventional semiconductor device.
9A and 9B are schematic cross-sectional views of a conventional semiconductor device, wherein FIG. 9A is a schematic cross-sectional view taken along the line AA in FIG. 8, and FIG. 9B is a schematic cross-sectional view taken along the line BB in FIG. It is.
10 is a schematic process sectional view taken along the line AA of the conventional semiconductor device of FIG. 9; FIG.
11A and 11B are schematic cross-sectional views of a conventional semiconductor device, wherein FIG. 11A is a schematic cross-sectional view taken along the line AA in FIG. 8, and FIG. 11B is a schematic cross-sectional view taken along the line BB in FIG. It is.
12 is a schematic process sectional view taken along the line AA of the conventional semiconductor device of FIG. 11; FIG.
[Explanation of symbols]
1,21 Silicon substrate
2, 35 Insulating film
3, 8, 24, 28, 29 Photoresist film
4, 30 Ion implantation
5, 31 Diffusion layer
6, 26 Gate oxide film
6a, 6b, 9, 34 Oxide film
7, 27 Gate electrode
7a, 27a conductive film
10, 33 groove
11, 32 Interlayer insulation film
22, 35 Silicon oxide film
23 Silicon nitride film
25 Field oxide film

Claims (5)

Forming a diffusion layer to be a source / drain region on a surface layer of a semiconductor substrate;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
Forming a conductive film on the entire surface of the semiconductor substrate;
Etching the conductive film using a resist pattern to form a gate electrode on the gate region between the source / drain regions and on the end of the source / drain region;
Forming a gate insulating film made of an oxide film by removing the oxide film other than on the source / drain regions and the gate region to expose the semiconductor substrate;
Forming a groove in the semiconductor substrate using the resist pattern and an oxide film on the source / drain region as a mask;
A step of forming an element isolation region composed of an interlayer insulating film and an insulating film embedded in a groove by laminating an insulating film over the entire surface of the semiconductor substrate after removing the resist pattern; Production method. Forming a gate electrode in a gate region on a semiconductor substrate via a gate insulating film;
Forming a diffusion layer to be a source / drain region on the surface layer of the semiconductor substrate using the gate electrode as a mask;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
Forming a gate insulating film made of an oxide film on the source / drain region by removing the oxide film other than on the source / drain region and the gate region to expose the semiconductor substrate;
Forming a groove in the semiconductor substrate using the resist pattern and an oxide film on the source / drain region as a mask;
A step of forming an element isolation region composed of an interlayer insulating film and an insulating film embedded in a groove by laminating an insulating film over the entire surface of the semiconductor substrate after removing the resist pattern; Production method. Gate region, the production method according to claim 1 or 2 including a groove. Forming a diffusion layer to be a source / drain region on a surface layer of a semiconductor substrate;
Forming the oxide film on the source / drain region thicker than the film thickness of the oxide film other than the source / drain region by oxidizing the semiconductor substrate;
And as factories to Ru to expose the semiconductor substrate to remove the oxide film other than the source / drain regions,
Forming a groove in a semiconductor substrate around the source / drain region including the gate region using the oxide film on the source / drain region as a mask;
Forming a conductive film on the entire surface of the semiconductor substrate after forming a gate insulating film made of an oxide film at least on the inner surface of the groove in the gate region;
Etching the conductive film using a resist pattern to form a gate electrode on the gate region between the source / drain regions and on the end of the source / drain region;
And a step of forming an element isolation region comprising an interlayer insulating film and an insulating film buried in a trench other than the gate region by laminating an insulating film over the entire surface of the semiconductor substrate. . The manufacturing method according to claim 3 , wherein the trench in the gate region is deeper than the junction depth of the diffusion layer in the source / drain region.

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