JPH08330425A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To form a complete contact hole by preventing the short-circuiting of a first conductive film such as a gate electrode and the hole and the opening failure of the' hole irrespective of the irregularity of the size of the opening sizes of a resist film as a mask material when the hole is etched. CONSTITUTION: The method for manufacturing a semiconductor device comprises the steps of forming a first conductive film (gate electrode) 4 of a predetermined pattern on a semiconductor substrate 1, covering the first conductive film with insulating films 14, 17, opening a contact hole arriving at the element provided on the surface of the substrate on the insulating films, forming second conductive films 21, 23 in the contact, forming a sidewall made of an insulator at the side of the first film 4 in the case of electrically connecting to the element, forming a high melting point metal film 8 on the region on the sidewall, and further, etching the films 14, 17 under the conditions of faster etching rate than that of the high melting point metal to open the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a contact hole for connecting an element formed on a silicon substrate and a wiring layer.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device having a stack type memory cell as an example of the semiconductor device in the order of steps. First, as shown in FIG. 5A, after forming a field oxide film 2 and a gate oxide film 3 on a p-type semiconductor substrate 1, a first polycrystalline silicon layer is formed and selectively etched by a photoetching method. Thus, the gate electrode 4 of the polycrystalline silicon layer is formed. After that, the n-type low-concentration impurity regions 6 to be the source / drain regions are formed by ion implantation. Next, the oxide film 7 is formed and anisotropically etched to remain only on the side surface of the gate electrode 4. Subsequently, although not shown, a high-concentration impurity region is formed in a predetermined portion of the peripheral circuit portion other than the memory cell portion.

Next, as shown in FIG. 5B, after forming a first insulating film 14 on the entire surface, a first contact hole reaching one of the n-type impurity regions is formed though not shown. In addition, after forming a conductive layer on the entire surface and etching it into a predetermined pattern to form a bit line, a second insulating film 17 is formed on the entire surface.
Then, a second polycrystalline silicon layer 18 is formed on the entire surface for 3000
After forming about Å, a photoresist film 19 is formed so that an opening exists on one of the low concentration impurity regions 6.

Then, as shown in FIG. 5C, the polycrystalline silicon layer 18, the first insulating film 14 and the second insulating film 1 are formed.
7 is sequentially removed by etching to form a second contact hole 20 reaching the low concentration impurity region 6. Then, Fig. 5
As shown in (d), after laminating the third polycrystalline silicon layer 21 on the second polycrystalline silicon layer 18 for about 1000 Å,
The second and third polycrystalline silicon layers 18 and 21 are removed by etching in a predetermined pattern. After forming a dielectric film 22 on the surfaces of the second and third polycrystalline silicon layers 18 and 21, a fourth polycrystalline silicon film 23 is laminated on the entire surface.

As a result, the second and third polycrystalline silicon layers 18 and 21 serve as storage electrodes for the capacitance of the memory cell, and the fourth polycrystalline silicon layer 23 serves as the counter electrode. By thus forming the storage electrode in two layers, the second polycrystalline silicon layer 18 is formed thick to increase the height of the side surface, and the third polycrystalline silicon layer 21 is formed thin. The capacitance value can be increased by utilizing the side wall along the contact hole as a capacitance.

[0006]

However, in the above-described conventional method of manufacturing a memory cell, when the resist film 19 is formed immediately above the polycrystalline silicon layer 18 for selective etching, the resist film 19 is directly underneath. Under the influence of the polycrystalline silicon layer 18 existing in the region, the multiple interference effect of light differs depending on the location where the resist film thickness is different, for example, inside the memory cell and the end portion of the memory cell portion, which causes the diameter of the opening to differ. It may be formed. If such a state occurs, when etching is performed under the condition matched with the side having a small opening diameter, overetching is likely to occur on the side having a large opening diameter, and as shown in FIG. Expanded to the area where the electrode 4 exists,
This causes a problem that the conductive layer 21 formed in the contact hole 20 and the gate electrode 4 are short-circuited. On the other hand, if etching is performed under conditions with a larger opening diameter side, underetching is likely to occur on the smaller opening diameter side, resulting in defective contact opening as shown in FIG. 6B.

[0007]

An object of the present invention is to provide a semiconductor capable of forming a complete contact hole without causing a short circuit with a gate electrode or a defective opening, regardless of variations in the opening diameter of the resist film. It is to provide a method of manufacturing a device.

[0008]

According to the manufacturing method of the present invention, a first conductive film having a required pattern is formed on a semiconductor substrate, and the first conductive film is covered with an insulating film. In a semiconductor device including a structure in which a contact hole reaching an element provided on a surface of a semiconductor substrate is formed, and a second conductive film is formed in the contact to electrically connect to the element, A step of forming a side wall made of an insulating material on a side surface of the film and forming a refractory metal film in a region on the side wall is performed. When the contact hole is opened, the insulating film is higher than an etching rate of the refractory metal. Is characterized in that the etching is performed under the condition that the etching rate is fast.

[0009]

Since the refractory metal film is formed on the side surface of the first conductive film via the side wall of the insulating material, even if overetching occurs when the contact hole is opened, the contact hole is formed by the refractory metal film. It is prevented that the first conductive film is exposed inside. Therefore, the second formed inside the contact hole
The conductive film is not short-circuited with the first conductive film, and a suitable contact hole can be formed.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 4 are cross-sectional views showing an embodiment of the manufacturing method of the present invention in the order of steps, showing a cross-sectional structure of a semiconductor device centering on a memory cell portion. First, FIG. 1 (a)
As described above, the field oxide film 2, the gate oxide film 3, the first polycrystalline silicon layer 4 and the first oxide film 5 are sequentially formed on the semiconductor substrate 1, and the first oxide film 5 is formed by using a photoresist film (not shown). The one polycrystalline silicon layer 4 and the first oxide film 5 are patterned to form the gate electrode 4. Further, ion implantation is performed using these as a mask to form the low concentration impurity region 6. After that, the photoresist film is removed and a second oxide film is deposited on the entire surface and etched back to form sidewalls 7 left on the side surfaces of the gate electrode 4 and the first oxide film 5.

Next, as shown in FIG. 1B, after depositing, for example, a titanium layer 8 of about 800 Å on the entire surface, it is annealed at 650 ° C. for about 30 seconds in a nitrogen atmosphere, and the surface of the low concentration impurity region Is silicided to form a titanium silicide layer 9. Subsequently, as shown in FIG. 1C, a photoresist film 10 is formed so as to overlap at least the titanium silicide layer 9 in the memory cell portion and the gate electrode 4 adjacent to the titanium silicide layer 9, and the photoresist film 10 is used as a mask. (D)
Then, the exposed unreacted titanium layer is removed.

Next, as shown in FIG. 2A, a first insulating film 14 is formed on the entire surface, and a second insulating film 17 is further formed on the first insulating film 14.
And a second polycrystalline silicon layer 18 is deposited. Next, as shown in FIG. 2B, a photoresist film 19 is applied on the second polycrystalline silicon layer 18, and an opening is provided in a region corresponding to a contact hole. The film 18 is removed by etching, and then the first and second insulating films 14 and 17 are etched by an etching method in which the titanium layer 8 has a slower etching rate than the first and second insulating films to form the contact holes 20. It is opened and the titanium layer 8 is exposed on the bottom surface.

After that, as shown in FIG. 2C, the exposed unreacted titanium layer 8 is removed by etching so that the contact hole 20 reaches the titanium silicide layer 9. Next, as shown in FIG. 2D, a third polycrystalline silicon layer 21 is stacked on the side wall of the contact hole 20 and the second polycrystalline silicon layer 18, and then as shown in FIG. Then, using the photoresist film 25, the second and third polycrystalline silicon layers 18 and 21 are removed by etching into a predetermined pattern.

Thereafter, as shown in FIG. 3B, a dielectric film 22 is formed on the surfaces of the second and third polycrystalline silicon layers 18 and 21, and then a fourth polycrystalline silicon layer 23 is deposited on the entire surface.
After patterning, a third insulating film 24 is deposited on the entire surface to obtain a semiconductor device.

Therefore, in this manufacturing method, when the contact hole 20 is opened, the side surface of the gate electrode is covered with the unreacted titanium layer 8. Therefore, when the contact hole 20 is etched, the titanium film 8 functions as an etching stopper film, so that the contact hole can be formed regardless of the variation in the opening diameter of the resist film used as a mask for forming the contact hole. It can be completely formed. Therefore, when etching is set to have a smaller opening size, even if overetching occurs in the contact hole, the contact hole does not expose the side surface portion of the gate electrode and the short circuit can be prevented.

Here, the chisan silicide layer 9 described above is used.
Is a so-called salicide process that has been performed in recent years to reduce the resistance of the surface of the source / drain region and the gate electrode. In this salicide process, after forming an n-type diffusion layer, a refractory metal is laminated on the entire surface and then annealed in a nitrogen atmosphere to make the diffusion layer and the surface of the gate electrode a refractory silicide. After that, the unreacted refractory metal is removed, so that the diffusion layer and the surface of the gate electrode can be silicidized in a self-aligned manner. In this embodiment, it can be said that this salicide process is used.

Although the above-described steps are for the memory cell section, the peripheral circuit section is actually manufactured at the same time when the memory cell section is manufactured. Therefore, a brief description of the manufacturing process of this peripheral circuit section is as shown in FIG.
4A, the photoresist film 10 is also formed on the p-channel transistor region of the peripheral circuit portion and the unreacted titanium layer in the n-channel transistor region is removed as shown in FIG. Next, arsenic is added to, for example, 50 keV, 5.0
Ions are implanted at × 10 ¹⁵ / cm to form the first high concentration impurity region 11.

After that, as shown in FIG. 4B, after removing the photoresist film, the region other than the p-channel transistor region of the peripheral circuit portion is covered with the photoresist film 12 together with the memory cell portion. Then, as shown in FIG. 4C, the unreacted titanium layer 8 only in the p-channel transistor region is removed, and boron is ion-implanted at, for example, 50 keV and 5 × 10 ¹⁵ / cm to form the second high-concentration impurity region 13. To form.

In addition, in the middle of the process of FIG.
As shown in (d), the photoresist film 15 is formed in a predetermined pattern, the first insulating film 14 and the unreacted titanium layer 8 are removed, and the first contact hole 16 is formed. Thereafter, although not shown, a conductive layer for forming a bit line is laminated to form a desired pattern.

Here, the above embodiment shows an example in which the present invention is applied to a semiconductor device having a stack type memory cell. However, if the semiconductor device includes a step of forming a contact hole and employs a salicide process. The present invention can be similarly applied.

In the above embodiment, titanium is used as the refractory metal for performing the salicide process.
Tungsten, molybdenum, nickel, cobalt, tantalum, or a laminated film of these can be similarly used.

[0022]

As described above, according to the present invention, the side wall of the first conductive film formed on the semiconductor substrate is formed with the side wall made of the insulating material, and the refractory metal film is formed in the region on the side wall. In the above, since the contact hole is opened by etching the insulating film on the first conductive film under the condition that the etching rate is higher than that of the refractory metal, the resist film used as a mask for forming the contact hole is opened. Even if there is variation in the size of the aperture, by performing etching with the side with the smaller opening as the reference, there is no defective opening of the contact hole, and over-etching has occurred on the side with the larger opening. Even in this case, the other-melting-point metal film can prevent the first conductive film from being short-circuited with the contact hole, and a complete contact hole can be formed.

Further, in the present invention, if the refractory metal film formed in the side surface region of the first conductive film is made of the refractory metal used in the existing salicide process, the manufacturing process is hardly increased. The invention can be realized.

[Brief description of drawings]

FIG. 1 is a first sectional view showing an embodiment of the manufacturing method of the present invention in the order of steps.

FIG. 2 is a second sectional view showing an embodiment of the manufacturing method of the present invention in the order of steps.

FIG. 3 is a third sectional view showing an embodiment of the manufacturing method of the present invention in the order of steps.

FIG. 4 is a fourth sectional view showing the embodiment of the manufacturing method of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing an example of a conventional manufacturing method in process order.

FIG. 6 is a cross-sectional view for explaining problems in the conventional manufacturing method.

[Explanation of symbols]

 1 semiconductor substrate 4 gate electrode (first polycrystalline silicon layer) 6 low concentration impurity region 7 sidewall (second oxide film) 8 titanium layer 9 titanium silicide layer 10 photoresist film 14 first insulating film 17 second Insulating film 18 Second polycrystalline silicon layer 19 Photoresist film 20 Contact hole 21 Third polycrystalline silicon layer 22 Dielectric film 23 Fourth polycrystalline silicon layer

Claims (4)

[Claims] 1. A first conductive film having a required pattern is formed on a semiconductor substrate, and the first conductive film is covered with an insulating film.
A contact hole reaching an element provided on the surface of the semiconductor substrate is opened in the insulating film, and a second hole is formed in the contact.
In a semiconductor device including a structure for forming a conductive film for forming an electrical connection to the element, a side wall made of an insulating material is formed on a side surface of the first conductive film, and a refractory metal is formed in a region on the side wall. A method of manufacturing a semiconductor device, comprising the step of forming a film, wherein the opening of the contact hole is performed under the condition that the etching rate of the insulating film is faster than the etching rate of the refractory metal. 2. An element isolation region, a gate oxide film, a first polycrystalline silicon layer and a first oxide film are sequentially formed on one main surface of a semiconductor substrate, and then the first polycrystalline silicon layer and the first polycrystalline silicon layer are formed. After the step of etching one oxide film into a predetermined pattern and forming an impurity region having a conductivity opposite to that of the semiconductor substrate by ion implantation, a second oxide film is formed over the entire surface and anisotropically etched. A step of etching the second oxide film, leaving only the side surfaces of the first polycrystalline silicon layer and the first oxide film, and depositing a refractory metal over the entire surface, and annealing in a non-oxidizing atmosphere. A step of forming a refractory metal silicide on the surface of the impurity region; a step of forming a resist film at least in a region overlapping with the first polycrystalline silicon layer; and a step of exposing the resist film to a mask. The above high A step of removing the melting point metal, a step of forming a first insulating film, a second insulating film and a second polycrystalline silicon layer on the entire surface, and an opening in a part of the region where the refractory metal is present. A step of forming a resist film on the second polycrystalline silicon film so as to exist, a step of removing the second polycrystalline silicon layer using the resist film as a mask, and the first and second A step of etching the first and second insulating films until the refractory metal is completely exposed by an etching method in which the refractory metal has a slower etching rate than the insulating film; and the exposed refractory metal. Removing the metal to form a contact hole reaching the silicide of the refractory metal; and forming a third polycrystalline silicon layer on the sidewall of the contact hole and on the second polycrystalline silicon layer. , The second and above Etching the third polysilicon layer into a predetermined pattern,
A step of forming a dielectric film on the surfaces of the second and third polycrystalline silicon layers, and a step of forming a fourth polycrystalline silicon layer on the dielectric film and forming it into a required pattern. A method for manufacturing a semiconductor device, comprising: 3. An element isolation region, a gate oxide film, a first polycrystalline silicon layer and a first oxide film are sequentially formed on one main surface of a semiconductor substrate, and then the first polycrystalline silicon layer and the first polycrystalline silicon layer are formed. After a step of etching one oxide film into a predetermined pattern and forming a low-concentration impurity region having a conductivity opposite to that of the semiconductor substrate by ion implantation, a second oxide film is formed over the entire surface, and anisotropic Etching the second oxide film by etching, leaving only the side surfaces of the first polycrystalline silicon layer and the first oxide film, and depositing a refractory metal over the entire surface, in a non-oxidizing atmosphere A step of annealing the surface of the low-concentration impurity region to a silicide of a refractory metal,
Forming a resist film so as to cover at least a part of the refractory metal in a part of the peripheral circuit part and a region where a memory cell will be formed in the future and to overlap with the first polycrystalline silicon layer; A step of removing the refractory metal exposed from the resist film as a mask and subsequently forming a first high-concentration impurity region by ion implantation; a step of removing the resist film; and a part of the peripheral circuit portion. After removing the refractory metal, a step of ion-implanting into a predetermined location to form a second high-concentration impurity, and a first insulating film, a second insulating film, and a second polycrystalline silicon layer over the entire surface. A step of forming, a step of forming a resist film on the second polycrystalline silicon film so that an opening exists in a part in a region where the refractory metal exists, the resist film as a mask Second And removing the crystalline silicon layer,
A step of etching and removing the first and second insulating films until the high melting point metal is completely exposed by an etching method in which the high melting point metal has a slower etching rate than the first and second insulating films. And a step of removing the exposed high-melting-point metal to form a contact hole reaching the silicide of the high-melting-point metal, and a third polycrystal on the sidewall of the contact hole and the second polycrystal silicon layer. A method of manufacturing a semiconductor device, comprising: a step of forming a silicon layer; and a step of etching the second and third polycrystalline silicon layers into a predetermined pattern. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the refractory metal is titanium, tungsten, molybdenum, nickel, cobalt, tantalum, or a laminated film thereof.