KR20030070968A - semiconductor device having local salicidation structure and method for fabricating the same - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device with a local salicidation structure is provided to improve an operation speed of the semiconductor device and maximize integration of devices using a borderless contact by selectively forming silicide in a cell area and a peripheral area. CONSTITUTION: A plurality of transistors having a gate spacer(60) are formed in the first and second regions defined in a semiconductor substrate(10). An etch stop layer(62) is stacked on the entire surface. A photoresist layer is formed to expose the upper portion of the etch stop layer only to the second region such that the etch stop layer covers the upper portion of the gate of the transistors. The etch stop layer exposed to the second region and the etch stop layer in the first region are eliminated by using the photoresist layer as an etch mask. After the photoresist layer is removed, refractory metal is stacked and a heat treatment process is performed. The upper portions of the gate and a source/drain active region in the first region are transformed into a silicide layer. Only the upper portion of the gate in the second region is transformed into a silicide layer.

Description

Semiconductor device having a local salicylation structure and a method of manufacturing the same {semiconductor device having local salicidation structure and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and more particularly, to a semiconductor device having a local salicide structure and a method of manufacturing the same.

In recent years, with the rapid spread of information media such as computers, the functions of semiconductor devices such as semiconductor memories have also developed remarkably. In the case of recent semiconductor products, high integration of products is essential for low cost and high quality to secure competitiveness. Higher integration has been accompanied by scale down including thinning and shortening the gate oxide film thickness and channel lengths of transistor elements.

As semiconductor devices become faster, self-aligned silicide (Saliside) technology has been widely applied in the art to reduce contact resistance and sheet resistance in the source / drain regions and at the same time reduce interconnect resistance of polysilicon lines. A conventional salicide process used in recent years is a heat treatment by depositing a metal such as titanium (Ti), cobalt (Co) and platinum (Pt) on a MOS structure, thereby self-aligning the top of the polysilicon gate and the source / drain. The silicide layer is formed on top of the active region. Here, the polysilicon forming the gate and the single crystal silicon forming the source / drain react with the high melting point metal to form silicide, but the gate spacer formed on the sidewall of the gate is not a silicon material but is typically a silicon oxide film or Since it is made of a nitride film, no silicide reaction occurs on the gate spacer. As a result, silicide does not form on the gate spacer. The gate and source / drain regions are electrically insulated from each other by removing the silicided reaction on top of the gate spacer and removing the deposited metal layer through a suitable etching technique in a subsequent process.

In the above case, the salicide present in the active region is located inside the source / drain junction, and if the profile of the formed salicide is poor, there is a possibility of causing a junction leakage. In addition, in case of ESD protection transistor to prevent chip breakdown by electrostatic discharge (ESD), the resistance of drain stage must be high to maximize the protection performance.In the case of salicide, simply increasing the length of drain stage is required. It is difficult to get high resistance. That is, although there is a benefit in device characteristics such as low resistance by forming salicide, there is a possibility that some devices may cause deterioration, so that there is a demand to selectively form salicide. That is, salicide is formed in the gate to reduce the interconnect resistance of the polysilicon line, and active does not form the salicide, so called local salicide, which can minimize junction leakage and maximize the protection performance of the electrostatic discharge protection transistor. The method is preferred.

On the other hand, as cell size decreases due to the increase in the degree of integration of semiconductor devices, various process limitations are exposed throughout the semiconductor manufacturing process, and in particular, from the viewpoint of photographic technology, process difficulties mainly due to the extremely small pattern size. This is emerging a lot. In order to overcome these limitations, various approaches have been attempted. In particular, many techniques for forming borderless contact formed over active and shallow trench isolation (STI) using high selectivity between nitrides in an oxide etching process are studied. It is becoming.

However, in the case of using a conventional local salicideation process, since it is difficult to form a nitride film that serves as an etch stop film during subsequent interlayer insulating film etching, the oxide film of STI is excessively etched when the oxide film of the borderless contact is etched. An electrical short may occur between the conductive layer and the well filled in the contact. Therefore, when the borderless contact cannot be applied, it is difficult to increase the degree of integration of the semiconductor device.

Hereinafter, the problem that the oxide film of the borderless contact is excessively etched when a conventional local salicide process is used will be described in more detail.

1A to 1D are cross-sectional views illustrating a method for forming a local salicide of a semiconductor device according to the prior art. First, referring to FIG. 1A, a process of forming an inter-element isolation insulating film 20 in a trench process on a semiconductor substrate 10, an insulating layer 40 as a gate insulating film, a polycrystalline polysilicon as a gate electrode, and a conductor on the front surface thereof. Laminating and forming a gate electrode 50 in a conventional photolithography process, forming a gate spacer 60 on sidewalls of the gate electrode 50, and implanting impurities using the formed gate electrode as a mask to activate the gate electrode 50. The result of the process of forming the area | region 30 and the process of laminating | stacking and planarizing the interlayer insulation film 70 are shown in order. Referring to FIG. 1B, a process of removing the interlayer insulating film 70 stacked on the top of the gate electrode 50 to the top height of the gate electrode 50 by using a chemical mechanical polishing (CMP) or etch back process is performed. Referring to FIG. 1C, a high melting point metal is deposited on the entire surface of the resultant of FIG. 1B, and the silicon atom inside the polycrystalline (poly) silicon is reacted with the stacked metal atoms by a heat treatment process to function as the gate electrode 50. The process of forming the silicide film 55 on the polycrystalline polysilicon surface is shown. Referring to FIG. 1D, the interlayer insulating film 75 is stacked again, the photoresist film is patterned using a conventional photolithography process, and the interlayer insulating film 75 is etched using the patterned photoresist film as a mask to form a borderless contact 65. The results of the process progress are shown.

As described above, when the semiconductor transistor is manufactured by a conventional local salicide process, the etch stop layer cannot be laminated, so that the STI 20 is formed when the oxide layer is etched to form the borderless contact. The oxide film is excessively etched together. Therefore, a phenomenon may occur in which the conductive layer filling the borderless contact and the well are electrically shorted. For this reason, there is a problem of limiting an increase in the degree of integration of a semiconductor device because the borderless contact is not conventionally applied.

Accordingly, an object of the present invention is to provide a low power semiconductor device capable of high integration and high speed operation and a method of manufacturing the same, which can solve the above-mentioned problems.

Another object of the present invention is to provide a method and a structure of a semiconductor transistor manufacturing method capable of significantly reducing junction leakage and significantly improving operation speed and device integration.

It is still another object of the present invention to provide an improved local salicide method that can maximize the device integration by enabling borderless contact while improving the operation speed of a semiconductor device.

In accordance with an aspect of the present invention, a method of manufacturing a semiconductor device includes: forming and etching a plurality of transistors each having a gate spacer in a first region and a second region defined in a semiconductor substrate; Forming a photoresist film so as to expose an upper portion of the etch stop film covering the gate top of the transistors only in the second region after stacking the stop films entirely; Removing both the etch stop film of the second region and the etch stop film of the first region by using the photoresist as an etch mask; After removing the photoresist layer, a high melting point metal is laminated on the entire surface and a heat treatment process is performed to form both the upper gate and the upper source / drain active region as a silicide layer in the first region, and only the upper gate portion is the silicide layer in the second region. It characterized in that it comprises a step of forming.

In the structure of the semiconductor transistor according to another aspect of the present invention, for transistors located in the first region of the substrate, a silicide layer is formed on the gate and the source / drain active region, respectively, and is spaced apart from the first region. For the transistors located in the second region, the silicide layer is formed only on the gate.

Here, when the first region is a peripheral region, the second region may be a memory cell region, and when the first region is a memory cell region, the second region may be a peripheral region. Also, preferably, the silicide layers formed in the first region and the second region are salicide layers formed at the same time by self alignment.

1A to 1D are views illustrating a process for forming a local salicide of a semiconductor device according to a prior art according to a process sequence;

2A to 2H are views illustrating a method for forming a local salicide of a semiconductor device according to an embodiment of the present disclosure according to a process sequence;

Hereinafter, a preferred embodiment of a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. Although shown in different figures, the same to similar layers are shown with the same reference numerals.

First, the gist of the embodiment will be described as follows without any other intention than to provide a thorough understanding of the present invention. Local salicides that selectively form salicides in accordance with device characteristics and applications are a fundamental solution of the present invention. For example, salicide is formed only in the gate in a specific region, and salicide is not formed in the source / drain active region. As a result, there is less junction leakage, which enables stable use even in low-power SRAMs, maximizes the protection of ESD protection transistors, reduces the interconnect resistance of polysilicon lines, and increases the operating speed of semiconductor devices. Because borderless contacts can be applied, the degree of integration can be increased by reducing the cell size. In addition, in another specific region, the salicide is simultaneously formed in the gate and the active region, thereby maximizing the speed of the semiconductor device. In other words, applying the above two factors at the same time has the advantage of making a low-power, high-speed device.

2A to 2H are views illustrating a method for forming a local salicide of a semiconductor device according to an embodiment of the present disclosure according to a process sequence. Among FIG. 2A to FIG. 2H shown in accordance with an embodiment of the present invention, reference is first made to FIG. 2A. FIG. 2A illustrates a process of forming an isolation insulating film between devices in a trench process on a semiconductor substrate 10 made of a material such as single crystal silicon. The insulating layer 40 as a gate insulating film, the polycrystalline silicon 50 as a gate electrode, and a conductor are shown in FIG. A process of forming an active region by implanting impurity ions using the gate electrode 50 as an ion implantation mask and laminating the entire surface and patterning by a conventional photolithography process. Nitride spacers 60 on the sidewalls of polycrystalline silicon 50. ), A process of forming a high concentration of the active region 30 by implanting impurities using polycrystalline silicon and sidewall spacers as masks is shown. Here, when the etch stop film 62 is entirely stacked and the photoresist 65, for example, a photoresist is applied and baked, the resultant of FIG. 2A is obtained. Here, the etch stop film 62 is preferably a nitride film having excellent selectivity with respect to the oxide film. In addition, when the first region 100 shown on the left side of the drawing is conveniently represented as a peripheral region instead of the memory cell region, the second region 200 shown on the right side becomes a memory cell region.

FIG. 2B shows a cross section after the photoresist film 65 of the desired region, here the first region 100, has been removed using the conventional photographic technique on the resultant of FIG. 2A. FIG. 2C shows a cross section after the photoresist film 65a on the resultant of FIG. 2B is etched back to stop the etch stop at the etch stop film 62 on the gate electrode 50. FIG. 2D is a cross-sectional view after removing the etch stop film 62 on the gate electrode 50 by using the resultant photosensitive film 65b of FIG. 2C as an etch mask. FIG. 2E shows a cross-sectional view after removing the resultant photosensitive film 65b of FIG. 2D. Accordingly, the gate electrode 50 and the gate spacer 60 are completely exposed in the first region 100, and only the upper portion of the gate electrode 50 is exposed in the second region 200.

FIG. 2F shows a result of laminating a high melting point metal on the entire surface of the resultant image of FIG. 2E and applying a heat treatment process. By the above process, the silicon atom inside the polycrystalline silicon as the gate electrode and the silicon atom inside the single crystal silicon as the active region react with the silicide. Therefore, the salicide is formed in both the gate and the source / drain region in the specific region 100, and the salicide is formed only in the gate in the other specific region 200. Here, titanium and cobalt may be selected from the metals used in the salicide process. The metal is known to have a very low resistance and react only with silicon atoms inside polysilicon or single crystal silicon to form silicides. When the salicide process is completed, after the etching of the remaining metal film not silicided, the additional heat treatment process may be further performed to stabilize the silicide film quality and to lower the resistance.

FIG. 2G shows the result of laminating the etch stop layer 68 on the entire surface of the resultant image of FIG. 2F. After that, the interlayer insulating film is laminated all over again, and then CMP is made to planarize. FIG. 2H shows that the interlayer insulating film 70 is etched using the patterned photoresist as a mask after patterning the contact on the resultant of FIG. 2G using a conventional photographic process. In this case, the etching of the interlayer insulating layer 70 is etched away from the etch stop layer 68. Thereafter, the photoresist layer is removed and the etch stop layer 68 is removed using the patterned interlayer insulating layer 70 as a mask. Then, a contact is formed and a barrier metal and tungsten are sequentially stacked to form a contact plug 80. By using CMP or etch back, the barrier metal and tungsten remaining on the interlayer insulating film 70 are removed to complete the borderless contact. In the above case, due to the role of the etch stop layer 68 in the contact hole manufacturing process for forming the borderless contact, it can be seen that the over-etching of the device isolation layer or the trench insulation layer is prevented as in the conventional case. Thereby, there is an advantage that can take a process advantageous for high integration.

If the semiconductor MOS transistor is manufactured by the method of the above-described embodiment, since the salicide is formed only in the gate in the specific region and the salicide is not formed in the active region, the junction leakage is small, so that it can be used stably even in the low power SRAM. The protection performance can be maximized, the interconnect resistance of polysilicon lines can be reduced, the operation speed of semiconductor devices can be increased, and the borderless contact can be applied, thereby reducing the cell size to increase the degree of integration. In addition, in another specific region, the salicide is simultaneously formed at the gate and the active, thereby maximizing the speed of the semiconductor device. In other words, applying the above two factors at the same time has the advantage of making a low power, high speed device.

In the above description, the embodiments of the present invention have been described with reference to the drawings, for example. However, it will be apparent to those skilled in the art that the present invention may be variously modified or changed within the scope of the technical idea of the present invention. . For example, if the matters are different, the order of the processes and the film material or shape may be changed.

By selectively forming the silicide according to the application region as described above, the operation speed of the semiconductor device is improved and the device density due to the application of the borderless contact can be maximized.

Claims (15)

For transistors located in the first region of the substrate, a silicide layer is formed over the gate and over the source / drain active regions, respectively; for transistors located in a second region spaced apart from the first region, the silicide layer is formed. Transistor structure, characterized in that each formed only on the gate. The transistor structure of claim 1, wherein the second region is a memory cell region when the first region is a peripheral region, and the second region is a peripheral region when the first region is a memory cell region. . The transistor structure of claim 1, wherein the silicide layers formed in the first region and the second region are salicide layers that are simultaneously self-aligned. After forming a plurality of transistors each having a gate spacer in a first region and a second region defined in a semiconductor substrate and stacking an etch stop layer on the entire surface, an upper portion of the etch stop layer covering the gate top of the transistors is formed only in the second region. Forming a photosensitive film so as to be exposed; Removing both the etch stop film of the second region and the etch stop film of the first region by using the photoresist as an etch mask; After removing the photoresist layer, a high melting point metal is laminated on the entire surface and a heat treatment process is performed to form both the upper gate and the upper source / drain active region as a silicide layer in the first region, and only the upper gate portion is the silicide layer in the second region. A semiconductor device manufacturing method comprising the step of forming a. The method of claim 4, wherein Sequentially stacking an etch stop film for forming a contact and an interlayer insulating film on the entire surface, and then planarizing them; And etching the interlayer insulating film of the portion of the interlayer insulating film to be formed to the etch stop layer for contact, and then forming a contact plug in electrical contact with the silicide layer. . The semiconductor device of claim 4, wherein the second region is a memory cell region when the first region is a peripheral region, and the second region is a peripheral region when the first region is a memory cell region. Manufacturing method. The method of claim 4, wherein the silicide layers formed in the first region and the second region are salicide layers that are simultaneously self-aligned. In the semiconductor device manufacturing method: A process of forming a isolation insulating film between devices by applying a trench process to a semiconductor substrate, a process of laminating an insulating layer as a gate insulating film and a polycrystalline silicon layer as a gate electrode and a conductor on the front surface and patterning by a conventional photolithography process, and patterned polycrystalline Forming an active region by implanting impurities using a silicon layer as a mask, forming a nitride spacer on the sidewall of the polycrystalline silicon layer, and implanting impurities using the polycrystalline silicon layer and the nitride spacer as a mask Forming an active region of the film, laminating an etch stop film, and applying and baking a photosensitive film; Removing a photoresist film of a desired area on the resultant using a conventional photographic technique; Etching back the photoresist film on the resultant to etch stop the etch stop film on the gate electrode; Removing the etch stop film on the gate electrode using the resulting photoresist as a mask; After removing the photoresist on the resultant layer, a high melting point metal was deposited on the entire surface and reacted with silicon atoms in the polycrystalline silicon layer as the gate electrode and silicon atoms in the single crystal silicon by heat treatment to form a specific region in the gate and source / drain regions. Forming a salicide and forming a salicide only in the gate in another specific region; Sequentially laminating an etch stop film and an interlayer insulating film on the entire surface of the resultant, and then performing polishing to planarize it; After the contact is patterned on the resultant using a conventional photolithography process, the interlayer insulating film is etched using the patterned photoresist film as a mask, and the etching stops at the etch stop layer. The photoresist film is removed and the patterned interlayer insulating film is etched. Forming a contact by removing the stop film, and sequentially stacking the barrier metal and tungsten, and then removing the barrier metal and tungsten on the interlayer insulating film to form a borderless contact. The method of claim 8, wherein the etch stop layer stacked on the polycrystalline silicon layer and the nitride layer spacer is a nitride layer having excellent selectivity with respect to an oxide layer. The method of claim 8, wherein the etching of the photoresist layer until the etch stop layer is exposed on the gate electrode is dry etching having a good selectivity with respect to the etch stop layer. The method of claim 8, wherein the high melting point metal is at least one of cobalt, titanium, nickel, and platinum. The method of claim 8, further comprising, after etching the residual metal film, an additional heat treatment process is further performed to stabilize the silicide film and reduce the resistance. The method of claim 8, wherein the planarization of the interlayer insulating film is CMP or dry etching. The method of claim 8, wherein the etch stop layer deposited after the silicide process is a nitride layer having excellent selectivity with respect to an oxide layer. The method of claim 8, wherein the removing of the barrier metal and tungsten on the interlayer insulating layer is CMP or dry etching.