KR20000000889A - Method for manufacturing semiconductor devices - Google Patents

Abstract

PURPOSE: A fabrication method is provided to simplify manufacturing processes at the time of a selective solicitation of embedded DRAM merged DRAM and logic without critical photo lithographic process. CONSTITUTION: The method comprises the steps of forming a gate electrode(104) on a silicon substrate(100); forming a spacer(106) at both sidewalls of the gate electrode; forming an active region in the substrate by ion-implanting; forming an etch stopper(108) on the resultant structure; forming an insulating layer(110) on the etch stopper; remaining the insulating layer(110) only on the surface of the active region by self-aligning method and chemical mechanical polishing the insulating layer using an etch stopper(108) as a stopping layer; etching the remained insulating layer(110) using a photoresist pattern(112) as a mask and removing the photoresist pattern; etching the remained etch stopper(108); and forming a silicide layer(114) on the surface of the gate electrodes and the active regions.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to the formation of a selective silicide film of highly integrated DRAM or merged DRAM and logic (MDL) in which DRAM and logic are merged. The present invention relates to a method of manufacturing a semiconductor device capable of preventing process defects caused by misalignment without applying a level of photolithography.

As the integration of semiconductor devices increases, the size of the contacts becomes smaller, which causes a problem of increasing the contact resistance of the semiconductor devices. In order to prevent this, a salicide (self-aligned silicide) process has been developed, and application has already begun for a 0.35 μm logic device.

Representative examples of low-resistance metals commonly used in forming salicides include W-polycide, which is a giga-bit class in which the line width of the cell gate is narrowed to 0.2 μm or less. Of DRAM or high-density gate logic merged, there is a limitation in application of W-polyside film due to gate resistance problem. Currently, low-resistance metals such as TiSi and CoSi are commonly used to form a selective silicide film. There is a trend.

When manufacturing a semiconductor device using the salicide process, there is no problem when forming a silicide film over the entire region of the semiconductor device. However, when a silicide film is selectively formed due to a problem in device characteristics, silicide is required. Since a separate photoetch process is required in order to leave a blocking layer (hereinafter referred to as SBL) only at a specific site, a problem such as complicated and difficult process progress is raised.

Since the silicide film forming part must be selectively opened in the presence of the gate step, a critical level of photoetching process is required to suppress process defects due to misalignment during SBL etching, as well as process margin. This is caused by a lot of difficulties in securing, and research is being actively conducted to improve this.

This will be described in the sixth step with reference to the process flow diagram illustrating a method for forming a selective silicide film of the conventional semiconductor device shown in FIGS. 1 to 7 as follows. As an example, in the fabrication of a semiconductor device in which a DRAM and a logic are merged, a silicide layer may be formed on the gate electrode and the active region of the logic forming portion and the gate electrode of the DRAM cell forming portion while avoiding the silicide film formation in the active region of the DRAM cell forming portion. Look at the case of forming. In the drawing, a portion A denotes a DRAM cell forming portion of the semiconductor device, and a portion denoted B denotes a logic forming portion of the semiconductor device.

As a first step, as shown in FIG. 1, a polysilicon gate electrode 14 is formed on a semiconductor substrate (silicon substrate) 10 having a gate insulating film (not shown) and a field oxide film 12. Using this as a mask, a low concentration of impurities are ion-implanted onto the substrate 10 to form a lightly doped drain (LDD) (not shown). Subsequently, spacers 16 made of a nitride film or an oxide film are formed on both sidewalls of the gate electrode 14, and a high concentration of impurities are ion-implanted onto the substrate to form the substrate 10 on both edges of the gate electrode 14. Source and drain active regions (not shown) are formed inside.

As a second step, as shown in FIG. 2, an insulating film 18 of a medium temperature oxide (hereinafter referred to as MTO) material to be used as SBL is formed on the entire surface of the resultant. Here, MTO represents the oxide film grown in the temperature range of 300-600 degreeC.

As a third step, an anti-reflective layer 20 (hereinafter referred to as ARL) 20 is formed on the insulating film 18 as shown in FIG. As such, the formation of the ARL 20 on the insulating film 18 causes a phenomenon that UV light is diffusely reflected on the surface of the insulating film 18 during the subsequent photoetching process. This is because it is difficult to form a fine pattern.

As a fourth step, as shown in FIG. 4, the photoresist film 22 is formed on the ARL 20, and an ARL (on the upper side of the gate electrode 14 of the DRAM cell forming unit A) is formed using a photolithography process. The photoresist film 22 is selectively etched to expose 20 and the surface of the ARL 20 of the logic forming unit B.

As a fifth step, the ARL 20 and the insulating film 18 are sequentially etched using the photosensitive film 22 etched as shown in FIG. 5 as a mask.

As a sixth step, as shown in Figure 6, a high melting point metal of Co, Ti, Ni material is formed on the entire surface of the resultant, and heat treatment is performed. At this time, in the region where the ARL 20 and the insulating film 18 are removed, silicon and the high melting point metal react to form a silicide film 24, which is a low resistance metal, while the insulating film 18 is left or the sidewall spacer 16. In the region where) is formed, silicon and the high melting point metal do not react, and the high melting point metal remains as an unreacted metal. Then, by removing the unreacted high melting point metal, the present process is completed.

However, when the selective silicide film forming process of the semiconductor device is performed as described above, the following problems occur as briefly mentioned above.

The problem does not occur in the region in which the silicide layer is formed on the entire surface, such as the logic forming portion B, but in the region in which the silicide layer is selectively formed only on the surface of the gate electrode 14, such as the DRAM cell forming portion A, the misalignment occurs. This causes a problem that a silicide film is not locally formed on the gate electrode 14 or a silicide film is locally formed in a source / drain region which is an active region. Such a phenomenon is further exacerbated when the size of the fine pattern is reduced due to the high integration of the DRAM cell, and therefore, an improvement for this phenomenon is urgently required.

Accordingly, an object of the present invention is to remove a process defect caused by misalignment without applying a critical level of photoetch process to leave an insulating film used as SBL only in a specific region, thereby selecting a selective silicide film of a semiconductor device. It is to provide a method of manufacturing a semiconductor device that enables to ensure the uniform characteristics of the product when forming.

1 to 6 are process flowcharts illustrating a method of forming a selective silicide film of a conventional semiconductor device;

7 to 11 are process flowcharts showing a method for forming a selective silicide film of a semiconductor device according to the present invention.

In order to achieve the above object, the present invention provides a process for forming a gate electrode on a semiconductor substrate; Forming spacers on both sidewalls of the gate electrode; Forming a source / drain active region in the substrate on both edges of the gate electrode; Forming an etch stopper on the entire surface of the substrate including the gate electrode and the spacer; Forming an insulating film on the etch stopper; CMP-processing the insulating film so that the etch stopper on the gate electrode is exposed so as to self-align the insulating film only on the surface of the active region of the DRAM cell forming portion and the surface of the active region of any other region; Forming a photoresist pattern defining a DRAM cell forming part on the resultant, using the mask as a mask to etch the remaining insulating film in any other region, and then removing the photoresist pattern; Etching the entire surface of the etch stopper in a portion where the insulating film is not remaining; And forming a silicide film on the gate electrode surface of the DRAM cell forming portion and on the gate electrode and the active region surface of any other region.

When the process is performed as described above, a critical level of photoetching process is not necessary for the etching of the insulating film used as SBL, and it is advantageous in terms of securing process margin compared to the conventional case, and thus it is misaligned when forming the self-aligned silicide layer. This can prevent process defects from occurring.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

According to the present invention, the silicide film may be self-aligned to a desired portion without applying a critical level of photoetch process to leave the insulating film used as the SBL only in a specific portion (for example, an active region between the gate electrodes of the DRAM cell forming portion A). It is a technology that focuses on making it possible to selectively form, to eliminate process defects caused by misalignment without compromising the refresh characteristics of the DRAM cell.

Referring to the process flow diagram illustrating a method for forming a selective silicide film of a semiconductor device according to the present invention shown in Figures 7 to 11, it is divided into a fifth step as follows. As an example, in the fabrication of a semiconductor device in which a DRAM and a logic are merged, a silicide layer may be formed on the gate electrode and the active region of the logic forming portion and the gate electrode of the DRAM cell forming portion while avoiding the silicide film formation in the active region of the DRAM cell forming portion. Look at the case of forming. In the drawing, a portion A denotes a DRAM cell forming portion of the semiconductor device, and a portion denoted B denotes a logic forming portion of the semiconductor device.

As a first step, as shown in FIG. 7, a polysilicon gate electrode 104 is formed on a semiconductor substrate (eg, a silicon substrate) 100 having a gate insulating layer (not shown) and a field oxide layer 102. LDD (not shown) is formed by ion implanting impurities of low concentration onto the substrate 100 using the mask as a mask. Next, an insulating film made of an oxide film or a nitride film is formed on the entire surface of the substrate 100 including the gate electrode 104, and then etched back to form spacers 106 made of an insulating film on both sidewalls of the gate electrode 104. Thereafter, a high concentration of impurities are ion-implanted onto the substrate 100 by using the gate electrode 104 and the spacer 106 as a mask, and active source and drain active within the substrate 100 on both edges of the gate electrode 104 are performed. Form an area (not shown).

As a second step, as shown in FIG. 8, an etch stopper 108 formed of a nitride film is formed on the entire surface of the substrate 100 including the gate electrode 104 and the spacer 106, and a gap fill thereon. An insulating film 110 made of a CVD oxide film material having excellent characteristics is formed. In this case, a single layer structure of a high density plasma (HDP) oxide film or a stacked structure of an "HDP oxide film / PE-TEOS oxide film" may be used as the insulating film 110.

As a third step, as shown in FIG. 9, the insulating film 110 is subjected to CMP treatment until the etch stopper 108 on the gate electrode 104 is exposed, so that the surface of the active region of the DRAM cell forming portion A is formed. Only a few hundred 절연막 or more insulating films 110 to be used as SBLs remain in the self-alignment only on the active region surface of the logic forming unit B. At this time, the gate electrode 104 formed on the field oxide film 102 has a higher step height than the gate electrode 104 formed on another portion (for example, the active region), and thus the etch stopper on the surface of the gate electrode 104 in the CMP process. Almost 108 will be removed.

As a fourth step, as shown in FIG. 10, a photoresist pattern 112 defining a DRAM cell forming portion A is formed on the resultant, and any other area (for example, logic) is formed using the photoresist pattern 112 as a mask. The remaining insulating film 110 of the forming portion is removed. In this case, the remaining insulating layer 110 is removed by a wet etching process using LAL as an etchant.

As a fifth step, as shown in FIG. 11, the photoresist pattern 112 is removed, and the etch stopper 108 is removed by etching the region except for the portion where the insulating layer 110 remains. The gate electrode surface of the portion A and the gate electrode surface and the active region surface of the logic forming portion B) are exposed. In this case, the etch stopper 108 may be etched by a dry etching process or a raido frequency (RF) etching process. Subsequently, a high melting point metal made of Co, Ti, or Ni is formed on the entire surface of the substrate 100 including the gate electrode 104, the spacer 106, and the remaining insulating film 110 used as SBL, and heat treatment is performed. At this time, in the region where the insulating layer 110 is removed, silicon and the high melting point metal react to form a silicide layer 114 which is a low resistance metal, whereas in the region where the insulating layer 110 remains or the spacer 106 is formed And the high melting point metal does not react, and the high melting point metal remains as unreacted metal. Then, the unreacted high melting point metal is removed using sulfuric acid to complete the present process.

In this case, since the etching process of the insulating film 110 used as the SBL is performed by the CMP process, a critical level of photoetching process is not required when forming the selective silicide layer, and the process margin is compared with the conventional case. Securing is advantageous, making it possible to eliminate process defects caused by misalignment. In addition, this can improve the yield, it is possible to obtain a great effect in terms of cost reduction.

In the present invention, in order to facilitate the understanding of the above-described process, specific reference to silicide film formation in the peripheral circuit portion, the input and output terminals, etc. has been avoided for convenience, but the above-described process is also applied to the formation of the selective silicide film.

As described above, according to the present invention, since the insulating film used as SBL is etched by a CMP process using an etch stopper instead of a critical level of photoetching process, a process margin can be secured, thus making it difficult to form a selective silicide film. Process defects caused by phosphorus (e.g., a defect in which no silicide film is locally formed on the gate electrode, or an active source or a silicide film is locally formed in the drain region) can be eliminated. Since it is possible to ensure a uniform characteristic of the high reliability semiconductor device can be implemented.

Claims (10)

Forming a gate electrode on the semiconductor substrate; Forming spacers on both sidewalls of the gate electrode; Forming a source / drain active region in the substrate on both edges of the gate electrode; Forming an etch stopper on the entire surface of the substrate including the gate electrode and the spacer; Forming an insulating film on the etch stopper; CMP-processing the insulating film so that the etch stopper on the gate electrode is exposed so as to self-align the insulating film only on the surface of the active region of the DRAM cell forming portion and the surface of the active region of any other region; Forming a photoresist pattern defining a DRAM cell forming part on the resultant, using the mask as a mask to etch the remaining insulating film in any other region, and then removing the photoresist pattern; Etching the entire surface of the etch stopper in a portion where the insulating film is not remaining; And And forming a silicide film on the gate electrode surface of the DRAM cell forming portion and on the gate electrode and the surface of the active region in any other region. The method of claim 1, wherein the insulating film is formed by a single layer structure of an HDP oxide film or a stacked structure of an "HDP oxide film / PE-TEOS oxide film". The method of claim 1, wherein the etch stopper is formed of a nitride film. The method of claim 1, wherein the remaining insulating film is wet etched. The method of claim 4, wherein the wet etching is performed by using LAL as an etchant. The method of claim 1, wherein the etch stopper is etched by a dry etching process or an RF etching process. The method of claim 1, wherein the silicide film Forming a high melting point metal on an entire surface of the substrate including the gate electrode, the spacer, and the remaining insulating film, and heat-treating the same; A method of manufacturing a semiconductor device, characterized in that formed through a process of removing the unreacted high melting point metal. The method of claim 7, wherein the high melting point metal is formed of any one selected from Co, Ti, and Ni. 8. The method of claim 7, wherein the unreacted high melting point metal is removed with sulfuric acid. The method of claim 1, wherein the arbitrary region is a peripheral circuit portion or a logic forming portion of the DRAM.