KR100543637B1 - Manufacturing Method of Flash Memory Device - Google Patents
Manufacturing Method of Flash Memory Device Download PDFInfo
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- KR100543637B1 KR100543637B1 KR1019980060328A KR19980060328A KR100543637B1 KR 100543637 B1 KR100543637 B1 KR 100543637B1 KR 1019980060328 A KR1019980060328 A KR 1019980060328A KR 19980060328 A KR19980060328 A KR 19980060328A KR 100543637 B1 KR100543637 B1 KR 100543637B1
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- ion implantation
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- memory device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 12
- 238000000206 photolithography Methods 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 239000010410 layer Substances 0.000 description 2
- 230000000593 degrading effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 플래쉬 메모리 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory device.
2. 발명이 이루고자하는 기술적 과제2. The technical problem of the invention
SAS 공정을 이용하는 플래쉬 메모리 소자의 제조 공정에서 소오스 라인의 선폭이 감소하는 것을 방지하고 소오스 라인의 저항이 증가되는 것을 방지하므로써 소자의 성능을 향상시킬 수 있도록 한다.In the manufacturing process of the flash memory device using the SAS process it is possible to improve the performance of the device by preventing the line width of the source line is reduced and the resistance of the source line is increased.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
본 발명에서는 SAS 공정에서 공통 소오스 라인을 확정한 후 기판을 식각하여 트렌치를 형성하고, 트렌치에 경사 이온 주입 방법으로 불순물 이온을 주입한 후 공통 소오스 및 드레인 형성을 위한 불순물 이온을 주입 공정을 실시하여 소오스 라인의 선폭을 대폭 증대시킬 수 있다.In the present invention, after the common source line is determined in the SAS process, the substrate is etched to form a trench, the impurity ions are implanted in the trench by a gradient ion implantation method, and then the impurity ions for forming the common source and drain are implanted. The line width of the source line can be significantly increased.
Description
본 발명은 플래쉬 메모리 소자의 제조 방법에 관한 것으로, 특히 자기정렬 소오스 공정에서의 고집적화로 소오스 라인의 선폭이 좁아지면서 소오스 저항 증가로 인한 소자 성능의 악화를 개선하기 위해 기판 식각 공정으로 트렌치 구조의 소오스 라인을 형성하여 셀의 전류 증가를 방지할 수 있는 플래쉬 메모리 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device. In particular, a source structure of a trench structure is formed by a substrate etching process to improve deterioration of device performance due to an increase in source resistance as the line width of the source line is narrowed due to high integration in a self-aligned source process. The present invention relates to a method of manufacturing a flash memory device capable of forming lines to prevent an increase in current in a cell.
플래쉬 메모리 소자의 집적도를 향상시키기 위해 적층 구조의 셀에서 셀과 셀간의 소오스 공간을 좁히는 자기정렬 소오스(self-aligned source; 이하 SAS라 함) 공정을 이용하고 있다. 이를 위해 적층 구조의 게이트 전극이 형성된 상태에서 별도의 SAS 마스크를 이용한 포토리소그라피 공정 및 식각 공정을 실시하여 셀의 소오스 영역을 오픈한 후 인접된 셀과의 공통 소오스 라인을 형성하기 위해 필드 산화막을 제거하는 이방성(anisotropic) 식각 공정을 실시한다.In order to improve the degree of integration of flash memory devices, a self-aligned source (hereinafter referred to as SAS) process is used to narrow the cell space between cells in a stacked cell. To this end, a photolithography process and an etching process using a separate SAS mask are performed while a gate electrode having a stacked structure is formed to open a source region of a cell, and then a field oxide film is removed to form a common source line with adjacent cells. An anisotropic etching process is performed.
이러한 공정으로 셀의 소오스 라인을 형성하는 종래의 SAS 공정을 이용한 플래쉬 메모리 소자의 제조 방법을 도 1을 참조하여 설명하기로 한다.A method of manufacturing a flash memory device using a conventional SAS process of forming a source line of a cell by such a process will be described with reference to FIG. 1.
도 1은 종래의 플래쉬 메모리 소자의 제조 방법을 설명하기 위한 셀의 단면도이다.1 is a cross-sectional view of a cell for explaining a method of manufacturing a conventional flash memory device.
반도체 기판(101)의 선택된 영역에 필드 산화막(도시안됨)을 형성하여 액티브 영역과 필드 영역을 분리한다. 액티브 영역의 반도체 기판(101) 상부에 터널 산화막(102), 제 1 폴리실리콘막(103), 유전체막(104), 제 2 폴리실리콘막(105), 텅스텐실리사이드막(106) 및 질화막(107)을 순차적으로 형성한다. 게이트 마스크를 이용한 포토리소그라피 공정 및 식각 공정을 실시하여 플로팅 게이트와 콘트롤 게이트가 적층된 스택 게이트를 형성한다. SAS 마스크를 이용하여 셀의 콘트롤 게이트(워드라인)을 따라 형성될 공통 소오스 라인을 확정한 후 불순물 이온 주입 공정을 실시하고, 인접된 셀과 셀간의 소오스 라인을 형성하기 위해 산화막 식각 공정으로 필드 산화막을 제거한다. 마스크 공정을 실시하여 셀 소오스 및 드레인 영역을 확정한 후 불순물 이온 주입 공정을 실시하여 소오스(108) 및 드레인(109)을 형성한다.A field oxide film (not shown) is formed in the selected region of the semiconductor substrate 101 to separate the active region and the field region. The tunnel oxide film 102, the first polysilicon film 103, the dielectric film 104, the second polysilicon film 105, the tungsten silicide film 106 and the nitride film 107 over the semiconductor substrate 101 in the active region. ) Are formed sequentially. A photolithography process and an etching process using a gate mask are performed to form a stack gate in which a floating gate and a control gate are stacked. After defining a common source line to be formed along the control gate (word line) of the cell using a SAS mask, an impurity ion implantation process is performed, and a field oxide film is formed by an oxide layer etching process to form a source line between adjacent cells and cells. Remove it. After the mask process is performed to determine the cell source and drain regions, an impurity ion implantation process is performed to form the source 108 and the drain 109.
셀의 집적도를 향상시키기 위한 상기와 같은 SAS 공정은 소오스 라인의 폭을 감소시키면서 이루어지기 때문에 외부 저항(external resistance)의 증가를 가져온다. 이로 인해 소자 동작시 소오스 라인의 저항 증가에 의해 셀 전류를 감소시켜 소자의 성능을 저하시킨다.Such a SAS process for improving the density of cells is performed while reducing the width of the source line, resulting in an increase in external resistance. As a result, the cell current is reduced by increasing the resistance of the source line during device operation, thereby degrading device performance.
따라서, 본 발명은 소오스 라인의 선폭이 감소하는 것을 방지하여 소오스 라인의 저항이 증가되는 것을 방지하므로써 소자의 성능을 향상시킬 수 있는 플래쉬 메모리 소자의 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of improving the performance of the device by preventing the line width of the source line from being reduced and thereby increasing the resistance of the source line.
상술한 목적을 달성하기 위한 본 발명은 필드 영역 및 액티브 영역이 확정된 반도체 기판이 제공되고, 상기 액티브 영역의 상기 반도체 기판 상부에 플로팅 게이트 및 콘트롤 게이트가 적층된 스택 게이트를 형성하는 단계와, SAS 마스크를 이용한 포토리소그라피 공정 및 식각 공정을 실시하여 공통 소오스 라인을 확정하는 단계와, 상기 공통 소오스 라인을 확정하여 노출된 상기 필드 영역의 필드 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 단계와, 상기 트렌치의 측벽에 제1 불순물을 이온 주입 공정을 실시하는 단계와, 셀 소오스 및 드레인 영역을 확정한 후 제2 불순물 이온 주입 공정을 실시하여 상기 스택 게이트 일측의 상기 트렌치 양 측벽 및 하부에 공통 송스를 형성하고, 상기 스택 게이트 다른 측의 상기 반도체 기판에 드레인을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a semiconductor substrate in which a field region and an active region are defined, and forming a stack gate in which a floating gate and a control gate are stacked on the semiconductor substrate in the active region. Determining a common source line by performing a photolithography process and an etching process using a mask; forming a trench by etching the field oxide film and the semiconductor substrate of the exposed field region by determining the common source line; Performing a ion implantation process on the sidewalls of the trench with an ion implantation process, and determining a cell source and a drain region, and then performing a second impurity ion implantation process to form a common song on both sidewalls and a lower portion of the trench on one side of the stack gate. And drain the semiconductor substrate on the other side of the stack gate. Including the step of: characterized by comprising.
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(d)는 본 발명에 따른 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 셀의 단면도이다.2 (a) to 2 (d) are cross-sectional views of cells sequentially shown to explain a method of manufacturing a flash memory device according to the present invention.
도 2(a)를 참조하면, 반도체 기판(201)상의 선택된 영역에 필드 산화막(도시안됨)을 형성하여 액티브 영역과 필드 영역을 확정한다. 액티브 영역의 반도체 기판(201) 상부에 터널 산화막(202), 제 1 폴리실리콘막(203), 유전체막(204), 제 2 폴리실리콘막(205), 텅스텐실리사이드막(206) 및 질화막(207)을 순차적으로 형성한다. 게이트 마스크를 이용한 포토리소그라피 공정 및 식각 공정을 실시하여 플로팅 게이트와 콘트롤 게이트가 적층된 스택 게이트를 형성한다.Referring to FIG. 2A, a field oxide film (not shown) is formed in a selected region on the semiconductor substrate 201 to determine an active region and a field region. The tunnel oxide film 202, the first polysilicon film 203, the dielectric film 204, the second polysilicon film 205, the tungsten silicide film 206, and the nitride film 207 on the semiconductor substrate 201 in the active region. ) Are formed sequentially. A photolithography process and an etching process using a gate mask are performed to form a stack gate in which a floating gate and a control gate are stacked.
도 2(b)를 참조하면, 전체 구조 상부에 감광막(208)을 형성한 후 SAS 마스크를 이용하여 패터닝한다. 이때, SAS 마스크에 의해 패터닝된 감광막(208)은 셀의 콘트롤 게이트(워드라인)를 따라 형성될 공통 소오스 라인을 노출시키도록 형성된다. 패터닝된 감광막(208)을 마스크로 인접된 셀과 셀간을 잇는 소오스 라인을 형성하기 위해 필드 산화막을 제거한다. 소오스 라인의 유효 폭(effective width)을 증가시키기 위해 비등방성 식각 공정으로 기판을 식각하여 트렌치(209)를 형성한다.Referring to FIG. 2B, the photoresist layer 208 is formed on the entire structure, and then patterned using a SAS mask. In this case, the photosensitive film 208 patterned by the SAS mask is formed to expose a common source line to be formed along the control gate (word line) of the cell. Using the patterned photoresist 208 as a mask, the field oxide film is removed to form a source line between the adjacent cells and the cells. The trench 209 is formed by etching the substrate using an anisotropic etching process to increase the effective width of the source line.
도 2(c)를 참조하면, 패터닝된 감광막(208)을 마스크로 트렌치(209)의 측벽에 경사 이온 주입(tilting implantation) 방법으로 불순물을 이온 주입한다. 이때, 주입되는 불순물 이온의 양은 두 번에 걸쳐 나누어 주입한다.Referring to FIG. 2C, impurities are implanted into the sidewall of the trench 209 using a patterned photoresist 208 as a mask by a tilting implantation method. At this time, the amount of impurity ions to be implanted is divided into two times.
도 2(d)를 참조하면, 패터닝된 감광막(208)을 제거하고 전체 구조 상부에 또다른 감광막(도시안됨)을 형성한 후 마스크 공정으로 셀 소오스 및 드레인 영역을 확정한다. 불순물 이온 주입 공정을 실시하여 스택 게이트 일측의 트렌치(209) 양 측벽 및 하부에 공통 소오스(210)를 형성하고, 스택 게이트 다른 측의 반도체 기판(201)에 드레인(211)을 형성한다.Referring to FIG. 2 (d), the patterned photoresist 208 is removed and another photoresist (not shown) is formed over the entire structure, and then the cell source and drain regions are determined by a mask process. The impurity ion implantation process is performed to form a common source 210 on both sidewalls and a bottom of the trench 209 on one side of the stack gate, and a drain 211 is formed on the semiconductor substrate 201 on the other side of the stack gate.
이후, 층간 절연막을 형성한 후 셀의 소오스, 드레인 및 게이트 단자를 연결시키기 위한 콘택을 형성한다. 그리고 소자 보호막을 형성하는 등의 일반적인 반도체 소자의 제조 공정을 실시한다.Thereafter, after forming the interlayer insulating film, a contact for connecting the source, drain and gate terminals of the cell is formed. And a general semiconductor element manufacturing process, such as forming an element protective film, is performed.
상술한 바와 같이 본 발명에 의하면 종래에 비해 소오스 라인을 약 2배 정도 넓게 형성할 수 있다. 따라서, 동일한 디자인 룰에 의한 같은 셀 면적에서도 소오스 라인의 선폭 증가를 얻을 수 있어 셀 정보를 읽을 경우 셀의 전류는 증가하게 되고, 소자의 성능을 향상시킬 수 있다. 이와 같이 본 발명에 따라 플래쉬 메모리 소자를 제조하면 차세대 소자 제조시 셀의 고집적화를 실현하면서 셀의 성능 또한 향상시킬 수 있다.As described above, according to the present invention, a source line can be formed about twice as wide as in the prior art. Therefore, the line width of the source line can be increased even in the same cell area by the same design rule. When the cell information is read, the current of the cell is increased and the performance of the device can be improved. As described above, if the flash memory device is manufactured according to the present invention, the cell performance may be improved while realizing high integration of the cell in manufacturing the next generation device.
도 1은 종래의 플래쉬 메모리 소자의 제조 방법을 설명하기 위한 셀 단면도.1 is a cross-sectional view of a cell for explaining a method of manufacturing a conventional flash memory device.
도 2(a) 내지 도 2(d)는 본 발명에 따른 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 셀 단면도.2 (a) to 2 (d) are cell cross-sectional views sequentially shown for explaining a method of manufacturing a flash memory device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
101 및 201 : 반도체 기판 102 및 202 : 터널 산화막101 and 201: semiconductor substrates 102 and 202: tunnel oxide film
103 및 203 : 제 1 폴리실리콘막 104 및 204 : 유전체막103 and 203: first polysilicon film 104 and 204: dielectric film
105 및 205 : 제 2 폴리실리콘막 106 및 206 : 텅스텐실리사이드막105 and 205: second polysilicon film 106 and 206: tungsten silicide film
107 및 207 : 질화막 108 및 210 : 소오스107 and 207: nitride films 108 and 210: source
109 및 211 : 드레인 208 : 감광막109 and 211: drain 208: photosensitive film
209 : 트렌치209: trench
Claims (4)
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| KR1019980060328A KR100543637B1 (en) | 1998-12-29 | 1998-12-29 | Manufacturing Method of Flash Memory Device |
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| KR1019980060328A KR100543637B1 (en) | 1998-12-29 | 1998-12-29 | Manufacturing Method of Flash Memory Device |
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| KR100861792B1 (en) * | 2002-07-16 | 2008-10-08 | 매그나칩 반도체 유한회사 | NOR type flash memory device having a buried source line and method for fabricating the same |
| KR100884472B1 (en) * | 2002-12-30 | 2009-02-20 | 동부일렉트로닉스 주식회사 | Manufacturing method of flash memory |
| KR100529605B1 (en) | 2003-10-01 | 2005-11-17 | 동부아남반도체 주식회사 | Fabrication method of semiconductor device |
| KR100661230B1 (en) * | 2004-12-30 | 2006-12-22 | 동부일렉트로닉스 주식회사 | Flash memory cell and method for manufacturing the same |
| KR100958632B1 (en) * | 2007-05-17 | 2010-05-20 | 주식회사 동부하이텍 | Fabricating Method of Flash Memory Device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH05275713A (en) * | 1991-12-19 | 1993-10-22 | Philips Gloeilampenfab:Nv | Nonvolatile storage device and manufacture thereof |
| KR970018611A (en) * | 1995-09-14 | 1997-04-30 | 김주용 | Nonvolatile Memory Cells and Manufacturing Method Thereof |
| JPH09252058A (en) * | 1996-03-15 | 1997-09-22 | Rohm Co Ltd | Semiconductor memory device and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05275713A (en) * | 1991-12-19 | 1993-10-22 | Philips Gloeilampenfab:Nv | Nonvolatile storage device and manufacture thereof |
| KR970018611A (en) * | 1995-09-14 | 1997-04-30 | 김주용 | Nonvolatile Memory Cells and Manufacturing Method Thereof |
| JPH09252058A (en) * | 1996-03-15 | 1997-09-22 | Rohm Co Ltd | Semiconductor memory device and manufacture thereof |
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