KR970018611A - Nonvolatile Memory Cells and Manufacturing Method Thereof - Google Patents

Nonvolatile Memory Cells and Manufacturing Method Thereof Download PDF

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KR970018611A
KR970018611A KR1019950029991A KR19950029991A KR970018611A KR 970018611 A KR970018611 A KR 970018611A KR 1019950029991 A KR1019950029991 A KR 1019950029991A KR 19950029991 A KR19950029991 A KR 19950029991A KR 970018611 A KR970018611 A KR 970018611A
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layer
nonvolatile memory
film
oxide film
silicon substrate
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KR1019950029991A
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KR0182869B1 (en
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박승희
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)

Abstract

발명은 비휘발성 메모리 셀 및 그 제조 방법에 관한 것으로, 프로그램의 효율을 향상시키기 위하여 실리콘 기판에 형성된 리세스(Recess) 구조의 중앙부에 드레인영역을 형성하고, 상기 리세스 구조의 양측부에 경사진 채널(Channel)이 형성되도록 하므로써 소자의 특성 및 동작 속도가 향상될 수 있도록 한 비휘발성 메모리 셀 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell and a method of manufacturing the same, wherein a drain region is formed in a central portion of a recess structure formed in a silicon substrate and is inclined at both sides of the recess structure in order to improve program efficiency. The present invention relates to a nonvolatile memory cell and a method of manufacturing the same, by which a channel can be formed so that the characteristics and operation speed of the device can be improved.

Description

비휘발성 메모리 셀 및 그 제조방법Nonvolatile Memory Cells and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2G도는 본 발명에 따른 비휘발성 메모리 셀의 제조방법을 설명하기 위한 소자의 단면도.2A to 2G are cross-sectional views of a device for explaining a method of manufacturing a nonvolatile memory cell according to the present invention.

Claims (8)

비휘발성 메모리 셀의 제조 방법에 있어서, 실리콘 기판상에 패드 산화막 및 질화막을 순차적으로 형성한 후 드레인 지역 및 상기 드레인 지역 양측부에 형성될 채널 지역의 일부를 포함하는 부분의 상기 패드 산화막이 노출되도록 상기 질화막을 패터닝하는 단계와; 상기 단계로부터 상기 패터닝된 질화막을 산화 방지층으로 이용한 산화 공정으로 상기 드레인 지역 및 상기 드레인 지역 양측부에 형성될 채널 지역의 일부를 포함하는 부분의 상기 실리콘기판에 필드산화막을 형성하는 단계와, 상기 단계로부터 상기 질화막을 제거한 후 상기 필드산화막 하부의 실리콘기판에는 채널 이온이 주입되지 않도록 전체 상부면에 채널 이온을 주입하는 단계와, 상기 단계로부터 상기 필드산화막 및 패드 산화막을 제거하는 단계와, 상기 단계로부터 전체 상부연에 채널 산화막, 제1폴리실리콘층, 유전체막 및 제2폴리실리콘층을 순차적으로 형성하는 단계와, 상기 단계로부터 게이트전극용 마스트를 이용한 식각 공정으로 상기 제2폴리실리콘층, 유전체막, 제1폴리실리콘층 터널 산화막을 순차적으로 패터닝하여 상기 실리콘기판의 채널 지역 상부에 게이트전극을 형성하는 단계와; 상기 단계로부터 노출된 실리콘기판에 불순물 이온을 주입하여 소오스 및 드레인영역을 형성하는 단계로 이루어지는 것을 특징으로 하는 비휘발성 메모리 셀의 제조 방법.In the method of manufacturing a nonvolatile memory cell, a pad oxide film and a nitride film are sequentially formed on a silicon substrate so that the pad oxide film of a portion including a drain region and a part of a channel region to be formed at both sides of the drain region is exposed. Patterning the nitride film; Forming a field oxide film on the silicon substrate in a portion including the drain region and a part of the channel region to be formed at both sides of the drain region by an oxidation process using the patterned nitride film as an anti-oxidation layer from the step; Removing the nitride film from the semiconductor substrate and implanting channel ions into the entire upper surface of the silicon substrate under the field oxide film so as to prevent channel ions from being implanted; removing the field oxide film and the pad oxide film from the step; Sequentially forming a channel oxide film, a first polysilicon layer, a dielectric film, and a second polysilicon layer on the entire upper edge, and etching the second polysilicon layer and the dielectric film from an etch process using a gate electrode mast. The silicon by sequentially patterning a first polysilicon layer tunnel oxide layer Forming a gate electrode on the channel region of the top plate and; And implanting impurity ions into the silicon substrate exposed from the step to form a source and a drain region. 제1항에 있어서, 상기 유전체막은 하부산화막, 질화막 및 상부산화막이 순차적으로 적층되어 형성된 것을 특징으로 하는 비휘발성 메모리 셀의 제조 방법.The method of claim 1, wherein the dielectric layer is formed by sequentially stacking a lower oxide layer, a nitride layer, and an upper oxide layer. 제1항에 있어서, 상기 게이트전극을 형성하기 위한 식각 공정은 지기 정렬 식각 방법으로 실시되는 것을 특징으로 하는 비휘발성 메모리 셀의 제조 방법.The method of claim 1, wherein the etching process for forming the gate electrode is performed by a substrate alignment etching method. 제1 또는 제3항에 있어서, 상기 게이트전극은 터널산화막, 플로팅게이트, 유전체막 및 콘트롤 게이트가 적층된 구조로 형성된 것을 특징으로 하는 비휘발성 메모리 셀의 제조 방법.The method of claim 1, wherein the gate electrode is formed of a structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked. 소오스 및 드레인영역이 형성된 실리콘 기판과, 상기 소오스 및 드레인영역 사이의 상기 실리콘 기판상에 형성된 게이트전극으로 이루어진 비휘발성 메모리 셀에 있어서, 상기 소오스 및 드레인영역 사이의 실리콘기판의 표면이 경사면으로 이루어진 것을 특징으로 하는 비휘발성 메모리 셀.A nonvolatile memory cell comprising a silicon substrate having a source and a drain region formed thereon, and a gate electrode formed on the silicon substrate between the source and drain regions, wherein the surface of the silicon substrate between the source and drain regions is formed with an inclined surface. A nonvolatile memory cell characterized by the above. 제5항에 있어서, 상기 드레인영역이 상기 소오스영역보다 낮게 형성된 것을 특징으로 하는 비휘발성 메모리 셀.6. The nonvolatile memory cell of claim 5, wherein the drain region is formed lower than the source region. 제5항에 있어서, 게이트 전극은 터널산화막, 플로팅게이트, 유전체막 및 콘트롤 게이트가 적층된 구조로 형성된 것을 특징으로 하는 비휘발성 메모리셀.6. The nonvolatile memory cell of claim 5, wherein the gate electrode has a structure in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked. 제7항에 있어서, 상기 유전체막은 하부산화막, 질화막 및 상부산화막이 순차적으로 적층되어 형성된 것을 특징으로 하는 비휘발성 메모리 셀.The nonvolatile memory cell of claim 7, wherein the dielectric layer is formed by sequentially stacking a lower oxide layer, a nitride layer, and an upper oxide layer.
KR1019950029991A 1995-09-14 1995-09-14 Non-volatile memory cell and manufacturing method thereof KR0182869B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543637B1 (en) * 1998-12-29 2006-03-28 주식회사 하이닉스반도체 Manufacturing Method of Flash Memory Device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618709B1 (en) * 2005-03-15 2006-09-06 주식회사 하이닉스반도체 Method for forming gate in semiconductor device
KR100717280B1 (en) 2005-08-22 2007-05-15 삼성전자주식회사 Cell array of semiconductor memory device and method of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100543637B1 (en) * 1998-12-29 2006-03-28 주식회사 하이닉스반도체 Manufacturing Method of Flash Memory Device

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