KR940006683B1 - Structure nand type rom cell and fabricating method thereof - Google Patents

Structure nand type rom cell and fabricating method thereof Download PDF

Info

Publication number
KR940006683B1
KR940006683B1 KR1019910018225A KR910018225A KR940006683B1 KR 940006683 B1 KR940006683 B1 KR 940006683B1 KR 1019910018225 A KR1019910018225 A KR 1019910018225A KR 910018225 A KR910018225 A KR 910018225A KR 940006683 B1 KR940006683 B1 KR 940006683B1
Authority
KR
South Korea
Prior art keywords
gate
polysilicon
nand type
type rom
rom cell
Prior art date
Application number
KR1019910018225A
Other languages
Korean (ko)
Other versions
KR930009069A (en
Inventor
이윤기
Original Assignee
금성 일렉트론 주식회사
문정환
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 금성 일렉트론 주식회사, 문정환 filed Critical 금성 일렉트론 주식회사
Priority to KR1019910018225A priority Critical patent/KR940006683B1/en
Publication of KR930009069A publication Critical patent/KR930009069A/en
Application granted granted Critical
Publication of KR940006683B1 publication Critical patent/KR940006683B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Abstract

The method is for manufacturing NAND type ROM cells without channel shortage and enhanced integration rate by formation of double polysilicon gate poly. The method consists of the four steps of: (A) forming a gate process by depositoin of a silicon dioxide film (2) on the substrate (1) and depositing a polysilicon layer (3); (B) coating and etching of photoresist and injection of n+ ion; (C) depositing and etching of a second silicon dioxide film (6) through the photo etch process, (D) depositing a second polysilicon layer and contact with the previously deposited polysilicon layer for the formation of a gate array.

Description

NAND형 ROM셀의 제조방법 및 그 구조Manufacturing method of NAND ROM cell and its structure

제1도 내지 제3도는 종래의 ROM셀 구조 및 단면도.1 to 3 show a conventional ROM cell structure and cross-sectional view.

제4도 내지 제8도는 본 발명의 ROM셀 제조 공정 및 구조도.4 to 8 is a ROM cell manufacturing process and structure diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 제1게이트 산화막1 silicon substrate 2 first gate oxide film

3 : 제1폴리실리콘 4 : 포토레지스트3: first polysilicon 4: photoresist

5 : 소스/드레인 6 : 제2게이트 산화막5: source / drain 6: second gate oxide film

7 : 제2폴리 실리콘7: second polysilicon

본 발명은 NAND형 ROM셀의 제조 방법 및 구조에 관한 것으로, 특히 셀의 사이즈가 축소됨으로서 발생되는 숏 채널(Short Channel) 효과를 줄이도록 한 NAND형 ROM셀의 제조방법 및 구조에 관한 것이다.The present invention relates to a manufacturing method and structure of a NAND type ROM cell, and more particularly, to a manufacturing method and structure of a NAND type ROM cell to reduce the short channel effect caused by the reduction in the size of the cell.

종래의 NAND형 ROM셀의 트랜지스터는 제1도에 도시된 바와같이 직렬로 연결되어 있다. 그 제조방법을 보면 제2도에 도시된 바와같이, 실리콘기판(1)위에 게이트 산화막(2)을 형성하고 폴리 실리콘(3)을 증착한다. 그 후 포토에치 공정으로 게이트 폴리를 만들고 n+이온을 주입하여 셀의 트랜지스터를 형성하게 된다.Transistors of the conventional NAND type ROM cell are connected in series as shown in FIG. As shown in FIG. 2, a gate oxide film 2 is formed on a silicon substrate 1 and polysilicon 3 is deposited. After that, a gate poly is formed by a photoetch process and n + ions are implanted to form a transistor of a cell.

제3도는 이와같이 형성된 셀의 평면 구조로서, 액티브 영역위로 폴리실리콘이 지나가는 부분이 셀 트랜지스터가 된다.3 is a planar structure of the cell formed as described above, wherein a portion of the polysilicon passing over the active region becomes a cell transistor.

이와같은 종래의 NAND형 ROM셀에서는 폴리실리콘과 폴리실리콘 사이의 간격이 제한되어 있어서, 셀면적 축소에는 한계가 있다.In such a conventional NAND type ROM cell, the spacing between polysilicon and polysilicon is limited, so that there is a limit to the cell area reduction.

본 발명은 이러한 문제점을 해결하기 위한 것으로서 첨부된 도면 제4 내지 8도를 참조하여 상술하면 다음과 같다.The present invention is to solve this problem as described above with reference to the accompanying drawings 4 to 8 as follows.

제4도 내지 8도는 본 발명의 ROM셀 제조 공정도로서, 먼저 제4도에 도시된 바와같이 실리콘 기판(1)상에 제 1게이트 산화막(2)을 형성하고 제 1폴리실리콘(3)을 증착한 다음 포토에치 공정으로 게이트 폴리를 형성한다.4 to 8 are process charts for manufacturing a ROM cell of the present invention. First, as shown in FIG. 4, a first gate oxide film 2 is formed on a silicon substrate 1 and the first polysilicon 3 is deposited. The gate poly is then formed by a photoetch process.

그후 제5도에 도시된 바와같이, 포토레지스트(4)를 입힌 후 정의하고 n+이온을 주입하여 셀 트랜지스터의 소스/드레인(5)을 형성한다.Then, as shown in FIG. 5, the photoresist 4 is coated and then defined and n + ions are implanted to form the source / drain 5 of the cell transistor.

그후 제6도와 같이, 제2게이트 산화막(6)을 형성하고 포토공정으로 폴리 게이트 상의 제2게이트 산화막 일부를 식각한다.Thereafter, as shown in FIG. 6, the second gate oxide film 6 is formed and a portion of the second gate oxide film on the poly gate is etched by a photo process.

계속해서 제7도와 같이, 제2폴리 실리콘(7)을 증착하여 제1폴리실리콘과 제2폴리실리콘을 접측시켜 동일한 게이트를 형성시킨다.Subsequently, as shown in FIG. 7, the second polysilicon 7 is deposited to contact the first polysilicon and the second polysilicon to form the same gate.

제8도는 상기 공정으로 제조된 ROM셀의 평면 구조도이다.8 is a plan view of a ROM cell manufactured by the above process.

이와같이 본 발명의 구조로 된 NAND형 ROM셀을 사용하므로, 셀의 면적이 줄어들고, 제1폴리 실리콘들 사이의 간격을 채널로 형성시키므로 이때 발생되는 숏 채널(Short Channel)효과를 제거시킬 수 있다.As described above, since the NAND type ROM cell having the structure of the present invention is used, the area of the cell is reduced, and the gap between the first polysilicon is formed as a channel, so that the short channel effect generated at this time can be eliminated.

Claims (2)

NAND형 ROM셀 제조 방법에 있어서, 실리콘 기판상에 제1게이트 산화막을 형성하고 제1폴리실리콘을 증착한 다음 포토에치 공정으로 게이트를 형성하는 단계(a)와, 포토 레지스트를 입힌 후 정의하여 n+이온이 이미 형성된 게이트를 하나씩 건너서 주입하는 단계(b)와, 제2게이트 산화막을 형성하고 포토공정으로 폴리게이트 상의 제2게이트 산화막 일부를 식각하는 단계(c)와, 제2폴리실리콘을 증착하여 제1폴리실리콘과 제2폴리 실리콘을 접촉시켜 동일 게이트를 형성하는 단계(d)를 포함하는 것을 특징으로 하는 NAND형 ROM셀 제조방법.In the NAND type ROM cell manufacturing method, the step of forming a first gate oxide film on a silicon substrate, depositing the first polysilicon and forming a gate by a photoetch process (a), and after applying a photo resist (b) implanting a gate having n + ions already formed thereon one by one, forming a second gate oxide layer and etching a portion of the second gate oxide layer on the polygate by a photo process (c), and the second polysilicon And (d) depositing and contacting the first polysilicon and the second polysilicon to form the same gate. NAND형 ROM셀 구조에 있어서, 실리콘 기판 상에는 게이트 산화막 및 게이트 폴리가 형성되고, 게이트 폴리상부의 일부를 제외하고는 게이트와 실리콘 기판을 절연시키는 게이트 산화막이 형성되어 있고, 산기 산화막이 제거된 게이트 폴리부상에는 제2폴리실리콘이 형성되어 게이트 폴리와 동일 게이트로 사용되는 것을 특징으로 하는 NAND형 ROM셀 구조.In the NAND type ROM cell structure, a gate oxide film and a gate poly are formed on a silicon substrate, except for a portion of the gate poly upper portion, a gate oxide film insulated from the gate and the silicon substrate is formed, and the gate poly oxide is removed. The floating NAND type ROM cell structure, characterized in that the second polysilicon is formed and used as the same gate as the gate poly.
KR1019910018225A 1991-10-16 1991-10-16 Structure nand type rom cell and fabricating method thereof KR940006683B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910018225A KR940006683B1 (en) 1991-10-16 1991-10-16 Structure nand type rom cell and fabricating method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910018225A KR940006683B1 (en) 1991-10-16 1991-10-16 Structure nand type rom cell and fabricating method thereof

Publications (2)

Publication Number Publication Date
KR930009069A KR930009069A (en) 1993-05-22
KR940006683B1 true KR940006683B1 (en) 1994-07-25

Family

ID=19321338

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018225A KR940006683B1 (en) 1991-10-16 1991-10-16 Structure nand type rom cell and fabricating method thereof

Country Status (1)

Country Link
KR (1) KR940006683B1 (en)

Also Published As

Publication number Publication date
KR930009069A (en) 1993-05-22

Similar Documents

Publication Publication Date Title
US6177311B1 (en) Method for making a floating gate memory with improved interpoly dielectric
KR0164079B1 (en) Semiconductor device
JPH1012847A (en) Manufacture of semiconductor device
KR940006683B1 (en) Structure nand type rom cell and fabricating method thereof
KR970004079A (en) Semiconductor device and manufacturing method
JP2595058B2 (en) Manufacturing method of nonvolatile semiconductor memory device
JP3257940B2 (en) Method for manufacturing semiconductor device
KR960014470B1 (en) Method of manufacturing a eprom
KR0123745B1 (en) Contact formation method of semiconductor device
KR100223795B1 (en) Manufacturing method of semiconductor memory device
KR100215914B1 (en) Memory cell capacitor fabrication method
KR0167668B1 (en) Method for fabricating thin film transistor
KR930008582B1 (en) Method for fabricating mos transistor with the vertical gate
KR100460704B1 (en) Method for fabricating bottom gate-type tft of sram to increase capacitance of node
KR100399965B1 (en) Method for forming storage node contact of semiconductor device
JPH0479336A (en) Production of semiconductor device
KR100261991B1 (en) Manufacturing method for transistor of semiconductor memory cell and its structure
KR100281037B1 (en) Ipyrom cell manufacturing method
KR0172619B1 (en) Self-registered capacitor bottom plate local interconnect scheme for dram
KR950012558B1 (en) Method of manufacturing a mask rom
KR20010058793A (en) Manufacturing method for flat rom
KR0172812B1 (en) Structure of memory device
KR960039406A (en) Manufacturing method of flash Y pyrom cell
KR930007756B1 (en) Manufacturing method of self-alignment contact
KR100198629B1 (en) Structure of thin film transistor and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20060619

Year of fee payment: 13

LAPS Lapse due to unpaid annual fee