KR100281037B1 - Ipyrom cell manufacturing method - Google Patents
Ipyrom cell manufacturing method Download PDFInfo
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- KR100281037B1 KR100281037B1 KR1019930024075A KR930024075A KR100281037B1 KR 100281037 B1 KR100281037 B1 KR 100281037B1 KR 1019930024075 A KR1019930024075 A KR 1019930024075A KR 930024075 A KR930024075 A KR 930024075A KR 100281037 B1 KR100281037 B1 KR 100281037B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 230000006355 external stress Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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Abstract
본 발명은 이이피롬(EEPROM)셀 제조방법에 관한 것으로 제한된 셀 면적내에서 셀의 ONO커패시터 면적을 크게하여 셀의 커패시턴스를 증가시키고, 외부스트래스에 의한 내압을 증대시키기 위해 드레인영역에 접한 매립제2도전형영역(BN+) 상측의 두꺼운산화막에 일정폭과 깊이를 갖는 복수개의 터널옥사이드를 형성하여, 플로우팅게이트와 ONO유전체막을 형성시킴으로서 유전체막의 면적을 크게하여 소자의 특성을 개선할 수 있다.The present invention relates to a method for manufacturing an EEPROM cell, and to increase the capacitance of the cell by increasing the ONO capacitor area of the cell within a limited cell area, and to filling the drain region in order to increase the breakdown voltage due to external stress. By forming a plurality of tunnel oxides having a predetermined width and depth in the thick oxide film on the upper side of the conductive region BN + , forming a floating gate and an ONO dielectric film, the area of the dielectric film can be increased to improve device characteristics.
Description
제1도는 종래의 EEPROM셀 평면도.1 is a plan view of a conventional EEPROM cell.
제2(a)도 내지 제2(g)도는 제1도의 EEPROM셀의 공정단면도.2 (a) to 2 (g) are process cross-sectional views of the EEPROM cell of FIG.
제3도는 본 발명의 EEPROM셀 평면도.3 is a plan view of the EEPROM cell of the present invention.
제4(a)도 내지 제4(g)도는 제3도의 EEPROM셀의 공정단면도.4 (a) to 4 (g) are process cross-sectional views of the EEPROM cell of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1：제1도전형반도체기판 2：필드산화막1: first conductive semiconductor substrate 2: field oxide film
3：게이트산화막 4：터널옥사이드3: gate oxide film 4: tunnel oxide
5：플오우팅게이트 5a：게이트5: Outing gate 5a: Gate
6：유전체막 7：컨트롤게이트6: dielectric film 7: control gate
8：소오스 및 드레인영역 9：층간절연막8 source and drain region 9 interlayer insulating film
10：전극10: electrode
본 발명은 EEPROM(Electrically Erasable PROM)셀에 관한 것으로, 특히 복수개의 터널옥사이드 구조를 사용하여 소자의 실효셀용량증가 및 신뢰성을 향상시키기에 적당하도록 한 이이피롬(EEPROM)셀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable PROM (EEPROM) cell, and more particularly to a method for manufacturing an EEPROM cell, which is suitable for increasing the effective cell capacity and reliability of a device by using a plurality of tunnel oxide structures.
이하, 첨부된 도면을 참조하여 종래의 기술을 설명하면 다음과 같다.Hereinafter, a conventional technology will be described with reference to the accompanying drawings.
제1도는 종래의 EEPROM셀의 평면도를 나타낸 것으로, 제1도전형반도체기판상의 선택영역에 형성된 활성영역의 하부 활성층(20)의 선택영역에 각각 일정면적으로 형성되는 매립제2도전형영역(BN+)과, 게이트산화막중 두꺼운산화막 부분의 선택영역에 일정면적과 일정깊이로 식각되어 형성되는 터널옥사이드(4a)와, 상기 게이트산화막중 두꺼운산화막 사이에 일정면적으로 형성되는 플로우팅게이트(5)와, 타측 얇은부분의 게이트산화막상에 형성되는 게이트(5a)와, 상기 플로우팅게이트(5)상의 유전체막상에 일정면적으로 형성되는 컨트롤게이트(7)와, 활성층(20)중 소오스 및 드레인영역상에 형성되는 전극(10)으로 구성된다.FIG. 1 is a plan view of a conventional EEPROM cell, and includes a buried second conductive region BN formed in a predetermined area in a selected region of the lower active layer 20 of the active region formed in the selected region on the first conductive semiconductor substrate. + ), A tunnel oxide 4a formed by etching a predetermined area and a predetermined depth in a selected region of the thick oxide film portion of the gate oxide film, and a floating gate 5 formed by a predetermined area between the thick oxide film of the gate oxide film A gate 5a formed on the gate oxide film of the other thin portion, a control gate 7 formed on a predetermined area on the dielectric film on the floating gate 5, and a source and drain region of the active layer 20. It consists of the electrode 10 formed on it.
제2(a)도 내지 제2(g)도는 제1도의 A-A' 선상을 자른 EEPROM셀의 공정단면도를 나타낸 것으로서, 제조공정순서는 먼저 제2(a)도와 같이 제1도전형반도체기판(1)상의 선택영역을 열산화하여 일정간격으로 복수개의 필드산화막(2)을 형성하여 활성층을 정의한다.2 (a) to 2 (g) show the process cross-sectional view of the EEPROM cell cut along the AA ′ line of FIG. 1, and the manufacturing process sequence is the first conductive semiconductor substrate 1 as shown in FIG. The active region is defined by thermally oxidizing the selected region on the?
이어 제2(b)도와 같이 활성영역상의 선택영역 두곳에 제2도전형불순물을 도핑한 후, 전표면을 열산화하여 게이트산화막(3)을 형성한다.Subsequently, as shown in FIG. 2 (b), the second conductive impurity is doped into two selected regions on the active region, and then the entire surface is thermally oxidized to form a gate oxide film 3.
이때 불순물도핑영역에 매립제2도전형영역(BN+)이 형성되고 매립제2도전형영역(BN+) 상측은 높은 불순물농도에 의해 다른영역보다는 상대적으로 두꺼운산화막이 형성된다.In this case, the buried second conductive region BN + is formed in the impurity doped region, and a thicker oxide film is formed on the upper side of the buried second conductive region BN + than the other regions due to the high impurity concentration.
그다음 제2(c)도와 같이 게이트산화막(3)중에서 두꺼운 일측 산화막을 선택적으로 일정폭과 깊이로 식각하여, 식각된 부분의 두께가 80Å이 되도록 터널옥사이드(4a)를 형성한다.Next, as shown in FIG. 2 (c), one side of the thick oxide film is selectively etched with a predetermined width and depth in the gate oxide film 3 to form the tunnel oxide 4a such that the etched portion has a thickness of 80 kPa.
이어 제2(d)도와 같이 전표면상에 폴리실리콘을 증착하고, 폴리실리콘상에 산화막-질화막-산화막(ONO)을 차례로 적층하여 유전체막(6)을 형성한 후, 전표면상에 감광막을 도포하고 포토공정을 수행하여, 게이트산화막(3)중 두꺼운산화막에 걸쳐, 터널옥사이드(4a)를 포함한 상측에 일정폭을 갖는 감광막패턴(30)과, 타측 게이트산화막(3)중 얇은부분상측의 선택영역에 일정폭을 갖는 감광막패턴(30)을 형성한다.Subsequently, polysilicon is deposited on the entire surface as shown in FIG. 2 (d), an oxide film-nitride-oxide film (ONO) is sequentially stacked on the polysilicon to form the dielectric film 6, and then a photosensitive film is coated on the entire surface. A photo process is performed to select a photoresist pattern 30 having a predetermined width over the thick oxide film of the gate oxide film 3 and the thin region of the other gate oxide film 3 over the thick oxide film of the gate oxide film 3. A photosensitive film pattern 30 having a predetermined width is formed on the substrate.
이어, 상기 감광막패턴(30)을 마스크로하여 유전체막(6)과 폴리실리콘을 패터닝하여 게이트산화막(3)중 두꺼운산화막에 걸쳐 일정폭을 갖는 컨트롤트랜지스터의 플로우팅게이트(5)를 형성하고, 타측 게이트산화막(3)중 얇은부분상에 선택트랜지스터의 게이트(5a)를 형성한 후, 잔존하는 감광막패턴(30)을 제거한 후, 플로우팅게이트(5)와 게이트(5a)측면에 절연막을 형성한다.Subsequently, the dielectric film 6 and the polysilicon are patterned using the photoresist pattern 30 as a mask to form a floating gate 5 of a control transistor having a predetermined width over the thick oxide film of the gate oxide film 3. After forming the gate 5a of the select transistor on the thin portion of the other gate oxide film 3, the remaining photosensitive film pattern 30 is removed, and then an insulating film is formed on the sides of the floating gate 5 and the gate 5a. do.
그다음 제2(e)도와 같이 전표면상에 폴리실리콘을 형성하고 선택적으로 패터닝하여, 플로우팅게이트(5)상측 유전체막(6)상에 일정폭을 갖는 컨트롤게이트(7)를 형성한다.Then, polysilicon is formed and selectively patterned on the entire surface as shown in FIG. 2 (e) to form a control gate 7 having a predetermined width on the dielectric film 6 above the floating gate 5.
이어 제2(f)도와 같이 전표면상에 제2도전형의 고농도불순물을 주입하여 매립제2도전형영역(BN+)과 접하여 형성되는 소오스 및 드레인영역(8)을 형성한다.Subsequently, a high concentration impurity of the second conductivity type is implanted on the entire surface as shown in FIG. 2 (f) to form the source and drain regions 8 formed in contact with the buried second conductivity type region BN + .
그다음 제2(g)도와 같이 전표면상에 층간절연막(9)을 형성하고, 포토-에칭공정으로 층간절연막(9)을 선택적으로 패터닝하여 소오스 및 드레인영역(8)이 노출되도록 콘택홀을 형성한 후, 전표면상에 금속을 증착하고 선택적으로 패터닝하여 소오스 및 드레인영역(8)상에 전극(10)을 형성한다.Then, as shown in FIG. 2 (g), the interlayer insulating film 9 is formed on the entire surface, and the contact hole is formed to selectively expose the source and drain regions 8 by selectively patterning the interlayer insulating film 9 by a photo-etching process. The metal is then deposited on the entire surface and selectively patterned to form electrodes 10 on the source and drain regions 8.
상기와 같은 종래의 기술은 제한된 칩(Chip) 크기 내에서 셀의 유전체막(6)의 면적을 충분히 증가시킬수 없어 정전용량을 크게 할 수 없고, 또한 외부스트레스에 민감하여 신뢰성측면에서 취약한 문제점이 있었다.The prior art as described above has a problem in that the area of the dielectric film 6 of the cell cannot be sufficiently increased within the limited chip size, so that the capacitance cannot be increased, and also it is sensitive to external stress and thus has a weak point in reliability. .
본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위해 안출한 것으로, 복수개의 터널옥사이드를 형성하여 셀의 정전용량 및 신뢰성을 향상시킨 EEPROM 제조방법을 제공함에 그 목적이 있다.The present invention has been made to solve the problems of the prior art, it is an object of the present invention to provide a method for manufacturing an EEPROM to improve the capacitance and reliability of the cell by forming a plurality of tunnel oxide.
이하, 상기와 같은 목적을 실현하기 위한 본 발명의 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, with reference to the accompanying drawings an embodiment of the present invention for realizing the above object.
제3도는 본 발명의 EEPROM셀의 평면도를 나타낸 것으로서, 제1도전형반도체기판상의 선택영역에 형성된 활성영역의 하부 활성층(20)의 선택영역에 각각 일정면적을 갖는 매립제2도전형영역(BN+)이 형성되고, 활성영역상에 형성되는 게이트산화막중 매립제2도전형영역(BN+)상의 두꺼운 일측 산화막에 일정면적과 깊이로 복수개의 터널옥사이드(4)가 형성되고, 상기 터널옥사이드(4)를 포함하여 게이트산화막중 두꺼운 양측 산화막에 걸쳐 일정면적을 갖는 플로우팅게이트(5)가 형성되고, 나머지 부분은 종래와 동일하다.3 shows a plan view of the EEPROM cell of the present invention, wherein the buried second conductive region BN having a predetermined area in each of the selected regions of the lower active layer 20 of the active region formed in the selected region on the first conductive semiconductor substrate. + ) Is formed, and a plurality of tunnel oxides 4 having a predetermined area and depth are formed in the thick one side oxide layer on the buried second conductive region BN + in the gate oxide layer formed on the active region. Including the 4), a floating gate 5 having a predetermined area is formed over both thick oxide films in the gate oxide film, and the remaining part is the same as in the prior art.
제4(a)도 내지 제4(g)도는 제3도의 A-A' 선상을 자른 EEPROM셀의 공정단면도를 나타낸 것으로서, 제조공정은 제4(a)도와 같이 먼저 제1도전형반도체기판(1)상의 선택영역에 필드산화막(2)을 형성하여 활성영역을 정의하고 제4(b)도와 같이 활성영역의 선택영역에 각각 일정폭과 깊이로 제2도전형불순물을 고농도로 주입한다음, 활성영역을 열산화시켜 게이트산화막(3)을 형성한다.4 (a) to 4 (g) show a process cross-sectional view of the EEPROM cell taken along the line AA ′ of FIG. 3, and the manufacturing process is first performed as shown in FIG. 4 (a). Define the active region by forming the field oxide film 2 in the selected region of the phase, and injecting the second conductive impurity at a predetermined width and depth into the selected region of the active region at high concentration, as shown in FIG. 4 (b). Is thermally oxidized to form the gate oxide film 3.
이때, 제2도전형불순물 주입영역에 매립제2도전형영역(BN+)이 형성되고, 매립제2도전형영역(BN+) 상측에는 고농도의 불순물에 의해 두꺼운산화막이 형성된다.In this case, the buried second conductive region BN + is formed in the second conductive impurity implantation region, and a thick oxide film is formed on the buried second conductive region BN + by high concentration of impurities.
이어, 제4(c)도와 같이 게이트산화막(3)중 일측 두꺼운산화막을 포토-에칭공정으로 일정폭과 깊이로 패터닝하여 4개이상의 복수개로 터널옥사이드(4)를 형성한다.Subsequently, as shown in FIG. 4 (c), one side of the thick oxide film of the gate oxide film 3 is patterned by a predetermined width and depth by a photo-etching process to form four or more tunnel oxides 4.
이어, 제4(d)도와 같이 전표면상에 폴리실리콘을 증착한 후 포토-에칭공정으로 패터닝하여 게이트산화막(3)중 터널옥사이드(4)를 포함하여 두꺼운산화막상에 걸쳐 일정폭을 갖는 플로우팅게이트(5)와 게이트산화막(3)중 일측 얇은 부분에 일정폭을 갖는 선택트랜지스터의 게이트(5a)를 동시에 형성한다음, 전표면상에 산화막-질화막-산화막(ONO)을 차례로 적층하여 유전체막(6)을 형성한다.Subsequently, as shown in FIG. 4 (d), polysilicon is deposited on the entire surface and then patterned by photo-etching to float over a thick oxide film including the tunnel oxide 4 in the gate oxide film 3. A gate 5a of a select transistor having a predetermined width is formed simultaneously on one side of the gate 5 and the gate oxide film 3, and then an oxide film-nitride-oxide film (ONO) is sequentially stacked on the entire surface to form a dielectric film ( 6) form.
이어, 유전체막(6)을 패터닝하여 플로우팅게이트(5)와 게이트(5a) 표면상에만 남도록 나머지부분은 제거한다.Subsequently, the dielectric film 6 is patterned to remove the remaining portions so as to remain only on the surfaces of the floating gate 5 and the gate 5a.
이어 제4(e)도와 같이 전표면상에 폴리실리콘을 증착하고 패터닝하여 플로우팅게이트(5)상측 유전체막(6)상에 컨트롤게이트(7)를 형성한다.Subsequently, polysilicon is deposited and patterned on the entire surface as shown in FIG. 4 (e) to form the control gate 7 on the dielectric film 6 above the floating gate 5.
그다음 제4(f)도와 같이 게이트(5a) 측벽에 측벽절연막을 형성하고, 전표면상에 고농도의 n형 불순물을 주입하여 컨트롤게이트(7)와 게이트(5a)로 마스킹되지 않은 제1도전형반도체기판(1)에 고농도의 매립제2도전형불순물영역(N+)으로서 소오스 및 드레인영역(8)을 형성한다.Next, as shown in FIG. 4 (f), a sidewall insulating film is formed on the sidewall of the gate 5a, and a high concentration of n-type impurities are injected onto the entire surface to mask the first conductive semiconductor that is not masked by the control gate 7 and the gate 5a. The source and drain regions 8 are formed in the substrate 1 as buried second conductive impurity regions N + .
이어, 제4(g)도와 같이 전표면상에 층간절연막(9)을 형성한 후 소오스 및 드레인영역(8)상측을 일정폭으로 제거하여 콘택홀을 형성하고, 전표면상에 금속을 증착한다음 선택적으로 패터닝하여 소오스 및 드레인전극(10)을 형성한다.Subsequently, as shown in FIG. 4 (g), the interlayer insulating film 9 is formed on the entire surface, and then the contact hole is formed by removing the upper portion of the source and drain regions 8 to a predetermined width, and then depositing a metal on the entire surface. Patterning to form the source and drain electrodes 10.
상기와 같은 본 발명은, 복수개의 터널옥사이드를 형성시킴으로서 외부스트래스에 대한 내압이 증대되고, 유전체막의 면적이 증가되어 커패시턴스의 용량이 증가되므로 EEPROM소자의 특성이 개선되는 효과가 있다.The present invention as described above has the effect of improving the characteristics of the EEPROM device by forming a plurality of tunnel oxide to increase the breakdown voltage against the external stress, the area of the dielectric film is increased to increase the capacitance capacity.
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| KR1019930024075A KR100281037B1 (en) | 1993-11-12 | 1993-11-12 | Ipyrom cell manufacturing method |
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