KR100210857B1 - Non-volatile semiconductor memory and its manufacturing method - Google Patents
Non-volatile semiconductor memory and its manufacturing method Download PDFInfo
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- KR100210857B1 KR100210857B1 KR1019960000013A KR19960000013A KR100210857B1 KR 100210857 B1 KR100210857 B1 KR 100210857B1 KR 1019960000013 A KR1019960000013 A KR 1019960000013A KR 19960000013 A KR19960000013 A KR 19960000013A KR 100210857 B1 KR100210857 B1 KR 100210857B1
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 239000004065 semiconductor Substances 0.000 title description 3
- 238000007667 floating Methods 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 230000008878 coupling Effects 0.000 description 7
- 238000010168 coupling process Methods 0.000 description 7
- 238000005859 coupling reaction Methods 0.000 description 7
- 239000010410 layer Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 230000001808 coupling effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
Abstract
본 발명은 비휘발성 메모리소자와 그 제조방법으로서, 필드영역과 활성영역을 가지는 기판과, 상기 필드영역상의 소정깊이의 단차를 갖는 필드절연막과, 상기 필드절연막의 측면에 상기 필드 절연막의 두께보다 더 높이 형성된 사이드윌 스페이서와, 상기 활성영역상의 제1게이트 절연막과, 상기 제1게이트 절연막상 및 상기 사이드윌 스페이서상 및 상기 제1게이트절연막으로부터 연장된 필드절연막의 일부상에 연장되며 상기 필드절연막과는 이격되어 형성된 부유게이트전극과, 상기 부유게이트전극의 표면상에 제2게이트절연막과, 상기 제2게이트절연막상에 제어게이트와, 상기 제어게이트 양측의 상기 기판에 불순물영역을 포함하여 이루어진다.The present invention provides a nonvolatile memory device and a method of manufacturing the same, comprising: a substrate having a field region and an active region, a field insulating film having a step depth of a predetermined depth on the field region, and a thickness of the field insulating film on the side of the field insulating film. A sidewall spacer formed high, a first gate insulating film on the active region, a first gate insulating film, a sidewall spacer, and a portion of a field insulating film extending from the first gate insulating film; And a floating gate electrode spaced apart from each other, a second gate insulating film on the surface of the floating gate electrode, a control gate on the second gate insulating film, and an impurity region in the substrate on both sides of the control gate.
Description
제1도는 종래의 비휘발성 메모리소자의 제조공정을 설명하기 위한 단면도.1 is a cross-sectional view for explaining the manufacturing process of the conventional nonvolatile memory device.
제2도는 비휘발성 메모리소자의 레이아웃도.2 is a layout diagram of a nonvolatile memory device.
제3도는 제2도의 III-III선 단면도.3 is a cross-sectional view taken along the line III-III of FIG.
제4도는 제2도의 IV-IV선 단면도.4 is a cross-sectional view taken along the line IV-IV of FIG.
제5도는 부유게이트의 공정 중 중간형태를 설명하기 위한 평면도.5 is a plan view for explaining the intermediate form of the floating gate process.
본 발명은 비휘발성 메모리소자 및 그 제작방법에 관한 것으로 특히 부유게이트와 제어게이트의 결합비(Coupling Ratio)를 증가시켜 프로그래밍 특성을 개선할 수 있는 방법에 관한 것이다.The present invention relates to a nonvolatile memory device and a method of fabricating the same, and more particularly, to a method of improving programming characteristics by increasing a coupling ratio between a floating gate and a control gate.
종래의 비휘발성 메모리소자는 제1도에 도시된 바와 같이, 필드절연막(21) 사이에 액티브 영역이 설정되고, 제어게이트 전극(25) 라인이 필드절연막과 수직으로 서로 교차하는 방향을 형성된다. 그리고 부유게이트(23)는 액티브 영역과 제어게이트가 교차하는 영역에 액티브영역과 제어게이트아 각각 절연되어 형성된다.In the conventional nonvolatile memory device, as shown in FIG. 1, an active region is set between the field insulating films 21, and the control gate electrode 25 lines are formed to cross the field insulating films perpendicularly to each other. The floating gate 23 is insulated from the active region and the control gate in an area where the active region and the control gate cross each other.
종래의 플래쉬 메모리셀을 형성하는 방법은 기판(20)에 필드절연막(21)을 형성하고, 여기서 게이트산화막(22)을 형성한 후 폴리실리콘을 데포지션하고 패터닝하여 중간 형태인 부유게이트를 형성한다. 이어서 부유게이트의 전 표면에 층간 절연막(24)을 형성하고, 또 층간절연막(24) 위에 폴리실리콘을 데포지션하고 패터닝하여 제어게이트(25)를 형성한다. 이 때 제어게이트를 형성하기 위한 마스크로서 부유게이트까지 식각하여 최종적으로 부유게이트(23)를 자기 정열(Self align) 방식으로 형성한다. 그리고 노출된 기판에 이온 주입하여 제어게이트 양편에 소스와 드레인을 형성한다.In the conventional method of forming a flash memory cell, a field insulating film 21 is formed on a substrate 20, and a gate oxide film 22 is formed thereon, followed by deposition and patterning of polysilicon to form a floating gate having an intermediate shape. . Subsequently, an interlayer insulating film 24 is formed on the entire surface of the floating gate, and polysilicon is deposited and patterned on the interlayer insulating film 24 to form the control gate 25. At this time, the floating gate 23 is etched as a mask for forming the control gate and finally the floating gate 23 is formed in a self align method. Ions are implanted into the exposed substrate to form a source and a drain on both sides of the control gate.
이렇게 형성된 플래쉬 메모리셀은 부유게이트(23)에 전자를 주입하거나 주입하지 않음으로 채널의 쓰레쉬홀드 전압(VT)이 변화되게 하여 프로그래밍한다.The flash memory cell thus formed is programmed by injecting or not injecting electrons into the floating gate 23 so that the threshold voltage V T of the channel is changed.
프로그램하는 방법으로는 제어게이트와 드레인 전극에 소스 전극에 비하여 상대적으로 높은 전압을 가하는데, 이때 제어게이트에 가해진 전압이 커플링 효과에 의하여 부유게이트에 유도되며, 이 유도 전압이 드레인 근처에서 발생된 핫일렉트론을 끌어들인다. 부유게이트에 유도된 전압(=커플링 유도 전압)은 제어게이트와 부유게이트의 오버랩(Overlap) 면적이 크면 클수록, 즉 커플링 비(Coupling Ratio:kc)가 크면 클수로 유도 전압도 크게 나타난다. 커플링 비가 크면 프로그래밍 효율 및 특성이 좋아지게 된다.In the programming method, a relatively high voltage is applied to the control gate and the drain electrode compared to the source electrode, wherein the voltage applied to the control gate is induced to the floating gate by the coupling effect, and the induced voltage is generated near the drain. Attract hot electrons. The induced voltage (= coupling induced voltage) to the floating gate is larger in number as the overlap area between the control gate and the floating gate is large, that is, when the coupling ratio (kc) is large. Large coupling ratios result in better programming efficiency and characteristics.
이 커플링 비 kc는 제어게이트와 부유게이트 사이의 정전 용량(Cpp)과, 부유게이트와 실리콘 기판 사이의 정전 용량(Cox)에 의해 결정된다. 스택 게이트(Stack Gate) 플래쉬 셀의 결합비는 Kc=Cpp(Cpp+Cox)가 되므로, Cox에 비해 Cpp의 값이 클수록 kc는 커지게 된다. Cpp를 증가시키기 위해서는 층간 절연막의 유전율을 크게 하거나 두께를 얇게 할 것, 또는 부유게이트와 제어게이트의 오버랩 되는 면적을 증가시켜야 한다.This coupling ratio kc is determined by the capacitance Cpp between the control gate and the floating gate, and the capacitance Cox between the floating gate and the silicon substrate. Since the coupling ratio of the stack gate flash cell is Kc = Cpp (Cpp + Cox), kc becomes larger as the value of Cpp is greater than that of Cox. In order to increase the Cpp, the dielectric constant of the interlayer insulating film should be increased or the thickness thereof should be increased, or the overlapping area of the floating gate and the control gate should be increased.
그러나 부유게이트와 제어게이트의 오버랩 면적을 증가시키는 종래의 방법에 의하면 셀 면적의 증가를 초래한다. 제어게이트와 부유게이트의 오버랩 면적이 부유게이트와 실리콘 기판 사이의 오버랩 면적보다 상대적으로 크게 하기 위해서는, 제1도에 보인 바와 같이, 부유게이트가 필드절연막 위로 많이 올라와야 하며 이로 인해 필드절연막의 폭이 증가되어야 된다. 결과적으로 셀 크기가 증가된다.However, according to the conventional method of increasing the overlap area of the floating gate and the control gate, the cell area is increased. In order for the overlap area of the control gate and the floating gate to be relatively larger than the overlap area between the floating gate and the silicon substrate, as shown in FIG. 1, the floating gate must be raised above the field insulating film, thereby increasing the width of the field insulating film. Should be. As a result, the cell size is increased.
필드절연막 위로 올라가는 부유게이트의 면적을 늘리지 않고, 프로그램이 용이한 전압을 부유게이트에 가해지도록 하기 위해서는 제어게이트에 인가하는 전압이 증가해야 한다. 부유게이트에 유도되는 전압이 클수록 부유게이트로의 전자 주입이 포화 상태에 도달하는 시간이 짧아져서 프로그래밍 속도가 빨라지게 된다.In order to apply a voltage that is easy to program to the floating gate without increasing the area of the floating gate that rises above the field insulating layer, the voltage applied to the control gate must be increased. The greater the voltage induced on the floating gate, the shorter the time for electron injection into the floating gate to reach saturation, resulting in faster programming.
본 발명의 목적은 부유게이트와 제어게이트의 오버랩 면적을 증가시킴으로서 결합비(coupling Ratio)를 증가시켜 프로그래밍 특성을 개선하려는 것이다.An object of the present invention is to improve the programming characteristics by increasing the coupling ratio by increasing the overlap area of the floating gate and the control gate.
본 발명의 비휘발성 메모리소자를 제조하는 방법은, 기판상에 필드영역과 활성영역을 정의하는 공정과, 상기 필드영역상에 필드절연막과 상기 필드절연막상에 임시막을 형성하는 공정과, 상기 활성영역상에 제1게이트절연막을 형성하는 공정과, 상기 활성영역과 상기 활성영역으로부터 연장된 상기 임시막의 일부 영역상에 부유게이트를 형성하는 공정과, 상기 임시막을 제거하는 공정과, 상기 부유게이트의 표면에 제2게이트절연막을 형성하는 공정과, 상기 제2게이트절연막상에 제어게이트를 형성하는 공정과, 상기 제어게이트 양측의 기판에 불순물영역을 형성하는 공정을 포함한다.A method of manufacturing a nonvolatile memory device of the present invention includes the steps of defining a field region and an active region on a substrate, forming a field insulating film on the field region and a temporary film on the field insulating film, and forming the active region. Forming a first gate insulating film thereon; forming a floating gate on the active region and a portion of the temporary film extending from the active region; removing the temporary film; and surface of the floating gate. Forming a second gate insulating film on the substrate; forming a control gate on the second gate insulating film; and forming an impurity region on the substrate on both sides of the control gate.
부유게이트를 형성하기 전에 필드절연막과 상기 임시막의 측면에 측벽을 형성하는 공정을 추가하면 더욱 좋다.It is further preferable to add a step of forming sidewalls on the side surfaces of the field insulating film and the temporary film before forming the floating gate.
임시막은 등방성 식각 방법에 의하여 제거하는데, 습식각 방법을 이용한다.The temporary film is removed by an isotropic etching method, using a wet etching method.
본 발명의 메모리소자는 필드영역과 활성영역을 가지는 기판과, 상기 필드영역상의 필드절연막과, 상기 활성영역상의 제1게이트 절연막과, 상기 제1게이트 절연막상과 상기 제1게이트 절연막으로부터 연장된 필드절연막의 일부상에 연장되며 상기 필드절여막과는 이격되어 형성된 부유게이트전극과, 상기 부유게이트전극의 표면상에 제2게이트절연막과, 상기 제2게이트절연막상에 제어게이트와, 상기 제어게이트 양측의 기판에 불순물영역을 포함하여 이루어진다.A memory device of the present invention includes a substrate having a field region and an active region, a field insulating film on the field region, a first gate insulating film on the active region, a field extending from the first gate insulating film and the first gate insulating film. A floating gate electrode formed on a portion of the insulating film and spaced apart from the field isolation film, a second gate insulating film on the surface of the floating gate electrode, a control gate on the second gate insulating film, and both sides of the control gate The impurity region is included in the substrate.
필드절연막의 측면에 필드절연막의 두께보다 더 높이 형성된 절연체로 된 측벽을 더 포함한다.The side of the field insulating film further includes a sidewall of an insulator formed higher than the thickness of the field insulating film.
이하에서 제2도 내지 제5도를 참조하면서 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described with reference to FIGS. 2 to 5.
제2도는 본 발명의 레이아웃을 보인 것이고, 제2도의 III-III선 단면도가 제3도의 (a-d)에 공정별로 도시되어 있고, 제2도의 IV-IV선 단면도가 제4도의 a 및 b에 도시되어 있다.FIG. 2 shows the layout of the present invention, the section III-III of FIG. 2 is shown by process in FIG. 3 (ad), and the section IV-IV of FIG. 2 is shown in a and b of FIG. It is.
본 발명은 먼저 제3도 (a)에 도시된 바와 같이, 반도체 기판(10) 위에 필드절연막으로 산화막(11)과, 임시막으로 질화막(12)을 증착한 후, 사진 식각 공정으로 액티브 영역(Active Region)의 상기 산화막과 질화막을 식각하여 액티브 영역을 정의한다. 이 액티브 영역은 롬셀들을 어레이로 배열하기 위하여 대부분 스트라이프 형상으로 길게 형성되며 필드영역과 역시 스트라이프 형상으로 길게 형성되어서 액티브 영역과 필드영역이 서로 교대로 배열된다.According to the present invention, as shown in FIG. 3A, first, an oxide film 11 is formed as a field insulating film on the semiconductor substrate 10, and a nitride film 12 is formed as a temporary film. The oxide layer and the nitride layer of the active region are etched to define an active region. The active area is formed to be long in stripe shape in order to arrange the ROM cells in an array, and the field area is also formed to be long in stripe shape so that the active area and the field area are alternately arranged.
그런 다음 절연막인 산화막을 증착하고 이를 에치백하여 필드 영역에 남아 있는 소정 깊이의 단차를 갖는 산화막(11)과 질하막(12)의 측면에 산화막 스페이서, 즉 측벽(13)를 만든다.Then, an oxide film, which is an insulating film, is deposited and etched back to form oxide spacers, that is, sidewalls 13, on the side surfaces of the oxide film 11 and the subsurface film 12 having a predetermined depth remaining in the field region.
이어서 제3도 (b)에 보인 바와 같이, 채널 위에 게이트산화막(14)을 형성시킨 다음, 부유게이트용 도전물질인 폴리실리콘을 증착하고, 사진 식각 공정으로 패터닝하여 제5도에서 보인 바와 같이 부유게이트(15)를 형성한다. 이 부유게이트는 액티브영역 위에 형성하지만 액티브영역에 인접한 필드 영역 가장자리의 일부 임시막 위를 덮도록 형성한다. 이 부유게이트는 액티브영역과 동일한 방향으로 형성한다.Subsequently, as shown in FIG. 3 (b), the gate oxide layer 14 is formed on the channel, and then polysilicon, which is a conductive material for the floating gate, is deposited, and patterned by a photolithography process to float as shown in FIG. The gate 15 is formed. The floating gate is formed on the active region, but is formed to cover a part of the temporary film on the edge of the field region adjacent to the active region. This floating gate is formed in the same direction as the active region.
다음에는 제3도 (c)에 보인 바와 같이, 질화막(12)을 습식각으로 제거한다. 그러면 부유게이트 밑에 있던 질화막까지 제거됨으로써 필드절연막(11)과 부유게이트(15) 사이에 빈 공간이 만들어진다.Next, as shown in FIG. 3 (c), the nitride film 12 is removed by wet etching. Then, the nitride film under the floating gate is removed, thereby creating an empty space between the field insulating film 11 and the floating gate 15.
이렇게 한 후 제3도 (d)와 같이, 부유게이트를 절연시키기 위한 층간절연막(16)을 부유게이트(15) 표면에 형성시킨 후, 제어게이트용 도전 물질인 폴리실리콘을 증착하고 패터닝하여 제어게이트(17)를 형성한다.After this, as shown in FIG. 3 (d), an interlayer insulating film 16 for insulating the floating gate is formed on the surface of the floating gate 15, and then polysilicon, which is a conductive material for the control gate, is deposited and patterned to control the gate. (17) is formed.
셀어레이를 형성할 경우에 액티브영역이 형성된 방향을 가로 방향이라고 하면 제어게이트는 세로 방향으로 형성한다. 그리고 가로 방향으로 형성되어 있는 중간 형태의 부유게이트를 세로 방향으로 식각하여 제어게이트 하부에 있는 부유게이트만 남기어서 셀 단위 별로 부유게이트(15')를 형성한다.In the case of forming the cell array, if the direction in which the active region is formed is referred to as the horizontal direction, the control gate is formed in the vertical direction. In addition, the floating gate of the intermediate shape formed in the horizontal direction is etched in the vertical direction, leaving only the floating gate under the control gate to form the floating gate 15 'for each cell.
다음에는 종래와 같은 방법으로 부유게이트(15')와 제어게이트(17)의 가로 방향 좌우 측에 노출되어 있는 액티브영역의 기판에 이온을 주입하여 불순물영역을 형성한다. 이 불순물영역은 채널 좌우에 형성되어서 소스와 드레인 역할을 한다.Next, an impurity region is formed by implanting ions into the active region substrate exposed to the left and right sides of the floating gate 15 'and the control gate 17 in the same manner as in the related art. This impurity region is formed on the left and right of the channel to serve as a source and a drain.
이 불순물영역의 형성방법은 여러 가지 방법을 이용할 수가 있지만 제4도의 (a)에 보인 바와 같이, 먼저 부유게이트(15')와 제어게이트(17)이 일측을 포토레지스트 마스크(5)로 덮은 다음 일측에만 저농도로 이온을 주입하여, 주입된 이온을 확산하여 n-불순물영역(19)을 형성하고, 다음에는 제4도의 (b)에서 보인 바와 같이, 포토레지스트 마스크(5)를 제거한 상태에서 부유게이트(15')와 제어게이트(17)의 가로 방향 좌우 측을 노출시킨 후 고농도로 이온을 주입하여 n+ 불순물영역(18,19')을 형성한다. 이렇게 하여 소스 쪽에는 LDD 구조의 불순물영역을 형성한다.There are various methods for forming the impurity region, but as shown in Fig. 4A, the floating gate 15 'and the control gate 17 cover one side with the photoresist mask 5 first. By implanting ions at low concentration on only one side, the implanted ions are diffused to form an n-impurity region 19. Next, as shown in (b) of FIG. 4, floating in the state where the photoresist mask 5 is removed After the left and right sides of the gate 15 'and the control gate 17 are exposed in the horizontal direction, ions are implanted at high concentration to form n + impurity regions 18 and 19'. In this way, an impurity region having an LDD structure is formed on the source side.
이러한 방법을 형성된 비휘발성 메모리소자는 반도체 기판에 필드 영역과 액티브영역이 구분되고, 액티브영역 내에 설정되는 채널영역 양측에 소스 전극 및 드레인 전극이 형성되고, 채널 영역 위에 있는 게이트절연막(14)이 형성되어 있다.In the nonvolatile memory device having the above-described method, a field region and an active region are divided in a semiconductor substrate, source and drain electrodes are formed on both sides of a channel region set in the active region, and a gate insulating film 14 is formed on the channel region. It is.
필드 영역에는 형성된 필드절연막(11)의 측면에 필드절연막의 두께보다 더 높이 절연체로 된 사이드윌 스페이서(Sidewall spacers)(13)가 형성되어 있다.In the field region, sidewall spacers 13 made of an insulator are formed on the side of the formed field insulating film 11 and higher than the thickness of the field insulating film.
게이트절연막(14)과 사이드윌 스페이서(13) 위에 부유게이트(15')가 형성되어 있는데, 이 부유게이트는 필드절연막의 가장자리 일부 영역 위에 임시막이 있던 공간만큼 이격되게 형성된 것이다.A floating gate 15 ′ is formed on the gate insulating layer 14 and the sidewill spacer 13, and the floating gate is formed to be spaced apart from the temporary insulating layer on a part of the edge of the field insulating layer.
부유게이트(15')를 제어게이트(17)와 절연시키기 위한 층간 절연막(16) 위에 제어게이트(17)가 형성되는데, 이 제어게이트는 필드절연막의 가장자리 위에서부터 부유게이트를 감싸는 구조로 되어 있다. 즉 게이트전극 라인의 세로 방향 단면은 제3도의 (d)에서 보인 단면과 같은 형상이 되고, 게이트전극 라인의 세로 방향과 직각되는 방향의 단면은 제4도에서 보인 단면과 같은 형상이 된다. 여기서 사이드윌 스페이서는 실리콘 산화막으로 형성된 것이고, 제어게이트와 부유게이트는 폴리실리콘으로 형성된 것이다.The control gate 17 is formed on the interlayer insulating film 16 for insulating the floating gate 15 'from the control gate 17. The control gate has a structure surrounding the floating gate from the edge of the field insulating film. That is, the longitudinal cross section of the gate electrode line has the same shape as the cross section shown in (d) of FIG. 3, and the cross section of the gate electrode line perpendicular to the longitudinal direction of the gate electrode line has the same shape as the cross section shown in FIG. The sidewill spacer is formed of a silicon oxide film, and the control gate and the floating gate are formed of polysilicon.
이렇게 하여 플래쉬 메모리셀을 제작하면, (1) 셀 크기를 증가시키지 않더라도 부유게이트와 제어게이트의 상호 오버 랩 면적을 늘려서 커플링 효과를 증가시킬 수 있다. 그래서 동일한 셀 크기와 동일한 유전체를 사용하여 제작된 종래의 플래쉬 셀에 비해 프로그래밍 특성이 개선되며, 제어게이트에 인가되는 전압을 낮출 수 있어서 전력 소모도 줄일 수 있다.When the flash memory cell is manufactured in this way, (1) the coupling effect can be increased by increasing the overlap area between the floating gate and the control gate without increasing the cell size. Therefore, the programming characteristics are improved compared to the conventional flash cell fabricated using the same cell size and the same dielectric, and the power applied to the control gate can be lowered, thereby reducing power consumption.
(2) 종래의 기술로 제작된 플래쉬 셀과 동일한 수준의 커플링 효과를 가지는 셀을 제작하려면 종래의 셀보다 더 작게 만들 수 있으므로 집적도를 향상시킬 수 있고, 수율 향상 및 원가 절감에도 유리하게 된다.(2) To manufacture a cell having the same level of coupling effect as a flash cell manufactured by the conventional technology, the cell can be made smaller than the conventional cell, and thus the degree of integration can be improved, and the yield and cost reduction are also advantageous.
Claims (9)
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