KR0155827B1 - Isolation method of nonvolatile semiconductor device - Google Patents

Abstract

A device isolation method of a nonvolatile semiconductor device in which a channel stop impurity region is locally formed below a field insulating film is disclosed. A device isolation method of a nonvolatile semiconductor device of the present invention is a nonvolatile memory including a memory cell array unit and a peripheral circuit having a first conductive channel for driving the same and a second conductive channel opposite to the first conductive channel. A semiconductor device, comprising: sequentially forming an insulating film, a silicon film, and an antioxidant film on a first conductivity type semiconductor substrate; patterning the antioxidant film to form an antioxidant film pattern; and forming the resultant into the antioxidant film pattern. Forming a field oxide film by oxidizing with a mask, removing the antioxidant pattern, the silicon film, and the insulating film, and sequentially forming a tunneling oxide film and a conductive film on the entire surface of the substrate on which the field oxide film is formed; Etching the conductive layer formed on the memory cell array unit and the peripheral circuit unit of the second conductive channel. It includes forming a conductive layer pattern exposing the group field oxide film, comprising the conductive film pattern as a mask, implanting impurities chaenneol stop for a front surface of the substrate. According to the present invention, since the impurity for channel stop is injected into a part of the lower portion of the field oxide film, the side diffusion of the impurity due to the subsequent high temperature process is reduced to increase the junction breakdown voltage.

Description

A device isolation method for a nonvolatile semiconductor device.

1A to 1E are cross-sectional views illustrating a device isolation method of a nonvolatile semiconductor device according to the related art.

2A to 2E are cross-sectional views illustrating a device isolation method of a nonvolatile semiconductor device according to a first embodiment of the present invention.

3 is a cross-sectional view illustrating a device isolation method of a nonvolatile semiconductor device according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

21 semiconductor substrate 22 channel stop impurity region

25 insulating film 26 tunneling oxide film

30 silicon film 31 field oxide film

32: conductive film 35: antioxidant film

37: photoresist pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a nonvolatile semiconductor device, and more particularly, to a device isolation method of a nonvolatile semiconductor device in which a channel stop impurity region is locally formed under a field insulating film.

Recently, the size of unit elements formed in the memory cell array portion and the peripheral circuit portion is becoming smaller. Accordingly, in order to achieve high integration, the isolation region separating the device and the device must be smaller and smaller, and the isolation effect between the devices must be maintained. However, the scale down of the device is limited because the threshold voltage of the transistor is changed by a short channel effect or a narrow width effect caused by the shrinking of the device. It is becoming. In particular, since the driving of the memory cell array portion in the nonvolatile semiconductor is performed at a high voltage (about 20 V) of Vcc or more, it is necessary to form the device isolation region so that the isolation effect between the devices is maintained.

Here, the device isolation method of the conventional semiconductor device will be described. A field oxide film is grown on a semiconductor substrate by a conventional method to form an active region and an inactive region (or field region) so as to be separated, and a channel stop impurity region is formed below the field oxide layer region to increase the isolation effect between devices. The channel stop impurity region is formed by selectively implanting impurities into the semiconductor substrate before forming the field oxide layer.

In the method of forming a channel stop impurity region prior to the formation of the field oxide film, a large amount of impurities are outdiffused during the formation of a field oxide film, which is a subsequent high temperature process, to reduce the concentration of impurities, thereby reducing the channel stop effect or in the substrate. The lateral diffusion at causes the channel stop impurities to contact the channel region resulting in a narrow width effect that reduces the width of the channel region or in contact with the source / drain regions formed by subsequent processes. Causes a junction breakdown voltage drop. Here, a method of forming a field oxide film of a conventional nonvolatile semiconductor device will be described.

1 (a) to 1 (e) are cross-sectional views illustrating a device isolation method of a nonvolatile semiconductor device according to the prior art.

FIG. 1A shows the steps of forming the insulating film 5, the silicon film 10 and the antioxidant film 15 on a semiconductor substrate. Specifically, the insulating film 5 and the silicon film 10 are sequentially stacked on the first conductive semiconductor substrate 1. Subsequently, a silicon nitride film is formed on the silicon film 10 as an anti-oxidation film, for example, and then a peripheral device of the memory cell region C and the first conductivity type channel (P channel A) using a conventional photolithography process. The silicon nitride layer is etched to pattern the oxide layer 15 so that the portion where the field region of the region around the region and the second conductivity type channel (N channel: B portion) is to be formed is exposed.

The insulating film 5 is formed using a silicon thermal oxide film with a thickness of 200 to 300 Å. The silicon film 10 is formed using one of polycrystalline silicon and amorphous silicon in a thickness of 800 to 1200 Å. The antioxidant film 15 is formed to a thickness of 1300 ~ 1700Å.

FIG. 1B shows a step of forming the field oxide film 11. First, after photoresist is applied to the entire surface of the substrate, the cell array portion (C portion of FIG. 1 (a)) and the N channel region (part B of FIG. 1 (a)) of the peripheral circuit portion are formed by a normal photographing process. A photoresist pattern (not shown) to be exposed is formed. Next, an impurity is implanted into the entire surface of the substrate using the photoresist pattern as an ion implantation mask to form the channel stop impurity region 2. Next, the field oxide film 11 is formed using an oxidation process using the antioxidant film 15 as a mask.

FIG. 1C illustrates a step of sequentially stacking the tunnel oxide film 6 and the conductive film 12. After removing the photoresist pattern and the insulating film 5, the tunnel oxide film 6 and the conductive film 12 are sequentially stacked. The tunnel oxide film 6 is usually formed to a thickness of 80 to 110 kPa by an oxidation process, and the conductive film 12 is formed of polycrystalline silicon containing a high concentration of impurities to a thickness of 1400 to 1600 kPa using a conventional CVD method.

FIG. 1D illustrates a step of forming the second photoresist pattern 17. Specifically, after the photoresist is applied on the conductive film 12, a second photoresist pattern 17 for patterning the conductive film 12 for the floating gate is formed by using a photolithography process. The photoresist pattern 17 is formed in the memory cell array in which the floating gate is formed and exposes the remaining region.

FIG. 1E shows a step of patterning the conductive film 12 for the floating gate. The photoresist pattern 17 is used as an etching mask to pattern the conductive layer 12 in the memory cell using a dry etching process to form a conductive layer pattern 12a, and the conductive layer 12 in the remaining region Remove Next, after removing the second photoresist pattern 17, peripheral devices and memory cells are formed to complete the nonvolatile semiconductor memory device.

The method of forming a device isolation region according to the prior art as described above has a problem in that the process cost increases because an additional photographic process for implanting impurities for the P channel stop is required as shown in FIG. .

In addition, a channel stop impurity region formed under the field oxide layer is laterally diffused in a subsequent high temperature process and overlaps with a source / drain region formed in a subsequent process, thereby preventing improvement in junction breakdown pressure.

Accordingly, it is an object of the present invention to limit the channel stop impurity region to a portion below the field oxide film, thereby increasing the separation distance from the source / drain region formed in a subsequent process, thereby improving the device isolation effect. To provide a way.

In order to achieve the above object, the present invention provides a nonvolatile semiconductor device comprising a memory cell array unit, a peripheral circuit portion having a first conductive channel for driving the same, and a second conductive channel opposite to the first conductive channel. The method of claim 1, further comprising: sequentially forming an insulating film, a silicon film, and an anti-oxidation film on the first conductive semiconductor substrate, patterning the anti-oxidation film to form an anti-oxidation film pattern, and forming the resultant into the anti-oxidation film pattern. Oxidizing as a mask to form a field oxide film, removing the antioxidant pattern, silicon film, and insulating film, and sequentially forming a tunneling oxide film and a conductive film on the entire surface of the substrate on which the field oxide film is formed; It is formed on the conductive film, and has an opening in the peripheral circuit portion of the memory cell array portion and the second conductivity type channel. Forming a photoresist pattern; and forming a conductive layer pattern exposing the field oxide layer by etching the conductive layer formed on the memory cell array unit and the peripheral circuit portion of the second conductive channel using the photoresist pattern as a mask. And injecting an impurity for channel stop into the entire surface of the substrate using the photoresist pattern and the conductive layer pattern as a mask.

The insulating film is formed of a silicon thermal oxide film, and the silicon film is formed of any one of polycrystalline silicon and amorphous silicon film. In addition, the anti-oxidation film is formed of a silicon nitride film, the conductive film is formed of a polycrystalline silicon film containing a high concentration of impurities, the tunneling oxide film is formed of a silicon thermal oxide film, and the channel stop impurities are formed of a first conductivity type. Use impurities.

The present invention provides a method for removing the photoresist pattern after the step of injecting impurities for the channel stop, and forming a second photoresist pattern having an opening on the conductive layer pattern formed in the peripheral circuit portion of the first conductivity type channel. And etching the conductive layer pattern using the second photoresist pattern as an etch mask, and implanting channel stop impurities using the second photoresist pattern and the etched conductive layer pattern as a mask. Can be.

The channel stop impurities use impurities of the second conductivity type.

According to another aspect of the present invention, there is provided a method of forming a second conductive impurity well region and a first conductive first impurity well region on a substrate on which the memory cell array unit is formed before forming the insulating layer. Forming a second impurity well region of a second conductivity type in the substrate on which the peripheral element portion having the second conductive type is formed, and a second impurity well region of the first conductivity type on the substrate on which the peripheral circuit portion having the second conductivity type channel is to be formed It may further comprise the step of forming.

According to the present invention, since the impurity for channel stop is injected into a portion of the lower portion of the field oxide film, the lateral diffusion of the impurity due to the subsequent high temperature process is reduced, thereby increasing the junction breakdown voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a device isolation method of a nonvolatile semiconductor device according to a first embodiment of the present invention.

FIG. 2A shows the steps of forming the insulating film 25, the silicon film 30, and the antioxidant film 35. Specifically, the insulating film 25 and the silicon film 30 are sequentially stacked on the first conductive semiconductor substrate 21. Subsequently, a silicon nitride film is formed on the silicon film 30 to prevent oxidation, and then a peripheral circuit part (D part) of the memory cell array part (F part) and the first conductivity type channel (P channel) using a photolithography process. ) And the silicon nitride film is etched to expose the portion where the field region of the peripheral circuit portion (part E) of the second conductivity type channel (N channel) is formed.

In this embodiment, the insulating film 25 is formed using a silicon thermal oxide film with a thickness of 200 to 300 Å. The silicon film 30 is formed using either polycrystalline silicon or amorphous silicon with a thickness of 800 to 1200 Å. The antioxidant film 35 is formed to a thickness of 1300 ~ 1700Å.

FIG. 2B shows a step of forming a field oxide film. Specifically, the field oxide film 31 is formed using an oxidation process using the antioxidant film 35 as a mask.

FIG. 2C illustrates a step of sequentially forming the tunneling oxide layer 26 and the conductive layer 32. First, after the field oxide film is formed, the antioxidant film 35, the silicon film 30, and the insulating film 25 are sequentially removed using an etching process. Subsequently, a tunnel oxide film 26 having a thickness of 80 to 110 kPa and a conductive film 32 having a thickness of 1400 to 1600 kPa are sequentially stacked using an oxidation process. The tunnel oxide film 26 uses a silicon thermal oxide film, and the conductive film 32 forms a polycrystalline silicon film containing a high concentration of impurities by a CVD method.

FIG. 2D illustrates a step of forming a first photoresist pattern 17 having an opening in an N channel region (a memory cell array portion and a peripheral circuit portion of a second conductivity type channel) on the conductive layer 32. . Specifically, after applying the photoresist on the conductive film 32, the N-channel region (memory cell array portion (F portion of Fig. 2 (a)) and the periphery of the second conductivity type channel using a photographic process) The first photoresist pattern 37 is formed by patterning the field region of the circuit portion (part E of FIG. 2A) to be exposed. At this time, the P channel region (part D of FIG. 2A) is in a form in which the photoresist is entirely coated.

FIG. 2E illustrates a step of ion implanting impurities for channel stop after etching the conductive layer 32. Specifically, dry etching the conductive layer 31 using the first photoresist pattern 37 as a mask to dry the N channel region (memory cell array portion (F portion of FIG. 2A) and the second conductive type). A floating gate conductive film pattern 32a exposing the field oxide film of the peripheral circuit portion of the channel (part E in FIG. 2A) is formed. Subsequently, an impurity is ion implanted using the first photoresist pattern 37 and the conductive layer pattern 32a as an ion implantation mask to form a channel stop impurity region 22. At this time, in the present invention, unlike the prior art, a floating gate conductive film pattern 32a is formed in the peripheral circuit portion of the second conductive channel. The channel stop impurity uses an impurity of a first conductivity type and is ion implanted at an energy of 100 keV to 300 keV to form a channel stop impurity region 22 in a portion below the field oxide layer. Next, the conductive film pattern 32a formed in the remaining regions except for the memory cell region is removed in a subsequent process.

Subsequently, after removing the first photoresist pattern 37, peripheral devices and memory cells are formed to complete the nonvolatile semiconductor memory device.

3 is a cross-sectional view illustrating a device isolation method of a nonvolatile semiconductor device according to a second embodiment of the present invention.

The second embodiment of the present invention is performed in the same manner as the steps of FIGS. 2A to 2E of the first embodiment.

Next, the first photoresist pattern 37 is removed, and then the photoresist is applied to the entire surface of the substrate, and then the P channel region [a peripheral circuit portion of the first conductivity type channel (see FIG. And the second region of the photoresist pattern 38 to form the second region of the photoresist pattern 38. At this time, the N channel region (memory cell array portion (F portion of FIG. 2 (a)) and the peripheral circuit portion of the second conductivity type channel (E portion of FIG. 2 (a)) is coated with the photoresist. Form.

Subsequently, the conductive layer pattern 32a is etched using the second photoresist pattern 38 as a mask to form an etched conductive layer pattern 32b exposing the field oxide layer 31. Next, an impurity is ion implanted using the etched conductive film pattern 32b and the second photoresist pattern 38 as a mask to form a channel stop impurity region 22a. At this time, the impurity for channel stop uses impurities of the second conductivity type.

Subsequently, after removing the second photoresist pattern 38, peripheral devices and memory cells are formed to complete the nonvolatile semiconductor memory device.

The effects of the device isolation method of the nonvolatile semiconductor device according to the present invention described above are as follows.

First, the additional photo process for channel stop impurity injection can be reduced, which simplifies the process and reduces production costs. Second, since the channel stop impurity is implanted into only a portion of the field oxide layer, the side diffusion of the impurity may be reduced by a subsequent high temperature process, thereby increasing the junction breakdown voltage. Third, the channel stop impurity can be injected only into a portion of the peripheral circuit portion below the field oxide film, thereby improving device characteristics.

As mentioned above, although this invention was demonstrated concretely, this invention is not limited to this, A deformation | transformation and improvement are possible in the range of the common knowledge of a person skilled in the art.

Claims (9)

A nonvolatile semiconductor device comprising a memory cell array portion and a peripheral circuit portion having a first conductivity type channel for driving the same and a second conductivity type channel opposite to the first conductivity type channel, the semiconductor substrate of the first conductivity type Sequentially forming an insulating film, a silicon film, and an antioxidant film on the substrate; Patterning the antioxidant film to form an antioxidant film pattern; Oxidizing the resultant using the anti-oxidation pattern as a mask to form a field oxide film; Removing the antioxidant pattern, the silicon film, and the insulating film; Sequentially forming a tunneling oxide film and a conductive film on an entire surface of the substrate on which the field oxide film is formed; Forming a photoresist pattern formed on the conductive film and having openings in peripheral circuits of the memory cell array unit and the second conductive channel; Forming a conductive layer pattern exposing the field oxide layer by etching the conductive layer formed in the peripheral portion of the memory cell array unit and the second conductive channel using the photoresist pattern as a mask; And implanting a channel stop impurity into the entire surface of the substrate using the photoresist pattern and the conductive layer pattern as masks. 2. The method of claim 1, wherein the insulating film and the anti-oxidation film are silicon thermal oxide films and silicon nitride films, respectively. The method of claim 1, wherein the silicon film is any one of a polycrystalline silicon and an amorphous silicon film. The method of claim 1, wherein the conductive film is a polycrystalline silicon film containing a high concentration of impurities. The method of claim 1, wherein the tunneling oxide film is a silicon thermal oxide film. The method of claim 1, wherein the channel stop impurities are impurities of a first conductivity type. 2. The method of claim 1, further comprising removing the photoresist pattern after implanting the channel stop impurity, and forming a second photoresist pattern on the conductive layer pattern formed in the peripheral circuit portion of the first conductivity type channel. Forming an oxide layer, etching the conductive layer pattern using the second photoresist pattern as an etch mask, and implanting a channel stop impurity using the second photoresist pattern and the etched conductive layer pattern as a mask A device isolation method for a nonvolatile semiconductor device, characterized by further comprising. 8. The method of claim 7, wherein the channel stop impurity is a second conductivity type impurity. The method of claim 1, further comprising: forming a second conductivity type impurity well region and a first conductivity type first impurity well region on the substrate on which the memory cell array unit is formed before forming the insulating layer; Forming a second impurity well region of a second conductivity type on a substrate on which the peripheral element portion having the conductive channel is to be formed, and a second conductivity type on the substrate on which the peripheral circuit portion having the second conductivity type channel is to be formed The method of claim 1, further comprising forming an impurity well region.