KR0182869B1 - Non-volatile memory cell and manufacturing method thereof - Google Patents
Non-volatile memory cell and manufacturing method thereof Download PDFInfo
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- KR0182869B1 KR0182869B1 KR1019950029991A KR19950029991A KR0182869B1 KR 0182869 B1 KR0182869 B1 KR 0182869B1 KR 1019950029991 A KR1019950029991 A KR 1019950029991A KR 19950029991 A KR19950029991 A KR 19950029991A KR 0182869 B1 KR0182869 B1 KR 0182869B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 17
- 150000004767 nitrides Chemical class 0.000 claims description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
Abstract
본 발명은 비휘발성 메모리 셀 및 그 제조 방법에 관한 것으로, 프로그램의 효율을 향상시키기 위하여 실리콘기판에 형성된 리세스(Recess) 구조의 중앙부에 드레인영역을 형성하고, 상기 리세스 구조의 양측부에 경사진 채널(Channel)이 형성되도록 하므로써 소자의 특성 및 동작 속도가 향상될 수 있도록 한 비휘발성 메모리 셀 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell and a method of manufacturing the same. In order to improve program efficiency, a drain region is formed in a central portion of a recess structure formed on a silicon substrate, and a drain region is formed on both sides of the recess structure. The present invention relates to a nonvolatile memory cell and a method of manufacturing the same, by which a photo channel is formed so that the characteristics and operation speed of the device can be improved.
Description
제1도는 종래 비휘발성 메모리 셀의 프로그램 동작을 설명하기 위한 동작 상태도.1 is an operation state diagram for explaining a program operation of a conventional nonvolatile memory cell.
제2a 내지 제2g도는 본 발명에 따른 비휘발성 메모리 셀의 제조 방법을 설명하기 위한 소자의 단면도.2A to 2G are cross-sectional views of elements for explaining the method for manufacturing a nonvolatile memory cell according to the present invention.
제3도는 본 발명에 따른 비휘발성 메모리 셀의 프로그램 동작을 설명하기 위한 동작 상태도.3 is an operational state diagram for explaining a program operation of a nonvolatile memory cell according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 및 11 : 실리콘기판 2 및 19 : 소오스영역1 and 11: silicon substrate 2 and 19: source region
3 및 20 : 드레인영역 4 및 15 : 터널산화막3 and 20: drain region 4 and 15: tunnel oxide film
5 및 16 A : 플로팅게이트 6 및 17 : 유전체막5 and 16 A: floating gate 6 and 17: dielectric film
7 및 18A : 콘트롤게이트 10 및 10A : 전자7 and 18A: Control Gates 10 and 10A: Electronic
12 : 패드 산화막 13 : 질화막12 pad oxide film 13 nitride film
14 : 필드산화막 16 : 제1폴리실리콘층14: field oxide film 16: the first polysilicon layer
18 : 제2폴리실리콘층 19 : 소오스 영역18: second polysilicon layer 19: source region
20 : 드레인 영역 21 : 포켓 영역20: drain area 21: pocket area
본 발명은 비휘발성 메모리 셀 및 그 제조 방법에 관한 것으로, 특히 실리콘기판에 형성된 리세스(Recess) 구조의 중앙부에 드레인영역을 형성하고, 상기 리세스 구조의 양측부에 경사진 채널(Channel)이 형성되도록 하므로써 프로그램의 효율을 향상시킬 수 있도록 한 비휘발성 메모리 셀 및 그 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory cell and a method of manufacturing the same. In particular, a drain region is formed in a central portion of a recess structure formed on a silicon substrate, and a channel inclined at both sides of the recess structure is formed. The present invention relates to a nonvolatile memory cell and a method for manufacturing the same, which can be formed to improve the efficiency of a program.
일반적으로 전기적인 프로그램 및 소거 기능을 함께 가지는 이피롬(Erasable Programmable Read Only Memory; EPROM), 플래쉬(Flash) 이이피롬(Electrically Erasable Programmable Read Only Memory; EEPROM) 등과 같은 비휘발성 메모리 소자의 메모리 셀(Cell)은 크게 적층-게이트(Stack-gate) 구조와 스프리트-게이트(Split-gate) 구조로 나누어 진다.Generally, a memory cell of a nonvolatile memory device such as erasable programmable read only memory (EPROM) and flash electrically erasable programmable read only memory (EPROM). ) Is largely divided into a stack-gate structure and a split-gate structure.
또한, 이와 같은 구조를 갖는 비휘발성 메모리 소자는 프로그램 및 소거 동작을 하게 되는데, 프로그램 동작은 플로팅 게이트(Floating gate)로 한 케리어(Hot carri er)가 주입(injection)되는 것에 의해 이루어지며, 소거 동작은 터널링(Tunnelling) 현상에 의해 주입된 핫 케리어가 소실되는 것에 의해 이루어진다. 그러므로 핫 케리어의 발생 정도는 프로그램의 효율을 결정하는 중요한 요소가 된다. 그러면 종래 적층-게이트 구조를 갖는 비휘발성 메모리 셀을 제1도를 통해 설명하기로 한다.In addition, a nonvolatile memory device having such a structure performs a program and erase operation. The program operation is performed by injection of a hot carrier into a floating gate, and erase operation. This is achieved by the loss of the hot carrier injected by the tunneling phenomenon. Therefore, the generation of hot carriers is an important factor in determining program efficiency. Next, a nonvolatile memory cell having a conventional stacked-gate structure will be described with reference to FIG. 1.
종래의 적층-게이트 구조를 갖는 비휘발성 메모리 셀은 제1도에 도시된 바와 같이 소오스 및 드레인영역(2 및 3)이 형성된 실리콘기판(1)의 채널 지역 상부에 터널산화막(4), 플로팅게이트(5), 유전체막(6) 및 콘트롤게이트(7)가 순차적으로 적층되어 형성되는데, 이러한 비휘발성 메모리 셀의 프로그램 동작을 설명하면 다음과 같다.A conventional non-volatile memory cell having a stacked-gate structure has a tunnel oxide film 4 and a floating gate over a channel region of a silicon substrate 1 having source and drain regions 2 and 3 formed thereon as shown in FIG. (5) The dielectric film 6 and the control gate 7 are sequentially stacked to form a program operation of the nonvolatile memory cell as follows.
프로그램 바이어스(Bias) 즉, 예를들어 상기 콘트롤게이트(7)에 12V, 드레인영역(3)에 5V 그리고 소오스영역(2)에 접지전위(0V)가 각각 인가되면 상기 실리콘기판(1)에는 수평 방향으로 전기장(Electric field)이 형성된다. 이때 상기 바이어스에 의해 드레인영역(3)의 가장자리(Edge)에는 채널 핀치-오프 영역(Channel pinch-off regi on)이 형성되는데, 이로 인해 전기장의 세기는 드레인영역(3) 주위에서 최대가 된다. 이러한 조건에서 상기 소오스영역(2)으로부터 전자(Electron)들이 실리콘기판(1)의 표면 부위에 형성된 채널을 따라 움직이다가 드레인영역(3) 주위의 고 전기장을 통과하면서 가속되어 상당한 에너지를 얻게 되는데, 이를 핫 케리어라 한다. 이러한 가속된 전자(핫 케리어)들은 상기 드레인영역(3)내의 실리콘(Si) 결정 구조와 충돌하여 그 운동 바향을 바꾸게 되고, 그 결과 플로팅게이트(5) 방향으로 경로를 바꾼 일부의 전자(10)들이 상기 콘트롤게이트(7)로부터 플로팅게이트(5)로의 캐패시터 커플링(Capacitor coupling)에 의해 유기된 수직 방향의 전기장의 도움으로 실리콘-산화막의 에너지 장벽을 뛰어넘어 상기 플로팅게이트(5)로 주입된다. 이와 같은 핫 케리어의 주입에 의해 소정의 데이타(Data)가 프로그램된다. 그런데 상기와 같은 충돌 이온화 현상(Impact ionization effect)에 의해 실리콘(Si) 원자와 충돌한 가속된 전자들은 충돌 지점으로부터 모든 방향으로 되튈 확률을 갖고 있으나, 플로팅게이트 방향(즉, 수직 방향)으로 되튄 전자들만이 플로팅 게이트에 주입되기 때문에 프로그램의 효율이 저하된다.For example, if a program bias (i.e., 12V is applied to the control gate 7, 5V to the drain region 3, and a ground potential (0V) to the source region 2) is applied to the silicon substrate 1, Electric field is formed in the direction. At this time, a channel pinch-off region is formed at the edge of the drain region 3 by the bias, so that the electric field strength is maximized around the drain region 3. Under these conditions, electrons move from the source region 2 along a channel formed in the surface portion of the silicon substrate 1 and are accelerated through a high electric field around the drain region 3 to obtain considerable energy. This is called a hot carrier. These accelerated electrons (hot carriers) collide with the silicon (Si) crystal structure in the drain region 3 to change its direction of movement, and as a result, some of the electrons 10 that have changed their paths in the direction of the floating gate 5 are provided. Are injected into the floating gate 5 over the energy barrier of the silicon-oxide film with the aid of the vertical electric field induced by the capacitor coupling from the control gate 7 to the floating gate 5. . By the injection of such a hot carrier, predetermined data Data is programmed. However, the accelerated electrons collided with the silicon (Si) atoms by the impact ionization effect have the probability of returning in all directions from the point of impact, but the electrons bounce back in the floating gate direction (ie, vertical direction). Since only these are injected into the floating gate, the efficiency of the program is lowered.
따라서 본 발명은 실리콘기판에 형성된 리세스 구조의 중앙부에 드레인영역을 형성하고, 상기 리세스 구조의 양측부에 경사진 채널이 형성되도록 하므로써 상기한 단점을 해소할 수 있는 비휘발성 메모리 셀 및 그 제조방법을 제공하는 데 그 목적이 있다.Accordingly, the present invention provides a non-volatile memory cell that can solve the above-mentioned disadvantages by forming a drain region in the center of the recess structure formed in the silicon substrate, and inclined channels are formed at both sides of the recess structure. The purpose is to provide a method.
상술한 목적을 달성하기 위한 본 발명에 따른 비휘발성 메모리 셀은 소오스 및 드레인 영역이 형성된 실리콘 기판과, 상기 소오스 및 드레인 영역 사이의 상기 실리콘 기판 상에 형성된 게이트 전극으로 이루어진 비휘발성 메모리 셀에 있어서, 상기 드레인 영역은 상기 소오스 영역보다 낮게 형성되어 상기 소오스 및 드레인 영역 사이의 실리콘 기판 표면이 경사면으로 이루어지고, 상기 소오스 영역측의 채널 영역에는 포켓 영역이 형성된 것을 특징으로 한다.A nonvolatile memory cell according to the present invention for achieving the above object is a nonvolatile memory cell comprising a silicon substrate having a source and a drain region formed, and a gate electrode formed on the silicon substrate between the source and drain region, The drain region is formed lower than the source region so that the surface of the silicon substrate between the source and drain regions is formed as an inclined surface, and the pocket region is formed in the channel region on the source region side.
또한, 상술한 목적을 달성하기 위한 본 발명에 따른 비휘발성 메모리 셀 제조 방법은 실리콘기판상에 패드 산화막 및 질화막을 순차적으로 형성한 후 드레인 지역 및 상기 드레인 지역 양측부에 형성될 채널 지역의 일부를 포함하는 부분의 상기 패드 산화막이 노출되도록 상기 질화막을 패터닝하는 단계와, 상기 패터닝된 질화막을 산화 방지층으로 이용한 산화 공정으로 상기 드레인 지역 및 상기 드레인 지역 양측부에 형성될 채널 지역의 일부를 포함하는 부분의 상기 실리콘기판에 필드산화막을 형성하는 단계와, 상기 질화막을 제거한 후 전체 상부면에 채널 이온을 주입하는 단계와, 상기 필드산화막 및 패드 산화막을 제거하는 단계와, 전체 구조 상부에 터널 산화막, 제1폴리실리콘층, 유전체막 및 제2폴리실리콘층을 순차적으로 형성하는 단계와, 게이트 전극용 마스크를 이용한 식각 공정으로 상기 제2폴리실리콘층, 유전체막, 제1폴리실리콘층 및 터널 산화막을 순차적으로 패터닝하여 상기 실리콘기판의 채널 지역 상부에 게이트전극을 형성하는 단계와, 노출된 실리콘기판에 불순물 이온을 주입하여 소오스 및 드레인영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In addition, the nonvolatile memory cell manufacturing method according to the present invention for achieving the above object is formed by sequentially forming a pad oxide film and a nitride film on a silicon substrate and then a portion of the drain region and the channel region to be formed on both sides of the drain region. Patterning the nitride film so that the pad oxide film is exposed, and a portion including a portion of a channel region to be formed at both sides of the drain region and the drain region by an oxidation process using the patterned nitride layer as an oxidation prevention layer. Forming a field oxide film on the silicon substrate, implanting channel ions into the entire upper surface after removing the nitride film, removing the field oxide film and the pad oxide film, and forming a tunnel oxide film over the entire structure. Sequentially forming the one polysilicon layer, the dielectric film, and the second polysilicon layer; And sequentially patterning the second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer by an etching process using a mask for a gate electrode to form a gate electrode on the channel region of the silicon substrate; And implanting impurity ions into the silicon substrate to form a source and a drain region.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2a 내지 제2g도는 본 발명에 따른 비휘발성 메모리 셀의 제조방법을 설명하기 위한 소자의 단면도이고, 제3도는 본 발명에 따른 비휘발성 메모리 셀의 프로그램 동작을 설명하기 위한 동작 상태도이다.2A through 2G are cross-sectional views of devices for describing a method of manufacturing a nonvolatile memory cell according to the present invention, and FIG. 3 is an operation state diagram for explaining a program operation of the nonvolatile memory cell according to the present invention.
제2a도는 실리콘기판(11)상에 패드 산화막(12) 및 질화막(13)을 순차적으로 형성한 후 드레인 지역(D) 및 상기 드레인 지역(D) 양측부에 형성될 채널 지역(C)의 일부(C')를 포함하는 부분(A)의 상기 패드 산화막(12)이 노출되도록 상기 질화막(13)을 패터닝한 상태의 단면도이다.2A illustrates a part of a channel region C to be formed at both sides of the drain region D and the drain region D after sequentially forming the pad oxide film 12 and the nitride film 13 on the silicon substrate 11. It is sectional drawing in the state which patterned the said nitride film 13 so that the said pad oxide film 12 of the part A containing (C ') may be exposed.
제2b도는 상기 패터닝된 질화막(13)을 산화 방지층으로 이용한 산화 공정으로 상기 드레인 지역(D) 및 상기 드레인 지역(D) 양측부에 형성될 채널 지역(C)의 일부(C')를 포함하는 부분(A)의 상기 실리콘기판(11)에 필드산화막(14)을 형성한 상태의 단면도이다.FIG. 2B illustrates the drain region D and a part C ′ of the channel region C to be formed at both sides of the drain region D by an oxidation process using the patterned nitride layer 13 as an oxidation preventing layer. It is sectional drawing of the state in which the field oxide film 14 was formed in the said silicon substrate 11 of the part A. FIG.
제2c도는 상기 질화막(13)을 제거한 후 전체 상부면에 붕소(B)와 같은 채널 이온을 주입하는 상태의 단면도인데, 이때 상기 필드산화막(14)의 두께를 이용한 선택적 이온 주입으로 상기 필드산화막(14) 하부의 실리콘기판(11)에는 채널 이온이 주입되지 않도록 한다.FIG. 2C is a cross-sectional view of a state in which channel ions such as boron (B) are implanted in the entire upper surface after the nitride film 13 is removed. In this case, the field oxide film ( 14) Do not implant channel ions into the lower silicon substrate 11.
제2d도는 상기 패드 산화막(12) 및 필드산화막(14)을 제거하므로써 상기 실리콘기판(11)의 상기 드레인 지역(D) 및 상기 드레인 지역(D) 양측부에 형성될 채널 지역(C)의 일부(C')를 포함하는 부분(A)이 리세스(Recess) 구조로 형성된 상태의 단면도이다.FIG. 2D illustrates a part of the channel region C to be formed at both sides of the drain region D and the drain region D of the silicon substrate 11 by removing the pad oxide layer 12 and the field oxide layer 14. A part A containing (C ') is sectional drawing of the state formed in the recess structure.
제2e도는 전체 상부면에 터널 산화막(15), 제1폴리실리콘층(16), 유전체막(17) 및 제2폴리실리콘층(18)을 순차적으로 형성한 상태의 단면도로서, 상기 유전체막(17)은 하부 산화막, 질화막 및 상부 산화막이 순차적으로 형성된 ONO 구조로 형성한다.FIG. 2E is a cross-sectional view of the tunnel oxide film 15, the first polysilicon layer 16, the dielectric film 17 and the second polysilicon layer 18 sequentially formed on the entire upper surface thereof. 17) has an ONO structure in which a lower oxide film, a nitride film and an upper oxide film are sequentially formed.
제2f도는 게이트 전극용 마스크를 이용한 자기 정렬 식각(Self Align Etch) 공정으로 상기 제2폴리실리콘층(18), 유전체막(17), 제1폴리실리콘층(16) 및 터널 산화막(15)을 순차적으로 패터닝하여 상기 실리콘기판(11)의 채널 지역(C) 상부에 터널산화막(15), 플로팅게이트(16A), 유전체막(17) 및 콘트롤게이트(18A)가 순차적으로 적층된 구조의 게이트전극을 형성한 상태의 단면도인데, 상기 채널 지역(C)의 일부(C')는 상기 실리콘기판(11)에 형성된 리세스 구조의 양측부에 의해 경사면을 갖는다.FIG. 2F illustrates the second polysilicon layer 18, the dielectric layer 17, the first polysilicon layer 16, and the tunnel oxide layer 15 by a self alignment etching process using a mask for a gate electrode. Patterned sequentially, the gate electrode having a structure in which the tunnel oxide film 15, the floating gate 16A, the dielectric film 17, and the control gate 18A are sequentially stacked on the channel region C of the silicon substrate 11. A portion C ′ of the channel region C has an inclined surface by both side portions of the recess structure formed in the silicon substrate 11.
제2g도는 노출된 실리콘기판(11)에 불순물 이온을 주입하여 소오스 및 드레인영역(19 및 20)을 형성하므로써 메모리 셀이 형성된 상태의 단면도이다. 소오스영역(19) 측의 채널 영역에는 채널 이온 주입 공정시 주입된 붕소 이온에 의해 포켓 영역(21)이 형성되게 된다. 소자의 프로그램 동작시 이 포켓 영역(21)에 의해 소오스영역(19)의 전기장이 증가하게 되며, 이는 소오스 사이드에 많은 핫 케리어가 발생하게 하여 프로그램 효율 및 속도가 향상될 수 있도록 한다.FIG. 2G is a cross-sectional view of a state in which a memory cell is formed by implanting impurity ions into the exposed silicon substrate 11 to form source and drain regions 19 and 20. The pocket region 21 is formed in the channel region on the source region 19 side by boron ions implanted during the channel ion implantation process. The pocket region 21 increases the electric field of the source region 19 during the program operation of the device, which causes many hot carriers to be generated on the source side, thereby improving the program efficiency and speed.
그러면 이와 같이 형성된 메모리 셀의 프로그램 동작을 제3도를 참조하여 설명하면 다음과 같다.The program operation of the memory cell thus formed will now be described with reference to FIG. 3.
제3도에 도시된 바와 같이 프로그램 바이어스 즉, 예를들어 상기 콘트롤 게이트(18A)에 12V, 드레인영역(20)에 5V 그리고 소오스영역(19)에 접지전위(0V)가 각각 인가되면, 상기 주입된 채널 이온에 의해 상기 소오스영역(19) 측부에서 고 전기장이 형성된다. 이는 소오스영역(19) 측부에서 핫 일렉트론이 발생하여 플로팅게이트(20)로 주입되는 소오스 사이드 주입(Source Side Injection) 방식을 이용한 것이다. 그러므로 전술한 바와 같이 고 전기장에 의해 가속되고 실리콘(Si)원자와 충돌한 거의 모든 전자(10A)들의 운동 방향이 상기 플로팅게이트(16A) 방향으로 되튀게 된다. 따라서 드레인영역(20)으로 손실되는 전류의 량을 효과적으로 감소시켜 프로그램의 효율이 매우 높고, 동작시 전류의 소모가 적다.As shown in FIG. 3, when the program bias, i.e., 12V is applied to the control gate 18A, 5V to the drain region 20 and ground potential 0V to the source region 19, respectively, is injected. The generated channel ions form a high electric field on the side of the source region 19. This is a source side injection method in which hot electrons are generated at the side of the source region 19 and injected into the floating gate 20. Therefore, as described above, the direction of movement of almost all electrons 10A accelerated by the high electric field and collided with the silicon (Si) atoms is returned to the floating gate 16A. Therefore, by effectively reducing the amount of current lost to the drain region 20, the efficiency of the program is very high, the current consumption during operation is low.
상술한 바와 같이 본 발명에 의하면 소오스 사이드 주입 방식에 의해 충돌 이온화 현상후 플로팅게이트로 주입되는 전자들이 증가되기 때문에 프로그램 효율이 높으며 고속의 동작 속도를 갖는 비휘발성 메모리 셀을 구현할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, since the electrons injected into the floating gate after the collision ionization phenomenon are increased by the source side injection method, there is an excellent effect of realizing a nonvolatile memory cell having high program efficiency and a high operating speed. .
Claims (7)
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| KR100618709B1 (en) * | 2005-03-15 | 2006-09-06 | 주식회사 하이닉스반도체 | Method for forming gate in semiconductor device |
| US7795643B2 (en) | 2005-08-22 | 2010-09-14 | Samsung Electronics Co., Ltd. | Cell array of semiconductor memory device and a method of forming the same |
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| KR100543637B1 (en) * | 1998-12-29 | 2006-03-28 | 주식회사 하이닉스반도체 | Manufacturing Method of Flash Memory Device |
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| KR100618709B1 (en) * | 2005-03-15 | 2006-09-06 | 주식회사 하이닉스반도체 | Method for forming gate in semiconductor device |
| US7795643B2 (en) | 2005-08-22 | 2010-09-14 | Samsung Electronics Co., Ltd. | Cell array of semiconductor memory device and a method of forming the same |
| US8237199B2 (en) | 2005-08-22 | 2012-08-07 | Samsung Electronics Co., Ltd. | Cell array of semiconductor memory device and a method of forming the same |
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