KR100624923B1 - Method of manufacturing a flash memory cell - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell, wherein an oxide layer is formed on a stack gate structure formed by stacking a tunnel oxide film, a printing gate, a dielectric film, a control gate, and a nitride film, and the first spacer is formed from the sidewall of the control gate, and the nitride film is formed into a nitride film. Since the control gate is not exposed when the second spacer is formed from the sidewall of the stack gate structure and subsequently forms the contact hole by the self-aligned etching process, failing by the bridge of the control gate and the tungsten plug can be prevented. A manufacturing method of a flash memory cell that can secure and improve the reliability of the device is presented.

Flash memory cell, double spacer

Description

Method of manufacturing a flash memory cell             

1 (a) to 1 (d) are cross-sectional views of devices sequentially shown to explain a conventional method of manufacturing a flash memory cell.

2 is a cross-sectional photograph of a flash memory cell manufactured according to a conventional method.

3 (a) to 3 (d) are cross-sectional views of devices sequentially shown for explaining a method of manufacturing a flash memory cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

101 and 201: semiconductor substrates 102 and 202: tunnel oxide film

103 and 203: first polysilicon film 104 and 204: dielectric film

105 and 205: second polysilicon film 106 and 206: tungsten silicide film

107 and 207: first nitride film 108 and 208: source region

109 and 209: drain region 110: oxide film

111: second nitride film 112 and 212 spacer

113 and 213: Third nitride film 114 and 214: Interlayer insulating film

115: photosensitive films 116 and 215: barrier metal layer

117 and 216: tungsten plug

210: first spacer (oxide film) 211: second spacer (nitride film)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory cell. In particular, a first spacer is formed from a sidewall of a control gate using an oxide film, and a second spacer is formed from a sidewall of a stack gate structure using a nitride film. Since the control gate is not exposed when the contact hole is formed by the process, the failure of the bridge between the control gate and the tungsten plug can be prevented, thereby ensuring a process margin and improving the reliability of the device. It relates to a manufacturing method.

A conventional method of manufacturing a flash memory cell will be described with reference to FIGS. 1 (a) to 1 (d) as follows.

Referring to FIG. 1A, after the tunnel oxide layer 102 and the first polysilicon layer 103 are formed on the semiconductor substrate 101, the first polysilicon layer 103 and the mask are etched using a mask and an etching process. The tunnel oxide film 102 is patterned. The semiconductor substrate 101 uses a triple well structure according to the characteristics of the device. After the dielectric film 104, the second polysilicon film 105, the tungsten silicide film 106, and the first nitride film 107 are sequentially formed on the entire structure, a mask and an etching process are performed to perform the semiconductor substrate 101. Expose a predetermined region of. As a result, a stack gate structure in which the floating gate and the control gate are stacked is formed. The floating gate is formed of the first polysilicon film 103, and the control gate is formed of the second polysilicon film 105 and the tungsten silicide film 106. An impurity ion implantation process is then performed to form the source region 108 and the drain region 109 in predetermined regions on the semiconductor substrate 101.

Referring to FIG. 1B, the oxide film 110 and the second nitride film 111 are sequentially formed on the entire structure, and then the entire surface etching process is performed to form the oxide film 110 and the second nitride film on the sidewalls of the stack gate structure. A double spacer 112 formed of 111 is formed. The spacer is formed to prevent the loss of the stack gate structure when the self-aligned etching process is performed. The spacer is formed of a nitride film. However, in the flash memory cell, when the spacer is formed only of the nitride layer, electrons occupied by the floating gate may be captured by the nitride layer, thereby causing data loss. Therefore, in a cell structure having a floating gate, such as a flash memory cell, a certain amount of insulating material is required to prevent a phenomenon in which electrons occupied in the floating gate to some extent are occupied by a nitride spacer, thereby lowering a potential of the floating gate. Accordingly, a dual structure of an oxide film and a nitride film is used.

Referring to FIG. 1C, a third nitride film 113 is formed over the entire structure, and an interlayer insulating film 114 is formed and then planarized. As the interlayer insulating film, a laminated structure of an insulating film, a PSG film, and a BPSG film is used. After the photoresist film 115 is formed on the entire structure, the photoresist film is patterned by an exposure and etching process using a contact mask. The interlayer insulating layer 114 and the third nitride layer 113 are etched using a self-aligned etching process using the photoresist pattern 115 as a mask to form a contact hole exposing the drain region 109. At this time, a portion of the spacer 112 is also etched to expose a portion of the stack gate structure, that is, the tungsten silicide layer 106.

Referring to FIG. 1D, after the photoresist pattern 115 is removed and the barrier metal layer 116 is formed over the entire structure including the contact hole while the tungsten silicide layer 106 of the stacked gate structure is exposed, the barrier metal layer 116 is formed. Tungsten is embedded to form a plug 117.

However, since a bridge phenomenon occurs in which the tungsten silicide layer 106, the barrier metal layer 116, and the tungsten plug 117 of the exposed stack gate structure are conductive, column fail and bit line fail are generated. The cross-sectional photograph of such a phenomenon is shown in FIG. In FIG. 2, reference numeral A denotes a state in which a bridge phenomenon occurs because the tungsten silicide layer 106, the barrier metal layer 116, and the tungsten plug 117 are conductive.

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory cell capable of preventing the generation of a fail by not exposing the tungsten silicide of the stacked gate structure when performing the self-aligned etching process.

The present invention for achieving the above object is to form a stacked gate structure in which a tunnel oxide film, a floating gate, a dielectric film, a control gate and a first nitride film are stacked in a selected region on the semiconductor substrate, and performing an impurity ion implantation process. Forming a source and a drain region in a predetermined region of the semiconductor substrate, and forming an oxide film over the entire structure, and then performing an entire surface etching process to form a source and drain region from the sidewall of the control gate to the upper portion of the semiconductor substrate. Forming a second spacer on the entire structure, and then performing a front side etching process to form a second spacer formed from the sidewall of the first nitride layer to the upper portion of the semiconductor substrate by performing a front etching process; After forming the third nitride film and the interlayer insulating film on the whole structure Forming a contact hole exposing the drain region by performing a predetermined etching process; forming a barrier metal layer over the entire structure including the contact hole, and then forming a plug to fill the contact hole; Characterized in that made.

The present invention will be described in detail with reference to the accompanying drawings.

3 (a) to 3 (d) are cross-sectional views of devices for explaining a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 3A, after the tunnel oxide layer 202 and the first polysilicon layer 203 are formed on the semiconductor substrate 201, the first polysilicon layer 203 and the mask are etched using a mask and an etching process. The tunnel oxide film 202 is patterned. The semiconductor substrate 201 uses a triple well structure according to the characteristics of the device. After the dielectric film 204, the second polysilicon film 205, the tungsten silicide film 206, and the first nitride film 207 are sequentially formed on the entire structure, a mask and an etching process are performed to perform the semiconductor substrate 201. Expose a predetermined region of. As a result, a stack gate structure in which the floating gate and the control gate are stacked is formed. The floating gate is formed of the first polysilicon film 203, and the control gate is formed of the second polysilicon film 205 and the tungsten silicide film 206. An impurity ion implantation process is then performed to form the source region 208 and the drain region 209 in the predetermined region on the semiconductor substrate 201.

Referring to FIG. 3B, after forming an oxide film on the entire structure, a first etching process is performed on the sidewalls of the stack gate structure by performing an entire surface etching process. The oxide film uses MTO and allows the first spacer 210 to be formed under the first nitride film 207.

Referring to FIG. 3C, after forming the second nitride layer on the entire structure, the entire surface etching process is performed to form the second spacer 211 on the sidewall of the stack gate structure. An etching process for forming the second spacer 211 is performed until the first nitride film 207 is exposed. As a result, a spacer 212 having a double structure of the first and second spacers 210 and 211 is formed.

Referring to FIG. 3D, a third nitride film 213 is formed over the entire structure, and an interlayer insulating film 214 is formed and then planarized. After the photoresist is formed over the entire structure, the photoresist layer is patterned by an exposure and etching process using a contact mask. The interlayer insulating film 214 and the third nitride film 213 are etched using a self-aligned etching process using a photoresist pattern (not shown) as a mask to form a contact hole exposing the drain region 209. At this time, even if the upper portion of the second spacer 211 in which the contact hole is a nitride film is damaged, the first spacer 210 is not damaged and the tungsten silicide film 206 is not exposed. The photoresist pattern is removed, a barrier metal layer 215 is formed on the entire structure including the contact hole, and tungsten is embedded to form a plug 216.

As described above, according to the present invention, when the first spacer is formed from the sidewall of the control gate using an oxide film, the second spacer is formed from the sidewall of the stack gate structure using a nitride film, and then the control gate is formed when a contact hole is formed by a self-aligned etching process. By not exposing, failing by the bridge between the control gate and the tungsten plug can be prevented, thereby ensuring a process margin and improving the reliability of the device.

Claims (1)

Forming a stacked gate structure in which a tunnel oxide film, a floating gate, a dielectric film, a control gate, and a first nitride film are stacked in a selected region over the semiconductor substrate; Performing an impurity ion implantation process to form a source and a drain region in a predetermined region of the semiconductor substrate; Forming an oxide layer on the entire structure and performing a front side etching process to form a first spacer formed from the sidewall of the control gate of the stack gate structure to an upper portion of the semiconductor substrate; Forming a second spacer on the entire structure and then performing a front surface etching process to form a second spacer formed from the sidewall of the first nitride film to the upper portion of the semiconductor substrate by performing a front etching process; Forming a contact hole for exposing the drain region by performing a self-aligned etching process after forming a third nitride film and an interlayer insulating film over the entire structure; And forming a plug to form the barrier metal layer on the entire structure including the contact hole and to fill the contact hole.

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