KR20070059324A - Method of manufacturing a nand type flash memory device - Google Patents

Abstract

A method for fabricating a NAND-type flash memory device is provided to minimize the possibility of damaging a SAC(self-align contact) in an etch process for forming a contact by forming a gate spacer nitride layer after a gate buffer oxide layer in a contact formation region is selectively removed by an etch process. After a gate in which a tunnel oxide layer(102), a plurality of conductive layers and a hard mask layer(112) are stacked is formed in a predetermined region on a semiconductor substrate(100), a selective oxide process is performed on the sidewall of the gate. A junction region(116) is formed on the semiconductor substrate between the gates. After a buffer oxide layer(118) is formed on the resultant structure, a part of the buffer oxide layer formed on a contact hole formation region and the hard mask layer are removed by a selective wet-etch process using chemical made of NH4F and HF. A spacer nitride layer(122), an SAC buffer oxide layer(124), an SAC nitride layer(126), a first interlayer dielectric and a second interlayer dielectric(130) are sequentially formed on the resultant structure. An etch process for forming a self-align contact is performed to form a contact hole, and the SAC nitride layer, the SAC buffer oxide layer and the spacer nitride layer in the lower part of the contact hole are removed to expose the junction part. A conductive material is filled in the contact hole to form a contact plug(134).

Description

Method of manufacturing a NAND type flash memory device

1A to 1E are cross-sectional views illustrating a device for explaining a method of manufacturing a NAND type flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

      100 semiconductor substrate 102 tunnel oxide film

      104: first polysilicon film 106: dielectric film

      108: second polysilicon film 110: tungsten silicide film

      112: hard mask film 114: spacer

      116: junction 118: buffer oxide film

      120: first photoresist film 122: spacer nitride film

      124: SAC buffer oxide film 126: SAC nitride film

      128: first interlayer insulating film 130: second interlayer insulating film

      132: second photoresist film 134: contact plug

      136: nitride film stopper 138: third interlayer insulating film

      140: third photoresist film 142: conductive film

The present invention relates to a method of manufacturing a NAND type flash memory device, and in particular, by removing the gate buffer oxide film in the region where a contact is to be formed by a selective etching process, and forming a gate spacer nitride film, thereby performing self-alignment during the etching process for forming a contact. The present invention relates to a method of manufacturing a NAND-type flash memory device capable of increasing the etching margin by minimizing the possibility of damage to an in-contact.

Hereinafter, a conventional method of manufacturing a NAND flash memory device will be briefly described. A floating gate is formed by stacking a tunnel oxide film, a first polysilicon film, a dielectric film, a second polysilicon film, a tungsten silicide film, and a hard mask film on a semiconductor substrate. And a gate electrode having a stacked control gate are formed, and a gate electrode having the same stacked structure is formed in the selection transistor region. Then, an oxidation process is performed to remove micro trenches and plasma damage generated during the gate etching, thereby forming an oxide film on the gate sidewalls, preferably sidewalls of the first and second polysilicon layers. An ion implantation step is then performed to form a junction that acts as a source and a drain.

After the oxide film and the SAC nitride film are formed over the entire structure, an insulating film is insulated between the gate lines and an insulating film for insulating the upper wiring. Then, a predetermined region of the insulating film, the SAC nitride film, and the oxide film is etched by a self-aligned contact etching process to form a contact that exposes the junction portion. Then, a conductive layer is formed to fill the contact to form a contact plug.

However, in the related art, when the source / drain select line space is reduced to reduce the chip size, a punch is generated in the SAC nitride film during the SAC nitride film etching by the self-aligned contact etching process, and subsequent cleaning is performed. As the process progresses, the loss of oxide is increased, and the contact plug and the gate are shorted, or the sealing function, which is a main function of the SAC nitride film, cannot be performed. have.

An object of the present invention is to remove the gate buffer oxide layer in the region where a contact is to be formed by a selective etching process, and then to form a gate spacer nitride layer, thereby minimizing the possibility of damage of the self-aligned contact during the etching process for forming a contact. An object of the present invention is to provide a method of manufacturing a NAND-type flash memory device capable of increasing an etching margin.

In the method of manufacturing a NAND type flash memory device according to an embodiment of the present invention, a gate in which a tunnel oxide film, a plurality of conductive layers, and a hard mask film are stacked is formed in a predetermined region on a semiconductor substrate, and then a selective oxidation process is performed on the gate sidewall. Performing; Forming a junction region on the semiconductor substrate between the gates; Forming a buffer oxide layer on the entire structure including the gate, and then performing a selective etching process to remove a region where a contact hole is to be formed and a portion of the buffer oxide layer formed on the hard mask layer; Sequentially forming a spacer nitride film, a SAC buffer oxide film, a SAC nitride film, a first interlayer insulating film, and a second interlayer insulating film over the entire structure; Forming a contact hole by performing an etching process for forming a self-aligned contact, and removing the SAC nitride film, the SAC buffer oxide film, and the spacer nitride film at the bottom of the contact hole to expose the junction; Embedding a conductor in the contact hole to form a contact plug.

After forming the contact plug, forming a nitride film stopper and a third interlayer insulating film on the entire structure; Etching a portion of the third interlayer insulating film and the nitride film stopper to expose the contact plug; The method may further include forming a conductive layer on the exposed contact plug.

The selective etching process is wet etching using a chemical compound of NH ₄ F and HF combination.

The SAC nitride film is formed by performing a low pressure thermal process.

The etching process for forming the self-aligned contact may include C ₅ F ₈ / Ar / O ₂ or C ₅ F ₈ / Ar / O ₂ / CH ₂ F ₂ or C ₄ F ₆ / O ₂ / Ar / CF ₄ . By using a combination of gas (Gas) is carried out using a gas combination to have an etching selectivity of about 10 to 20 times faster than the nitride (Oxide) etch rate.

Before and after the removal of the SAC nitride film, the SAC buffer oxide film and the spacer nitride film, a post etch treatment process using a combination of O ₂ and Ar is performed to remove the polymer and other residues.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1A to 1E are cross-sectional views of devices sequentially illustrating a method of manufacturing a NAND-type flash memory device according to an embodiment of the present invention, and include a gate cross-sectional view including a selection transistor region in which source / drain contacts are to be formed. It is shown.

Referring to FIG. 1A, a tunnel oxide film 102, a first polysilicon film 104, a dielectric film 106, and a second polysilicon film 108 are formed on a semiconductor substrate 100 on which a cell region and a selection transistor region are determined. ), A tungsten silicide layer 110 and a hard mask layer 112 are stacked to form a gate electrode in which a floating gate and a control gate are stacked in a cell region, and a gate electrode having the same structure is formed in a selection transistor region.

A selective oxidation process is performed to form spacers 114 with oxides on the sidewalls of the gate sidewalls, preferably the first polysilicon film 104, the second polysilicon film 108, and the tungsten silicide film 110. do. The ion implantation process is then performed to form the junction 116 serving as a source and a drain.

The buffer oxide film 118 is formed on the entire structure, but the buffer oxide film 118 formed in the gate line is formed to be different, so that the buffer oxide film 118 formed in the hard mask film 112 is formed relatively thinner than other portions. It is desirable to.

FIG. 1B is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1A. Referring to FIG. 1B, a first photoresist layer 120 is formed to remove a region where a source / drain contact is to be formed and a portion of the buffer oxide layer 118 formed on the hard mask layer 112 of the selection gate.

The reason for removing the region where the source / drain contact is to be formed and a portion of the buffer oxide layer 118 formed on the hard mask layer 112 of the selection gate is that the buffer oxide layer 118 remains in the hard mask layer 112 of the selection gate. If present, since the buffer oxide layer 118 is rapidly etched from the hard mask layer 112 due to the etching selectivity during the subsequent self-aligned contact etching process, SAC nitride damage may occur, and the oxide loss may be lost during the subsequent cleaning process. This is to prevent this because the increase may cause a short between the gate and the contact plug.

In the buffer oxide film 118 removal process, it is preferable to perform a wet etching process using a wet chemical compound of NH ₄ F and HF combination.

FIG. 1C is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1B. Referring to FIG. 1C, after the first photoresist film 120 is removed, the spacer nitride film 122, the SAC buffer oxide film 124, and the SAC nitride film 126 are formed on the entire structure.

Here, the SAC nitride film 126 may be formed by performing a low pressure thermal process in order to effectively perform a sealing role of the gate line while having a thin thickness.

After forming the first interlayer insulating film 128 on the entire structure, and then planarizing and forming the second interlayer insulating film 130, a second photoresist for forming a source / drain contact on the second interlayer insulating film 130. A film 132 is formed.

Next, an etching process for forming a self-aligned contact is performed, but C ₅ F ₈ / Ar / O ₂ or C ₅ F ₈ / Ar / O ₂ / CH ₂ F ₂ or C ₄ F ₆ / O ₂ / Ar / The second photoresist film is formed by using a gas combination such that the etching rate of oxide to Nitride is about 10 to 20 times faster by using a gas combination such as CF ₄ . Remove 132.

Accordingly, since the buffer oxide layer 118 between the hard mask layer 112 and the SAC nitride layer 126 of the selection gate is removed in advance in the region where the contact hole is formed during the etching of the SAC buffer oxide layer 124. Even if some photo mask alignment shift occurs, the hard mask layer 112 and the SAC nitride layer 126 of the selection gate sufficiently serve as an etch stop layer, thereby preventing damage to the self-aligned contact. have.

FIG. 1D is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1C. Referring to FIG. 1D, the semiconductor substrate 100 is exposed by removing the SAC nitride film 126, the SAC buffer oxide film 124, and the spacer nitride film 122 remaining at the bottom of the contact.

Before and after the removal of the SAC nitride film 126, the SAC buffer oxide film 124, and the spacer nitride film 122, a post etch treatment process using a combination of O ₂ and Ar is performed to polymer and other residues. Remove it.

Next, a contact plug 134 is formed by embedding a conductor in the contact hole, and then a planarization process is performed.

After forming the nitride film stopper 136 so as to enable uniform etching depth even when an overlay shift occurs in the photomask for connecting subsequent contacts or lines on the entire structure, a third interlayer insulating film 138 is formed. The third photoresist layer 140 is formed to etch the region to be connected to the contact plug 134.

FIG. 1E is a cross-sectional view of a semiconductor device having undergone the following process of FIG. 1D. Referring to FIG. 1E, a portion of the third interlayer insulating film 138 and the nitride film stopper 136 are etched using the third photoresist film 140 as a mask to expose the contact plug 134, and then the third photoresist film. Remove 140.

Next, a conductor is embedded to contact the exposed contact plug 134 to form a conductive film 142.

As described above, the process of FIGS. 1A to 1E, which is a preferred embodiment, removes the gate buffer oxide layer 118 in the region where a contact is to be formed by a selective etching process, and then forms a gate spacer nitride layer 122. The etching margin can be increased by minimizing the possibility of damaging the self-aligned contact during the formation of the etching process.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible.

Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, after removing the gate buffer oxide layer in the region where a contact is to be formed by a selective etching process, a gate spacer nitride layer is formed, and thus the possibility of damaging the self-aligned contact during the etching process for forming a contact is possible. By increasing the etching margin (Margin) can be increased.

Claims (6)

Forming a gate in which a tunnel oxide film, a plurality of conductive layers, and a hard mask film are stacked in a predetermined region above the semiconductor substrate, and then performing a selective oxidation process on the gate sidewalls; Forming a junction region on the semiconductor substrate between the gates; Forming a buffer oxide layer on the entire structure including the gate, and then performing a selective etching process to remove a region where a contact hole is to be formed and a portion of the buffer oxide layer formed on the hard mask layer; Sequentially forming a spacer nitride film, a SAC buffer oxide film, a SAC nitride film, a first interlayer insulating film, and a second interlayer insulating film over the entire structure; Forming a contact hole by performing an etching process for forming a self-aligned contact, and removing the SAC nitride film, the SAC buffer oxide film, and the spacer nitride film at the bottom of the contact hole to expose the junction; And embedding a conductor in the contact hole to form a contact plug. The method of claim 1, After forming the contact plug, Forming a nitride film stopper and a third interlayer insulating film on the entire structure; Etching a portion of the third interlayer insulating film and the nitride film stopper to expose the contact plug; And forming a conductive layer on the exposed contact plug. The method of claim 1, The selective etching process is a method of manufacturing a NAND flash memory device for performing wet etching using a chemical (Chemical) of NH ₄ F and HF combination. The method of claim 1, The SAC nitride film is formed by performing a low pressure thermal process. The method of claim 1, The etching process for forming the self-aligned contact, Nitride (Gas) such as C ₅ F ₈ / Ar / O ₂ or C ₅ F ₈ / Ar / O ₂ / CH ₂ F ₂ or C ₄ F ₆ / O ₂ / Ar / CF ₄ A method of manufacturing a NAND flash memory device using a combination of gases such that an etching rate of oxide is about 10 to 20 times faster than that of Nitride). The method of claim 1, NAND type flash memory that performs a post etch treatment process of O ₂ and Ar combination to remove polymer and other residues before and after the removal of the SAC nitride film, the SAC buffer oxide film and the spacer nitride film. Method of manufacturing the device.

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