KR20050024667A - Method for fabricating butting contact in semiconductor device - Google Patents

Abstract

PURPOSE: A method of fabricating a butting contact in a semiconductor device is provided to restrain an etching process to an intermediate temperature oxide layer as a buffer layer by forming a selective epitaxial growth layer having sufficient etch selectively on a gate conductive layer pattern. CONSTITUTION: A gate conductive layer pattern(308) is formed by inserting a gate insulating layer(306) into a semiconductor substrate(302) having an active region. A buffer layer is formed on the gate conductive layer pattern and the active region. A gate spacer is formed on a lateral part of the gate conductive layer pattern. A selective epitaxial growth layer(320) is formed on an upper surface of the gate conductive layer pattern. An etch stop layer is formed to cover the selective epitaxial growth layer, the gate spacer, and the buffer layer. An interlayer dielectric is formed to cover the etch stop layer and the active region. A butting contact hole(330) is formed by removing partially the interlayer dielectric and the etch stop layer.

Description

Method for fabricating butting contact in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a butt contact of a semiconductor device.

Recently, many efforts have been made to increase the degree of integration of semiconductor devices, but it is also true that there are some limitations. One of these limitations is a contact structure for creating a path for applying a signal to an active, source, drain, or gate of a semiconductor device. This is because the contact structure of the semiconductor device should be made while ensuring alignment margin or device isolation margin. As one method for removing such a limiting factor, a butting contact for connecting a gate and an active is mainly used in the case of a semiconductor memory device such as an SRAM or a semiconductor logic device such as a CPU.

1A to 1F are cross-sectional views illustrating a conventional butt contact forming method of a semiconductor device.

First, as shown in FIG. 1A, a gate insulating film 106 is formed on a semiconductor substrate 102 in which an active region is defined by a device isolation film 104 having a trench structure, and a gate stack 108 is formed on the gate insulating film 106. ). The gate stack 108 is a structure in which the gate conductive film pattern 108a, the metal silicide film 108b, and the antireflection film ARL 108c are sequentially stacked on the gate insulating film 106. Next, a shallow impurity region 110 is formed in the upper region of the semiconductor substrate 102 exposed by the gate stack 108.

Next, as shown in FIG. 1B, a portion of the gate insulating film 106 covering the exposed surface of the semiconductor substrate 102 is removed, and an intermediate temperature oxidation (MTO) film 112 as a buffer layer is formed on the entire surface. Next, the gate spacer 114 is formed on both sides of the gate stack 108 by performing a conventional gate spacer forming process. Next, an ion implantation process using the gate spacer 114 as an ion implantation mask is performed to form a deep impurity region 116 surrounded by a shallow impurity region 110 in the upper region of the semiconductor substrate 102. The shallow impurity region 110 and the deep impurity region 116 together form an impurity region having a lightly doped drain (LDD) structure.

Next, as illustrated in FIG. 1C, an etching process using phosphoric acid as an etching solution is performed to reduce the thickness of the gate spacer 114. As the thickness of the gate spacer 114 decreases, the gap W ₂ between adjacent gate spacers 114 becomes larger than the gap before the etching process (W _{1 in} FIG. Can be secured. Next, as shown in FIG. 1D, a silicon nitride film 118 as an etch stop film is formed on the entire surface of the resultant product of FIG. 1C. At this time, a thinning phenomenon occurs in which the silicon nitride film 118 is stacked to a thin thickness at the edge of the gate stack 108 (a portion indicated by A in the drawing).

Next, as shown in FIGS. 1E and 1F, an interlayer insulating film 120 is formed, and a photoresist film pattern 122 is formed thereon. Then, the butting contact hole 124 is formed by removing the interlayer insulating film 120 exposed by the photoresist film pattern 122. The butting contact hole 124 is for connecting the gate and the active, and therefore must expose the gate and the active together. However, there is a step between the top surface of the gate and the top surface of the active, which causes a problem that the gate and the active is not exposed together.

For example, as shown in FIG. 1E, when the etching end position is determined as the upper surface of the gate stack 108 during the etching process with respect to the interlayer insulating layer 120, the active is not exposed as indicated by B of FIG. 1E. This happens. In addition, as shown in FIG. 1F, when the etching end position is determined as the upper surface of the active surface, that is, the upper surface of the semiconductor substrate 102, during the etching process of the interlayer insulating film 120, as indicated by C of FIG. 1F. Transient etching is performed on the gate stack 108, and the etching process continues while all of the thin silicon nitride film 118 is removed from the edge portion of the gate stack 108. As a result, the intermediate temperature oxide film 112 between the gate stack 108 and the gate spacer 114 is completely etched.

2A and 2B are cross-sectional views illustrating another example of a method of forming a butt contact of a conventional semiconductor device.

First, as shown in FIG. 2A, after performing the same process as described with reference to FIGS. 1A to 1D, an interlayer insulating film 202 is formed on the resultant product of FIG. 1D. A portion of the interlayer insulating layer 202 is removed using a first mask layer pattern (not shown) to form a first butting contact hole 204 that exposes the active portion of the semiconductor substrate 102. In addition, the first butting contact hole 204 is formed to completely fill the first butting contact hole 204. Next, a normal planarization process is performed.

Next, as shown in FIG. 2B, the second butting contact hole exposing the upper surface of the gate stack 108 by removing a part of the interlayer insulating layer 202 using a second mask layer pattern (not shown) ( 210). The second butting contact hole 210 also exposes the first butting contact conductive film 206. Next, a second butting contact conductive film 212 is formed to completely fill the second butting contact hole 210. The flattening process is performed to complete the butting contact.

Such a method does not occur as shown in FIGS. 1E and 1F, but since the etching process for the active exposure and the etching process for the gate stack exposure are performed separately, two mask layer patterns are formed. There is a problem that the number of process steps is increased, such as an etching process, a two-step planarization process, and the like.

An object of the present invention is to provide a method of forming a butt contact of a semiconductor device capable of simultaneously exposing a gate and an active through a single butt contact hole forming process.

In order to achieve the above technical problem, a butting contact forming method of a semiconductor device according to an embodiment of the present invention, forming a gate conductive film pattern on the semiconductor substrate having an active region via a gate insulating film; Forming a buffer layer covering both the gate conductive layer pattern and the active region; Forming a gate spacer on a side of the gate conductive layer pattern; Forming a selective epitaxial growth film on an upper surface of the gate conductive film pattern; Forming an etch stop layer covering the selective epitaxial growth layer, the gate spacer, and the buffer layer; Forming an interlayer insulating layer covering the etch stop layer and the active region; Removing a portion of the interlayer insulating layer and the etch stop layer to form a butting contact hole exposing both a part surface of the selective epitaxial growth layer and a part surface of the active region; And filling the butting contact hole with a conductive material film.

The buffer layer may be formed using an intermediate temperature oxide layer, and the etch stop layer may be formed using a silicon nitride layer or a silicon oxide nitride layer.

The gate conductive layer pattern may be formed using a doped polysilicon layer pattern, and the selective epitaxial growth layer may be a single crystal silicon layer.

It is preferable to further include forming a metal salicide film on the selective epitaxial growth film after forming the selective epitaxial growth film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms and, therefore, the scope of the present invention should not be construed as limited to the embodiments described below.

3A to 3H are cross-sectional views illustrating a method of forming a butting contact of a semiconductor device according to the present invention.

Referring first to FIG. 3A, a trench isolation device isolation layer 304 is formed in a semiconductor substrate 302 such as silicon to define an active region. In some cases, a device isolation film having a LOCOS structure may be used as the device isolation film 304. Next, a gate insulating film 306 such as an oxide film is formed on the surface of the semiconductor substrate 302 in a thin thickness. A gate conductive film pattern 308 and an antireflection film pattern 310 are formed on the gate insulating film 306. The gate conductive film pattern 308 is a polysilicon film pattern, and the anti-reflection film pattern 310 is a silicon oxide nitride (SION) film pattern. The gate conductive film pattern 308 and the anti-reflection film pattern 310 expose a portion of the active area. Next, a conventional ion implantation process for forming a source / drain of the LDD structure is performed to form a shallow first impurity region 312 in the upper region of the semiconductor substrate 302.

Next, referring to FIG. 3B, the gate insulating film 306 exposed on the surface of the semiconductor substrate 302 is removed to expose the first impurity region 312 of the semiconductor substrate 302. A buffer film 314 is formed over the entire surface. An MTO film is used as the buffer film 314. The buffer film 314 covers the gate conductive film pattern 308 and the anti-reflection film pattern 310, and simultaneously covers the exposed surface of the semiconductor substrate 302. Next, the gate spacer 316 is formed by performing a normal gate spacer forming process. That is, a gate spacer material film, for example, a nitride film, is formed on the entire surface, and then a process such as etchback is performed to remove all the gate spacer material film on the upper portion of the buffer film 314 and to leave only the side of the gate spacer 316. ). Next, a conventional ion implantation process for source / drain formation of the LDD structure is performed to form a deep second impurity region 318 surrounded by the first impurity region 312 in the upper region of the semiconductor substrate 302. . The impurity concentration in the second impurity region 318 is higher than the impurity concentration in the first impurity region 312.

Next, referring to FIG. 3C, an etching process is performed to remove the anti-reflection film pattern 310 of FIG. 3B on the gate conductive film pattern 308 to expose the upper surface of the gate conductive film pattern 308. A wet etching process is used as the etching process, and a solution having a high etching selectivity between the buffer layer 314 and the anti-reflection film pattern 310 covering the exposed surface of the semiconductor substrate 302 is used as the etching solution. Otherwise, all of the buffer film 314 on the semiconductor substrate 302 may be removed by the etching process, and as a result, the exposed semiconductor substrate 302 may be damaged. For example, when the antireflection film pattern 310 is a silicon oxide nitride film pattern and the buffer film 314 is an MTO film, a phosphoric acid (H ₃ PO ₄ ) solution may be used as an etching solution. In the case of the phosphoric acid solution, the etching ratio of the silicon oxide nitride film and the MTO film is approximately 200: 4. ) Remain on the semiconductor substrate 302 without being removed to protect the semiconductor substrate 302.

Next, referring to FIG. 3D, the selective epitaxial growth process is performed to form the selective epitaxial growth layer 320 on the exposed gate conductive layer pattern 308. Since the gate conductive film pattern 308 is a polysilicon film pattern, the selective epitaxial growth film 320 becomes a single crystal silicon film. This single crystal silicon film has a sufficient etching selectivity with an etch stop film, such as a silicon nitride film, to be formed in a subsequent step.

Next, referring to FIG. 3E, a metal salicide layer 322 is formed on the selective epitaxial growth layer 320. To this end, first, a metal film, such as a cobalt (Co) film, is formed on the entire surface and heat is applied. Then, a reaction occurs at the boundary between the selective epitaxial growth film 320 and the cobalt film to form a cobalt salicide film 322. After the cobalt salicide film 322 is made, all of the cobalt film that is not reacted is removed. Next, an etch stop film 324 is formed on the entire surface. The etch stop film 324 is formed using a material film having a sufficient etching selectivity with the selective epitaxial growth film 320. For example, when the selective epitaxial growth film 320 is a single crystal silicon film, a silicon nitride film is used as the etch stop film 324. The etch stop layer 324 covers all of the gate spacer 316, the selective epitaxial growth layer 320, and the buffer layer 314.

Next, referring to FIG. 3F, an interlayer insulating film 324 is formed on the etch stop film 324. A mask film pattern, for example, a photoresist film pattern 328, is formed on the interlayer insulating film 324. The photoresist film pattern 328 has an opening that exposes a portion of the surface of the interlayer insulating film 324.

Next, referring to FIG. 3G, an etching process using the photoresist film pattern 328 as an etching mask is performed to remove the exposed interlayer insulating film 324. This etching process is performed until the top surface of the metal salicide film 322 and a part of the surface of the semiconductor substrate 302 are exposed. Although the thickness of the interlayer insulating film 326 to be etched at the portion where the gate conductive pattern 308 is disposed is different from the thickness of the interlayer insulating film 326 to be etched at the surface portion of the semiconductor substrate 302, the semiconductor substrate ( Even though the etch stop layer 324 on the gate conductive layer pattern 308 is exposed faster than the etch stop layer 324 on the surface, the selective epitaxial growth layer 320 may be formed on the etch stop layer 324. Since it has a sufficient etching selectivity, the buffer film 314 disposed under the selective epitaxial growth film 320 is not affected during the etching process. After the etching process, a butting contact hole 330 exposing a part of the surface of the metal salicide layer 322 or the selective epitaxial growth layer 320 and exposing all of the surface of the active region of the semiconductor substrate 302. This is made.

Next, referring to FIG. 3H, the butting contact conductive layer 332 is formed to completely fill the inside of the butting contact hole 330. Since the butting contact conductive film 332 is also formed on the interlayer insulating film 326, the butting contact conductive film 332 is formed on the interlayer insulating film 326 by performing a planarization process, for example, a chemical mechanical polishing (CMP) process. ) Are all removed.

As described above, according to the method of forming a butting contact of a semiconductor device according to the present invention, an etching stop film and a selective epitaxial growth film having sufficient etching selectivity are formed on the gate conductive film pattern during the etching process. It provides an advantage that the etching of the intermediate temperature oxide film as a buffer layer can be suppressed.

1A to 1F are cross-sectional views illustrating a conventional butt contact forming method of a semiconductor device.

2A and 2B are cross-sectional views illustrating another example of a method of forming a butt contact of a conventional semiconductor device.

3A to 3H are cross-sectional views illustrating a method of forming a butting contact of a semiconductor device according to the present invention.

Claims (4)

Forming a gate conductive film pattern on the semiconductor substrate having an active region through a gate insulating film; Forming a buffer layer covering both the gate conductive layer pattern and the active region; Forming a gate spacer on a side of the gate conductive layer pattern; Forming a selective epitaxial growth film on an upper surface of the gate conductive film pattern; Forming an etch stop layer covering the selective epitaxial growth layer, the gate spacer, and the buffer layer; Forming an interlayer insulating layer covering the etch stop layer and the active region; Removing a portion of the interlayer insulating layer and the etch stop layer to form a butting contact hole exposing both a part surface of the selective epitaxial growth layer and a part surface of the active region; And And filling the butting contact hole with a conductive material film. The method of claim 1, And the buffer film is formed using an intermediate temperature oxide film, and the etch stop film is formed using a silicon nitride film or a silicon oxide nitride film. The method of claim 1, And the gate conductive layer pattern is formed using a doped polysilicon layer pattern, and the selective epitaxial growth layer is a single crystal silicon layer. The method of claim 1, And forming a metal salicide film on the selective epitaxial growth film after the selective epitaxial growth film is formed.