KR20030094742A - Method for manufacturing semiconductor device including silicide process - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device including a silicide process is provided to effectively reduce contact resistance by introducing a source/drain layer or a conductive contact and by performing self-aligned silicide process on the surface of the source/drain layer or conductive contact. CONSTITUTION: A gate stack(200) is formed on a semiconductor substrate(100) including a cell region and a core region. The source/drain layer(350) raised from the surface of the substrate exposed to the gate stack is grown by a selectively epitaxial growth(SEG) process. The raised source/drain layer is covered with an interlayer dielectric. A conductive contact(370) penetrates the interlayer dielectric to be electrically connected to the raised source/drain layer in the cell region. The interlayer dielectric on the core region is selectively removed to expose the upper surface of the raised source/drain layer on the core region. A silicide layer is formed by simultaneously performing a silicide process on the surface of the exposed raised source/drain layer and the surface of the conductive contact.

Description

Method for manufacturing semiconductor device including silicide process {Method for manufacturing semiconductor device including silicide process}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing, and more particularly, to a semiconductor device manufacturing method including a silicide process for implementing a reduction in resistance.

As semiconductor memory devices, such as DRAM (DRAM) devices, have been increasingly integrated, pattern miniaturization or design rules have been rapidly decreasing. As design rules decrease, it is important to more secure electrical connection between integrated devices. To this end, methods for reducing the electrical resistance involved in the electrical connection between the devices have been proposed.

For example, silicide processes are being introduced to reduce contact resistance to source and drain in the core region or peripheral circuit regions of a DRAM device. In addition, in the cell region of the DRAM device, a silicide process is introduced in order to reduce contact resistance to conductive contact. However, this silicide process is currently introduced separately for each purpose. Therefore, as many silicide processes are introduced for each purpose during the manufacture of DRAM devices, the manufacturing process of the entire DRAM device becomes more complicated. The complexity of the manufacturing process of the entire DRAM device is a constraint on the effective introduction of the silicide process.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a semiconductor device capable of preventing a manufacturing process of an entire semiconductor device from becoming very complicated and effectively reducing a resistance including a silicide process.

1 to 9 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device including a silicide process according to a first embodiment of the present invention.

2 to 17 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device including a silicide process according to a second embodiment of the present invention.

One aspect of the present invention for achieving the above technical problem, there is provided a semiconductor device manufacturing method for performing a silicide process on a cell region (core region) and a core region (core region) at the same time.

The manufacturing method includes forming a gate stack on a semiconductor substrate including a cell region and a core region, and a source raised from a surface of the semiconductor substrate exposed to the gate stack. And growing a raised source and drain layer to selectively epitaxial growth (SEG), and forming an interlayer insulating layer covering the raised source and drain layer. Forming a conductive contact electrically penetrating the interlayer insulating layer and electrically connected to the raised source and drain layer of the cell region, and the interlayer insulating layer portion on the core region. Selectively removing the oxide to expose the top surface of the raised source and drain layer of the core region, and And forming a silicide layer by simultaneously performing a silicide process on the surface of the raised source and drain layers and the surface of the conductive contact.

Wherein forming the conductive contact comprises forming a contact hole in the interlayer insulating layer exposing the raised source and drain layers of the cell region below, and from the exposed source and drain layer surfaces. The method may include growing the conductive contact to selectively epitaxial growth (SEG). In this case, the manufacturing method may further include performing ion implantation into the conductive contact grown after the growing of the conductive contact.

The manufacturing method may further include performing ion implantation on the raised source and drain layers after growing the raised source and drain layers.

The manufacturing method may further include forming an etch stop layer under the interlayer insulating layer, and the etch stop layer may serve as an etch stop when selectively removing a portion of the interlayer insulating layer on the core region. The etching termination may be performed at a portion located on the core region of the etching termination layer, and the manufacturing method may include selectively removing a portion located on the core region of the etching termination layer serving as an etching termination layer. It may further include.

The manufacturing method may further include forming a buffer layer under the etch stop layer. In this case, the etching termination layer may include a silicon nitride layer, and the buffer layer may include a silicon oxide layer.

The manufacturing method may include sequentially forming a second etch stop layer and a second interlayer insulating layer covering the silicide layer, and planarizing the second interlayer insulating layer by using the second etch stop layer as an etch stop. It may further include.

In addition, the manufacturing method includes forming a gate stack on a semiconductor substrate including a cell region and a core region, and forming a first interlayer insulating layer covering the gate stack. Selectively etching the first interlayer insulating layer to form a contact hole exposing the semiconductor substrate portion of the core region and exposing the semiconductor substrate portion of the cell region, and the exposed semiconductor substrate Growing a raised source and drain layer from a surface to selectively epitaxial growth (SEG) and silicide process on the raised source and drain layer Forming a silicide layer, and forming a second interlayer insulating layer covering the silicide layer and having a planarized surface. It may be made, including.

Here, the manufacturing method may further comprise the step of performing ion implantation to the raised source and drain layer after growing the raised source and drain layer.

The method may further include forming an etch stop layer under the first interlayer insulating layer, wherein the etch stop layer may serve as an etch stop when selectively removing a portion of the first interlayer insulating layer on the core region. Can be. The etch termination is performed at a portion located on the core region of the etch termination layer, and the manufacturing method further includes selectively removing a portion located on the core region of the etch termination layer serving as an etch termination. can do.

The manufacturing method may include sequentially forming a second etch stop layer and a second interlayer insulating layer covering the silicide layer, and planarizing the second interlayer insulating layer by using the second etch stop layer as an etch stop. It may further include.

According to the present invention, it is possible to prevent the manufacturing process of the entire semiconductor device from becoming very complicated, and to reduce the contact resistance of the conductive contact pads in the cell region of the semiconductor element and the source and drain of the peripheral circuit region or core region. In order to provide a method for manufacturing a semiconductor device incorporating a silicide process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements. In addition, where a layer is described as being "on" another layer or semiconductor substrate, the layer may exist in direct contact with the other layer or semiconductor substrate, or a third layer therebetween. May be interposed.

In an embodiment of the present invention, it is proposed to effectively introduce a silicide process to reduce the resistance of a semiconductor device. For example, a method of simultaneously performing a silicide process on the source and drain of a contact pad and a core region (or a peripheral circuit region) of a cell region in a semiconductor device such as a DRAM is presented. As described above, by simultaneously performing the silicide process required for different regions in the semiconductor device, the entire semiconductor device manufacturing process may be prevented from becoming more complicated and the resistance reduction effect of the silicide process may be realized to the maximum.

First embodiment

1 to 9 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device including a silicide process according to a first embodiment of the present invention.

Referring to FIG. 1, a step of introducing a semiconductor substrate 100 having a gate stack 200 is schematically illustrated. Specifically, the device isolation layer 150 for device isolation is formed on the semiconductor substrate 100. Thereafter, the gate dielectric layer 210 is introduced onto the semiconductor substrate 100 set by the device isolation layer 150, and a gate 220 and a capping layer 230 are formed thereon. Thereafter, a gate spacer 240 is formed to form the gate stack 200.

According to a method of manufacturing a semiconductor device such as a DRAM, the semiconductor substrate 100 adjacent to the gate 220 may be formed before the process of forming the gate spacer 240, for example, forming and anisotropically etching the spacer layer. An impurity layer 310 for drain and source of the transistor may be ion implanted into the transistor. The impurity layer 310 may be formed of n ⁻ conductive type in the case of NMOS.

Referring to FIG. 2, a raised source and drain layer 350 is formed. Specifically, the silicon layer is epitaxially grown from the silicon surface of the semiconductor substrate 100 exposed by the gate stack 200 using selectively epitaxial growth (SEG). Selective epitaxial growth is that silicon is not epitaxially grown from the silicon nitride of the gate spacer 240 or the silicon oxide surface of the device isolation layer 150, and the silicon layer is formed from the silicon surface of the exposed semiconductor substrate 100. It is a silicon layer growth method using epitaxial growth. By such selective epitaxial growth, a single crystal silicon layer is preferably grown from the surface of the semiconductor substrate 100 adjacent to the gate stack 200. Since the silicon layer is substantially grown from the source and the drain of the transistor, it may be referred to as a raised source and drain layer 350.

After the raised source and drain layers 350 are formed, ion implantation is performed on the raised source and drain layers 350. Such ion implantation can be performed with a high concentration of impurity doses, such as n ⁺ conductivity type. On the other hand, a high concentration of the second impurity layer (not shown) may be formed to partially overlap the first impurity layer of the core region by ion implantation of the high concentration dose. Accordingly, a lightly doped drain (LDD) structure may be formed in the transistor of the core region.

Referring to FIG. 3, a first etch stopper 410 is formed on the raised source and drain layers 350. In detail, the first etch finish layer 410 is deposited on the entire product on which the raised source and drain layers 350 are formed. The first etch stop layer 410 is mainly used as an etch stop in an etching process for selectively removing subsequent first inter layer dielectric (ILD1). Accordingly, the first etch stop layer 410 is preferably made of a material for forming ILD1, such as silicon oxide, and a material capable of achieving a sufficient etching selectivity, such as silicon nitride (Si ₃ N ₄ ). The first etch stop layer 410 is approximately 100 ?? The thickness may be formed in the form of a liner having a thickness, but the thickness may vary according to the subsequent etching process.

When the first etch stop layer 410 is preferably formed of silicon nitride, a buffer layer 415 may be used to relieve stress between the silicon nitride and the raised source and drain layers 350. Can be introduced. The buffer layer 415 may be introduced into the silicon oxide layer. If the stress is minimal, the introduction of the buffer layer 415 may be omitted.

Referring to FIG. 4, a first interlayer insulating layer 510 to be used as the ILD1 is formed. After the deposition of the first interlayer insulating layer 510, a process of planarizing the first interlayer insulating layer 510 may be introduced. This planarization process may be performed by chemical mechanical polishing (CMP).

A contact hole 515 for conductive contact is formed in the cell region by using self aligned contact etch (SAC etch). Accordingly, the contact hole 515 exposes the raised source and drain layers 350 of the cell region. The contact hole 515 is not introduced in the core region or the peripheral circuit region.

Referring to FIG. 5, the conductive contact 370 filling the contact hole 515 is formed. The conductive contact 370 is made of a silicon layer grown by selective epitaxial growth. At this time, the silicon layer may preferably be grown into a single crystal silicon layer. Thereafter, ion implantation is performed in the conductive contact 370 of the silicon. The ion implantation process may serve to provide conductivity to the conductive contact 370 and the raised source and drain layers 350 under the conductive contact 370. Such ion implantation can be performed with a high concentration of impurity doses, for example n ⁺ conductivity.

Referring to FIG. 6, an etching process of opening the core region is performed. That is, the portion of the first interlayer insulating layer 510 on the core region is etched and removed. The etching for removing the portion of the first interlayer insulating layer 510 on the core region is terminated at the portion of the first etch termination layer 410 on the core region. Subsequently, etching is continued to remove portions of the exposed first etch finish layer 410. The removal of the exposed portion of the first etch finish layer 410 is etched off the portion of the buffer layer 415 below. Then, the exposed portion of the buffer layer 415 is removed by wet etching.

By the etching process of opening the core region, the surfaces of the raised source and drain layers 350 formed on the core region are exposed.

Referring to FIG. 7, a silicide process is performed on the exposed conductive contacts 370 and the raised source and drain layers 390 in accordance with a process of self aligned silicide (SAC). For example, a cobalt layer is deposited and then thermally treated to suicide between the silicon and cobalt of the conductive contact 370 and the raised source and drain layers 390 of the core region. Thereafter, a portion of the unsilicided cobalt layer is removed to selectively form a silicide layer 390 on the upper surface of the conductive contact 370, and together with the surface of the raised source and drain layer 390 in the core region. Optionally, silicide layer 390 is also formed. Although the silicide layer 390 is described as being made of cobalt silicide (CoSi _x ), this silicide process may be performed by introducing another metal layer.

The silicide layer 390 may implement a desirable effect of reducing contact resistance, thereby reducing the resistance of the entire semiconductor device.

Referring to FIG. 8, a second etching finish layer 430 is formed to cover an upper surface of the first interlayer insulating layer 510. The second etch finish layer 430 serves as an etch finish mainly in the process of planarizing another second interlayer insulating layer forming ILD1. Therefore, it is preferable that the second etch finish layer 430 is formed of a material capable of achieving a sufficient etching selectivity with a silicon oxide, which is preferably the second interlayer insulating layer, for example, silicon nitride.

The second etch stop layer 430 preferably extends to cover the portion of the silicide layer 390 on the core region. An extended portion of the second etch finish layer 430 may also serve to prevent oxidation that may occur during annealing of the second interlayer insulating layer.

Referring to FIG. 9, an ILD1 including the first interlayer insulating layer 510 and the second interlayer insulating layer 550 is formed by forming and planarizing a second interlayer insulating layer 550 on the second etch finish layer 430. Achieve. Specifically, after depositing the second interlayer insulating layer 550 to the thickness of at least the first interlayer insulating layer 510 on the second etch finish layer 430, the second etching on the first interlayer insulating layer 510 The second interlayer insulating layer 550 is planarized using a portion of the termination layer 430 as the end of etching. Accordingly, the heights of the first interlayer insulating layer 510 and the second interlayer insulating layer 500 become substantially equal, and include the first interlayer insulating layer 510 and the second interlayer insulating layer 500. ILD1 is formed.

The semiconductor device manufacturing method according to the first embodiment of the present invention implements an effect of reducing the contact resistance of the semiconductor device by introducing a silicide process. This silicide process is performed on the upper surface of the conductive contact 370 of the cell region of the semiconductor device, and together with the silicide layer 390 in contact with the source and drain regions of the core region. To this end, the conductive contact 370 is formed by selective epitaxial growth, and the source and drain layers 350 mounted on the core region are introduced.

Some processes of this first embodiment may be modified according to the process. This modified example will be described by illustrating the following second embodiment.

Second embodiment

10 to 17 are cross-sectional views schematically illustrating a method of manufacturing a semiconductor device including a silicide process according to a second embodiment of the present invention. In the second embodiment, the same reference numerals as in the first embodiment can be understood to mean equivalent members.

First, as described in the first embodiment with reference to FIG. 1, the semiconductor substrate 100 on which the gate stack 200 is formed is introduced.

Referring to FIG. 10, a first etch stopper 410 ′ covering the gate stack 200 is formed. In detail, the first etch stop layer 410 ′ is deposited on the entire product on which the gate stack 200 is formed. The first etch termination layer 410 ′ is mainly used as an etch termination in an etching process for selectively removing subsequent ILD1, for example, an etching process for opening a core region. Accordingly, the first etch stop layer 410 'is preferably made of a material for forming ILD1, for example, silicon oxide and a material capable of achieving a sufficient etching selectivity, for example, silicon nitride (Si ₃ N ₄ ). The first etch stop layer 410 ′ is approximately 100 ?? The thickness may be formed in the form of a liner having a thickness, but the thickness may vary according to the subsequent etching process.

When the first etch stop layer 410 ′ is preferably formed of silicon nitride, a buffer layer may be used to alleviate stress that may occur between silicon nitride and silicon, which preferably forms the semiconductor substrate 100. layer: 415 '). The buffer layer 415 'may be introduced into the silicon oxide layer, but in some cases, the introduction of the buffer layer 415' may be omitted.

Referring to FIG. 11, a first interlayer insulating layer 510 ′ to be used as ILD1 is formed. After the deposition of the first interlayer insulating layer 510 ′, the process of planarizing the first interlayer insulating layer 510 ′ may be introduced into the CMP process.

Referring to FIG. 12, after the first interlayer insulating layer 510 ′ is planarized, a contact hole 515 ′ for conductive contact is formed in the cell region using self aligned contact etching (SAC etch). The planarization may be performed by CMP or the like, and may be performed by using the first etch finish layer 410 ′ as an etch finish (or polishing end).

The contact hole 515 ′ exposes a surface of a portion of the semiconductor substrate 100 adjacent to the gate stack 200 in the cell region, that is, a portion of the semiconductor substrate 100 in the source and drain regions. The contact hole 515 'is not introduced in the core region or the peripheral circuit region.

Referring to FIG. 13, an etching process of opening the core region is performed. That is, a photoresist pattern (not shown) that exposes the core region by a photo process is introduced as an etch mask to etch and remove a portion of the first interlayer insulating layer 510 'on the core region. The etching for removing the portion of the first interlayer insulating layer 510 'on the core region is terminated at the portion of the first etch termination layer 410' on the core region. Subsequently, etching is continued to completely remove the exposed portion of the first etching termination layer 410 '. The removal of the exposed portion of the first etch stop layer 410 ′ ends the etch at the portion of the buffer layer 415 below. Then, the exposed portion of the buffer layer 415 'is removed by wet etching.

By the etching process of opening the core region, the surface of the semiconductor substrate 100 adjacent to the gate stack 200 formed on the core region, that is, the surface of the semiconductor substrate 100 in the source and drain regions is exposed. .

Referring to FIG. 14, the silicon layer is selectively epitaxially grown (SEG) from the surface of the semiconductor substrate 100 exposed in the cell region and the core region (or the peripheral circuit region). Selective epitaxial growth is that silicon is not epitaxially grown from the silicon nitride of the gate spacer 240 or the silicon oxide surface of the device isolation layer 150, and the silicon layer is formed from the silicon surface of the exposed semiconductor substrate 100. It is a silicon layer growth method using epitaxial growth. Accordingly, the raised source and drain layers 360 selectively grown from the surface of the semiconductor substrate 100 exposed by the contact holes 515 'in the cell region and from the exposed surface of the semiconductor substrate 100 in the core region. ) Is formed.

After the raised source and drain layers 360 are formed in this manner, ion implantation for imparting conductivity to the raised source and drain layers 360 is performed. Such ion implantation can be performed with a high concentration of impurity doses, such as n ⁺ conductivity type. Accordingly, the raised source and drain layers 360 of the cell region may also serve as conductive contacts to substantially fill the contact holes 515 '.

Referring to FIG. 15, a silicide process is performed on the raised source and drain layers 360 in accordance with a process of self-aligned silicide (SAC). For example, a silicide is formed between silicon and cobalt of the source and drain layers 360 which are heated by depositing a cobalt layer and then performing heat treatment. Thereafter, the unsilicided cobalt layer portion is removed to selectively form a silicide layer 390 'on the surface of the raised source and drain layers 360 of the cell region and the core region simultaneously. Although the silicide layer 390 ′ is described as being made of cobalt silicide (CoSi _x ), this silicide process may be performed by introducing another metal layer.

The silicide layer 390 ′ implements a desirable effect of reducing contact resistance, thereby reducing the resistance of the entire semiconductor device.

Referring to FIG. 16, a second etching finish layer 430 ′ covering an upper surface of the first interlayer insulating layer 510 ′ is formed. The second etch stop layer 430 ′ may mainly serve as an etch stop in the process of planarizing another second interlayer insulating layer constituting ILD1. Therefore, it is preferable that the second etch finish layer 430 'is made of a material capable of achieving a sufficient etch selectivity with a silicon oxide, which preferably forms the second interlayer insulating layer. The second etch finish layer 430 ′ preferably extends to cover the silicide layer 390 ′. The extended second etch stop layer 430 ′ may also serve to prevent oxidation that may occur during annealing of the second interlayer insulating layer.

Referring to FIG. 17, the first interlayer insulating layer 510 ′ and the second interlayer insulating layer 550 ′ may be formed and planarized on the second etching finish layer 430 ′. ILD1 consists of. Specifically, after depositing the second interlayer insulating layer 550 ′ on the second etch stop layer 430 ′, the second etch finish layer (on the first interlayer insulating layer 510 or on the gate stack 200 ( The second interlayer insulating layer 550 'is planarized using the portion 430') as the end of etching. As a result, an ILD1 including the first interlayer insulating layer 510 'and the second interlayer insulating layer 500' is formed.

The semiconductor device manufacturing method according to the second embodiment of the present invention implements the silicide process to reduce the contact resistance of the semiconductor device. This silicide process is performed to self-align at the surface of the raised source and drain layers 360 introduced together in the cell and core regions of the semiconductor device.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, It is clear that the deformation | transformation and improvement are possible by the person of ordinary skill in the art within the technical idea of this invention.

According to the present invention described above, after introducing a source and drain layer raised by selective epitaxial growth (SEG) or introducing a conductive contact, it is possible to perform a silicide process by self-alignment on their surface. Accordingly, the contact resistance can be effectively reduced. Furthermore, the silicide process can be performed simultaneously in the cell region and the core region (or peripheral circuit region), thereby preventing the entire semiconductor manufacturing process from becoming very complicated and effectively introducing the silicide process during the manufacturing process.

Claims (16)

Forming a gate stack on a semiconductor substrate including a cell region and a core region; Growing a source and drain layer raised from the surface of the semiconductor substrate exposed to the gate stack to selectively epitaxial growth (SEG); Forming an interlayer insulating layer covering the raised source and drain layer; Forming a conductive contact through said interlayer insulating layer and electrically connected to said raised source and drain layer of said cell region; Selectively removing portions of the interlayer dielectric layer on the core region to expose an upper surface of a raised source and drain layer of the core region; And And performing a silicide process on the exposed surface of the raised source and drain layers and the surface of the conductive contact at the same time to form a silicide layer. The method of claim 1, wherein forming the conductive contact Forming a contact hole in the interlayer insulating layer exposing the raised source and drain layers of the cell region below; And Growing said conductive contact in selective epitaxial growth (SEG) from said raised source and drain layer surfaces. The method of claim 2, And performing ion implantation into the conductive contacts grown after the growing of the conductive contacts. The method of claim 1, And growing the raised source and drain layers and performing ion implantation into the raised source and drain layers. The method of claim 1, The method may further include forming an etch stop layer under the interlayer insulating layer. And the etch stop layer serves as an etch stop when selectively removing the interlayer insulating layer portion on the core region. The method of claim 5, The etching termination is at a portion located on the core region of the etching termination layer, And selectively removing a portion located on the core region of the etch finish layer acting as the etch stop. The method of claim 5, And forming a buffer layer under the etch stop layer. The method of claim 7, wherein The etching finish layer comprises a silicon nitride layer, the buffer layer is a semiconductor device manufacturing method characterized in that it comprises a silicon oxide layer. The method of claim 1, Sequentially forming a second etch stop layer and a second interlayer insulating layer covering the silicide layer; And And planarizing the second interlayer insulating layer using the second etch stop layer as an etch stop. Forming a gate stack on a semiconductor substrate including a cell region and a core region; Forming a first interlayer insulating layer covering the gate stack; Selectively etching the first interlayer insulating layer to form a contact hole exposing the semiconductor substrate portion of the core region and exposing the semiconductor substrate portion of the cell region; Growing a source and drain layer raised from the exposed surface of the semiconductor substrate to selectively epitaxial growth (SEG); Forming a silicide layer by performing a silicide process on the raised source and drain layer; And Forming a second interlayer insulating layer covering the silicide layer and having a planarized surface. The method of claim 10, And growing the raised source and drain layers and then performing ion implantation into the raised source and drain layers. The method of claim 10, The method may further include forming an etch stop layer under the first interlayer insulating layer. And the etch stop layer acts as an etch stop when selectively removing the first interlayer insulating layer portion on the core region. The method of claim 12, The etching termination is at a portion located on the core region of the etching termination layer, And selectively removing a portion located on the core region of the etch finish layer acting as the etch stop. The method of claim 12, And forming a buffer layer under the etch stop layer. The method of claim 14, The etching finish layer comprises a silicon nitride layer, the buffer layer is a semiconductor device manufacturing method, characterized in that comprises a silicon oxide layer. The method of claim 1, Sequentially forming a second etch stop layer and a second interlayer insulating layer covering the silicide layer; And And planarizing the second interlayer insulating layer using the second etch stop layer as an etch stop.